Midterm I March 12, 2003 CS152 Computer Architecture and Engineering
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1 University of California, Berkeley College of Engineering Computer Science Division EECS Spring 23 John Kubiatowicz Midterm I March 2, 23 CS2 Computer Architecture and Engineering Your Name: SID Number: Discussion Section: Problem Possible Score Total
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3 Problem : Short Answer Problem a [3 pts]: What is Amdhal s law? Give a formula and define the terms. How is this useful? Amdal s law: speed up = F is the part that you speed up n is the speed up ratio F ( F ) + n The Amdal s law tells you can NOT speed up too much the whole system by speeding up only one part Problem b [3 pts]: What are setup and hold-time and how can they be violated in a synchronous circuit? Can you still use a chip that is experiencing hold-time violations? How about setup violations? T setup is the time that input signal should arrive before the clock edge T hold is the time that input signal should keep unchanged after the clock edge If the clock cycle time is not long enough, you could have Setup time violation. To avoid setup violation, the cycle time T clk should satisfy: T clk >T clk_q +T max +T setup +T skew +T j If the combinational logic delay is too short, you could have hold time violation. The following has to be satisfied to avoid hold time violation: T clk_q +T min >T skew +T hold If setup time is violated, you can slow down the clock to make the chip work If hold time is violated, you can NOT make the chip work Problem c [2 pts]: Is the multi-cycle data path always faster than the single-cycle data path? Explain. NO, for example: lw for MIPs in multi-cycle data path will be slower than single-cycle data path for more T clk_q overhead is introduced in multi-cycle data path. Problem d [3 pts]: What are precise interrupts and why is it easy to provide them for our multi-cycle data path? Precise interrupts means that the instructions before offending instruction are executed but no instructions are executed after the offending instruction. In our multi-cycle data path, it is easy to provide precise interrupts for interrupts only occur before WB stage and instructions are executed in order. 3
4 Problem e [3 pts]: Suppose that you have analyzed a benchmark that runs on your company s processor. This processor runs at MHz and has the following characteristics: Instruction Type Frequency (%) Cycles Arithmetic and logical 4 Load and Store 3 2 Branches 2 Floating Point 2 What is the CPI and MIPS rating of this processor running this benchmark? CPI=*.4+2*.3+*.2+2*.=2.4 MIPS=/2.4=28 MIPS Problem f [2 pts]: What is the technique used for a carry-select adder and how can it be used in general to speed up hardware (hint: this is a very general technique to make a time space tradeoff) In carry select adder, you pre-compute the addition both with carry in and. Then, the correct result is selected by the late arrival carry in. In general, you can throw in more hardware, do parallel pre-computing and select the correct by using late arrival signal, which can speed up the hardware. Problem g [3pts]: What does it mean for a branch to have a delay slot, and why does it complicate the servicing of interrupts? Delay slot means that the instruction right after branch is always executed regardless the branch is taken or not. If the instruction in the delay causes the exception, you have to re-evaluate the branch to figure out the correct next executing instruction after the interrupt service. 4
5 Problem h[3pts]: The Clark paper on testing talked about using randomness in at least two different ways during testing of the VAX. What were they?. Use random vector 2. Insert random errors Problem i [3 pts]: The -bit Booth algorithm recodes one of the operands of a multiplier from binary into trinary logic with symbols:,, and. The transformation occurs one bit at a time, as given in class: Cur Prev Out Suppose we encode 3 bits at a time. Finish filling out the following transformation table: Cur Prev Out
6 Problem 2: Delay For a Full Adder A key component of an ALU is a full adder. A symbol for a full adder is: A B C out Full Adder C in S Problem 2a [pts]: Implement a full adder using as few 2-input AND, OR, and XOR gates as possible. Keep in mind that the Carry In signal may arrive much later than the A or B inputs. Thus, optimize your design (if possible) to have as few gates between Carry In and the two outputs as possible: A B S C in C out 6
7 Assume the following characteristics for the gates: AND: Input load: ff, Propagation delay: TPlh=.4ns, TPhl=.4ns, Load-Dependent delay: TPlhf=.2ns, TPhlf=.2ns OR: Input load: ff Propagation delay: TPlh=.2ns, TPhl=.6ns Load-Dependent delay: TPlhf=.2ns, TPhlf=.2ns XOR: Input load: 2fF, Propagation delay: TPlh=.8ns, TPhl=.8ns Load-Dependent delay: TPlhf=.4ns,TPhlf=.42ns Problem 2b [3pts]: Compute the input load for each of the 3 inputs to your full adder: C A =C B =Ccin=2fF+fF=3fF Problem 2c [4pts]: Identify two critical paths from the inputs to the Sum and the Carry Out signal. Compute the propagation delays for these critical paths based on the information given above. (You will have 2 numbers for each of these two paths): Notice A and B are symmetric inputs Critical path from inputs to the sum: since XOR is slow compared to AND and OR, the critical path for sum is A->XOR->XOR->S Critical path from inputs to the carry out: since XOR is slow compared to AND and OR, the critical path for sum is A->XOR->AND->OR->Cout W/o wire delay caculation TphlAS=.8+.42*(2+)+.8=2.86ns TplhAS=.8+.42*(2+)+.8=2.86ns TphlAC out =.6+.2* *(2+)+.8=3.48ns TplhAC out =.2+.2* *(2+)+.8=3.8ns W/ wire delay caculation TphlAS=.8+.42*(2+)*2+.8=4.2ns TplhAS=.8+.42*(2+)*2+.8=4.2ns TphlAC out =.6+.2*2* *(2+)*2+.8=.6ns TplhAC out =.2+.2*2* *(2+)*2+.8=4.76ns Problem 2d [2pts]: Compute the Load Dependent delay for your two outputs. TphlASf=.42ns/fF, TplhASf=.4ns/fF, TplhAC out f=.2ns/ff TphlAC out f=.2ns/ff 7
8 Problem 2e [6pts]: Suppose we wish to build a fast adder. One component might be a 4-bit adder with propagate and generate signals (such as might be used for carry-lookahead logic). Construct this adder as a 4-bit ripple adder internally (you can use your full-adders) with separate propagate and generate outputs. Let the output carry be a function of the propagate and generate signals. Draw a circuit for this component and compute the propagation delay for the slowest signal. C out [FAST] A[3:] B[3:] 4-BIT Adder C in A B P S S[3:] G P Cin C out G A3 B3 A2 B2 A B A B bit full adder bit full adder bit full adder bit full adder Cin S3 S2 S S P P P2 P3 C4 Notice that the slowest path should be A->S3 for the XOR gate is much slower than AND/OR used for generating Carry out C 4 (which uses 7 AND/OR levels). Assuming that P drives AND gate, P drive 2 AND gates, P2 drives 3 AND gates and P3 drives 4 AND gates for C4 generation. Notice the implementation is NOT unique! W/o wiring delay: TphlCinS3=[ * *(*2+2)]+2*(.2* *2+.6)+.2*3 +.8=9.22ns W/ wiring delay: TphlCinS3=[ **2+.8+2*.42*(*2+2)]+2*(.2*3* *2*2+.6)+. 2*3*2+.8=3.84ns 8
9 Problem 3: Non-Restoring Division Here is the pseudo-code for an unsigned division algorithm. It is the non-restoring version of the last divider that we developed. Assume that quotient and remainder are -bit global values. As far as inputs are concerned dividend is bits wide, while divisor is no more than 3 bits. divide(dividend, divisor) { int count; /* Missing initialization instructions */ MOBIUS64(remainder,quotient); while (count > ) { count--; /* Low bit of quotient is inverted sign of remainder*/ if (quotient & x) remainder = remainder - divisor; else remainder = remainder + divisor; } MOBIUS64(remainder,quotient); } /* Missing trailing instructions */ The MOBIUS64(hi,lo) instruction rotates the 64-bit value <hi,lo> around to the left bit, wrapping the top bit of hi back to the bottom of lo and inverting it in the process. So, for instance: MOBIUS64(xFFFFFFFF, xff) xfffffffe, xfe And: MOBIUS64(xFFFFFFF, xff) xffffffe, xff Problem 3a [pts]: Implement MOBIUS64($t, $t) as 6 MIPS instructions. Assume $t2 contains the constant x8. Hint: what can different flavors of slt/sltu do to help? slt $t3, $t,$ sltu $t4, $t, $t2 sll $t,$t, sll $t,$t, addiu, $t,$t, $t4 addiu, $t,$t, $t3 Problem 3b [pts]: The divide algorithm is incomplete. It is missing some initialization and some final code. What is missing? (Careful what if the remainder is negative?) Initialization: Remainder =; Quotient Dividend; Count=; Trail: Remainder =Remainder>>; If (!(Quotient&x)){ Remainder=Remainder x8; Remainder+=Divisor; } 9
10 Problem 3c [pts]: Assume that you have a MIPS processor that is missing the divide instruction. Assume that dividend and divisor are in $a and $a respectively, and that remainder and quotient are returned in registers $v and $v respectively. You can use MOBIUS64 as a pseudo-instruction that takes 3 registers (don t forget the constant in $t2). Make sure to adher to MIPS register conventions, and optimize the loop as much as possible. Divide: loop: mov $t, $ mov $t, $a ori $t8, lui $t2, x8 MOBIUS64($t,$t) beq $t8, $, DONE addi $t8, $t8, - andi $t3, $t, beq $t3, $, MOBIUSNEG j loop MOBIUSNEG: add $t, $t, $a j loop DONE: mov $v, $t9 mov $v, $t srl $v,$v, andi $t3, $v, bne $t3,$, exit or $v,$v, $t2 add $v,$v,$a exit: jr $ra Problem 3d [4pts]: How will this algorithm have to change if the divisor is allowed to be bits in size? Check for the bit value for divisor and treat separately Either Q=, Remainder=Dividend-Divisor Or Q=, Remainder=Divisor
11 Problem 4: New instructions for a multi-cycle data path PCWr PC IorD PCWrCond Zero MemWr RAdr Ideal Memory WrAdr Din Dout IRWr Instruction Reg Mem Data Reg RegDst Rs Rt Rt Rd RegWr Ra Rb busa A Reg File Rw busw busb B << 2 ALUSelA 4 PCSrc 2 3 Zero ALU ALU Control ALU Out Imm 6 ExtOp Extend MemtoReg ALUOp The Multi-Cycle datapath developed in class and the book is shown above. In class, we developed an assembly language for microcode. It is included here for reference: Field Name Values For Field Function of Field Add ALU Adds ALU Sub ALU subtracts Func ALU does function code (Inst[:]) Or ALU does logical OR SRC PC PC st ALU input rs R[rs] st ALU input nd ALU input rt R[rt] 2 nd ALU input SRC2 Extend sign ext imm6 (Inst[:]) 2 nd ALU input Extend zero ext imm6 (Inst[:]) 2 nd ALU input ExtShft 2 nd ALU input = sign extended imm6 << 2 rd-alu ALUout R[rd] ALU Dest rt-alu ALUout R[rt] rt-mem Mem input R[rt] Read-PC Read Memory using the PC for the address Memory Read-ALU Read Memory using the ALUout register for the address Write-ALU Write Memory using the ALUout register for the address MemReg IR Mem input IR PC Write ALU ALU value PCibm ALUoutCond If ALU Zero is true, then ALUout PC Seq Go to next sequential microinstruction Sequence Fetch Go to the first microinstruction Dispatch Dispatch using ROM ALUSelB
12 In class, we made our multicycle machine support the following six MIPS instructions: op rs rt rd shamt funct = MEM[PC] op rs rt Imm6 = MEM[PC] INST Register Transfers ADDU R[rd] R[rs] + R[rt]; PC PC + 4 SUBU R[rd] R[rs] - R[rt]; PC PC + 4 ORI R[rt] R[rs] + zero_ext(imm6); PC PC + 4 LW R[rt] MEM[ R[rs] + sign_ext(imm6)]; PC PC + 4 SW MEM[R[rs] + sign_ext(imm6)] R[rs]; PC PC + 4 BEQ if ( R[rs] == R[rt] ) then PC PC sign_ext(imm6) else PC PC + 4 For your reference, here is the microcode for two of the 6 MIPS instructions: Label ALU SRC SRC2 ALUDest Memory MemReg PCWrite Sequence Fetch Add PC 4 ReadPC IR ALU Seq Dispatch Add PC ExtShft Dispatch RType Func rs rt Seq rd-alu Fetch BEQ Sub rs rt ALUoutCond Fetch In this problem, we are going to add five new instructions to this data path: jal <const> PC zero_ext(instr[2:]) addiu $rt, $rs, <const> R[3] PC + 4 R[rt] R[rs] + sign_ext(imm6) multu $rs, $rt <hi,lo> R[rs] R[rt] mfhi $rs R[rs] <hi> mflo $rs R[rs] <lo>. The jal instruction is familiar to you from the normal MIPS instruction set. 2. The addiu instruction is also a normal MIPS instruction that has an immediate value 3. The multu instruction is an unsigned multiply, and the mfhi/mflo instructions are for getting the result. 2
13 Problem 4a [pts]: Describe/sketch the modifications needed to the datapath for the new instructions. Assume that the original datapath had only enough functionality to implement the original 6 instructions. Try to add as little hardware as possible. In particular, you must use the existing ALU for multiply. You can showing additions to the data path you do not need to completely redraw it. Make sure that you are very clear about your changes. Hint: you need to add hi and lo registers. They can be made from shift-registers. Your CPI for multiply should be no more than 4. So: how will you loop times for multu??? jal.expand RegW mux to include $r3 2.expand BusW mux to include data from pc register 3.expand PC source mux to include jump address PCsrc 3 R t R d M u x RegW R W BusW PC MEM ALUout RegtoMem ALU ALUout PC[3:28] ShiftedExtImm M u x PC addiu No change is needed to implement this instruction multu $rs, $rt. pc<-pc+4 2. ALUout<-pc+ShiftedExImm 3. lo<-r[rt],hi<-,a<-r[rs],count<- 4. hi<-hi+ lo[]= =?, A; count<-count-. srl ovm hi lo, 6. hi<hi+ lo[]= =?, A; count<-count- HiSr OVM hi WriteHi lo WriteLo Shift R[rt] A Lo[] PC M u x M u x ALUsrcA 4 B ExImm shifteximm Hi M u x ALUsrcB load dec ALU Counter Zero mfhi mflo BusW Hi Lo MEM ALUout 3 RegtoMem Rs R t R d M u x RegW R W
14 Problem 4b [6pts]: Draw a block diagram of as microcontroller that will support the new instructions (it will be slightly different than that required for the original instructions). Include sequencing hardware, the dispatch ROM, the microcode ROM, and decode blocks to turn the fields of the microcode into control signals. Hint: you will need to provide a branching facility to your sequencer. Make sure to include this functionality! Adder micropc - Adder M u x µaddress Select Logic ROM Opcode Counter is not zero ALUop SRC SRC2 ALUdest Mem MemReg PCWrite Sequence Multu
15 Problem 4c [4pts]: Describe changes to the microinstruction assembly language for these new instructions. How wide are your microinstructions now? ALUop: no change (3bits) SRC: bit->2bits (including data) SRC2: no change (3bits, but the mux is expanded) ALUdest: 2bits->3bits(supporting r3-pc, rs-hi,rs-lo) Mem: no change (2bits) MemReg: no change (bit) PCWrite: no change (2bits, but support jump address now) Sequence: no change (2bist, but support dec ) Multu: new 3bits(support load, shift, WriteHi,WriteLo, HiSrc) New microinstruction length is : =2 Problem 4d [pts]: Write complete microcode for the new instructions. Include the Fetch and Dispatch microinstructions. If any of the microcode for the original instructions must change, explain how. label ALU SRC SRC2 ALUdest Mem MemReg PCwrite Sequence MULTU fetch add pc 4 ReadPC IR ALU seq dispatch add pc shiftext dispatch jal 3-pc jumpaddr fetch addiu add rs extimm seq rt-alu fetch multu Load, WriteHi, Writelo, HiSrc= add or rs hi seq Count--,WriteHi,HiSrc= dec shift mfhi rs-hi fetch mflo rs-lo fetch
16 Problem 4e [Extra Credit: pts]: Describe a (relatively) small change that will allow you to implement the signed mult instruction (think Booth!). Be complete with your answer (datapath/microcode, etc). The microcode will be quite similar to the non-booth encoding case. but one reset signal is introduced to reset prev lo[] bit register to. WriteHi WriteLo Shift OVM hi lo Prev lo[] R[rt] Reset ALU ALUsrcA Lo[:] A -A M u x PC M u x 6
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19 EXTRA SHEET FOR PROBLEM 4: FEEL FREE TO REMOVE PCWr PC IorD PCWrCond Zero MemWr RAdr Ideal Memory WrAdr Din Dout IRWr Instruction Reg Mem Data Reg RegDst Rs Rt Rt Rd RegWr Ra Rb busa A Reg File Rw busw busb B << 2 ALUSelA 4 PCSrc 2 3 Zero ALU ALU Control ALU Out Imm 6 ExtOp Extend MemtoReg The Multi-Cycle datapath developed in class and the book is shown above. In class, we developed an assembly language for microcode. It is included here for reference: Field Name Values For Field Function of Field Add ALU Adds ALU Sub ALU subtracts Func ALU does function code (Inst[:]) Or ALU does logical OR SRC PC PC st ALU input rs R[rs] st ALU input nd ALU input rt R[rt] 2 nd ALU input SRC2 Extend sign ext imm6 (Inst[:]) 2 nd ALU input Extend zero ext imm6 (Inst[:]) 2 nd ALU input ExtShft 2 nd ALU input = sign extended imm6 << 2 rd-alu ALUout R[rd] ALU Dest rt-alu ALUout R[rt] rt-mem Mem input R[rt] Read-PC Read Memory using the PC for the address Memory Read-ALU Read Memory using the ALUout register for the address Write-ALU Write Memory using the ALUout register for the address MemReg IR Mem input IR PC Write ALU ALU value PCibm ALUoutCond If ALU Zero is true, then ALUout PC Seq Go to next sequential microinstruction Sequence Fetch Go to the first microinstruction Dispatch Dispatch using ROM ALUSelB ALUOp 9
20 EXTRA SHEET FOR PROBLEM 4: FEEL FREE TO REMOVE In class, we made our multicycle machine support the following six MIPS instructions: op rs rt rd shamt funct = MEM[PC] op rs rt Imm6 = MEM[PC] INST Register Transfers ADDU R[rd] R[rs] + R[rt]; PC PC + 4 SUBU R[rd] R[rs] - R[rt]; PC PC + 4 ORI R[rt] R[rs] + zero_ext(imm6); PC PC + 4 LW R[rt] MEM[ R[rs] + sign_ext(imm6)]; PC PC + 4 SW MEM[R[rs] + sign_ext(imm6)] R[rs]; PC PC + 4 BEQ if ( R[rs] == R[rt] ) then PC PC sign_ext(imm6) else PC PC + 4 For your reference, here is the microcode for two of the 6 MIPS instructions: Label ALU SRC SRC2 ALUDest Memory MemReg PCWrite Sequence Fetch Add PC 4 ReadPC IR ALU Seq Dispatch Add PC ExtShft Dispatch RType Func rs rt Seq rd-alu Fetch BEQ Sub rs rt ALUoutCond Fetch In this problem, we are going to add five new instructions to this data path: jal <const> PC zero_ext(instr[2:]) addiu $rt, $rs, <const> R[3] PC + 4 R[rt] R[rs] + sign_ext(imm6) multu $rs, $rt <hi,lo> R[rs] R[rt] mfhi $rs R[rs] <hi> mflo $rs R[rs] <lo> 4. The jal instruction is familiar to you from the normal MIPS instruction set.. The addiu instruction is also a normal MIPS instruction that has an immediate value 6. The multu instruction is an unsigned multiply, and the mfhi/mflo instructions are for getting the result. 2
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