361 multipath..1. EECS 361 Computer Architecture Lecture 10: Designing a Multiple Cycle Processor

Transcription

1 36 multipath.. EECS 36 Computer Architecture Lecture : Designing a Multiple Cycle Processor

2 Recap: A Single Cycle Datapath We have everything except control signals (underline) Today s lecture will show you how to generate the control signals RegDst busw Clk RegWr Rd imm6 Rs Rw Ra Rb -bit Registers 6 busb Extender npc_sel Clk Src Instruction Fetch Unit ctr Data In Clk Instruction<3:> <2:2> WrEn Rs <6:2> MemWr Adr Data Rd <:> <:> Imm6 MemtoReg 36 multipath..2 ExtOp

3 Recap: PLA Implementation of the Main op<>.. op<>.. op<>.. op<>.. op<>.. op<>.. <> <> <> <> <> op<> R-type ori lw sw beq jump RegWrite Src RegDst MemtoReg MemWrite Branch Jump ExtOp op<2> op<> op<> 36 multipath..3

4 The Big Picture: Where are We Now? The Five Classic Components of a Computer Processor Input Datapath Output Today s Topic: Designing the Datapath for the Multiple Clock Cycle Datapath 36 multipath..

5 Outline of Today s Lecture Recap and Introduction Introduction to the Concept of Multiple Cycle Processor Multiple Cycle Implementation of R-type Instructions What is a Multiple Cycle Delay Path and Why is it Bad? Multiple Cycle Implementation of Or Immediate Multiple Cycle Implementation of Load and Store Putting it all Together 36 multipath..

6 Abstract View of our single cycle processor Next PC PC Instruction Fetch Data Mem Register Fetch Mem Access Reg. Wrt MemWr npc_sel Equal ExtOp Src ctr RegDst RegWr Result Store op Main fun control Ext MemWr MemRd looks like a FSM with PC as state 36 multipath..6

7 What s wrong with our CPI= processor? Arithmetic & Logical PC Inst Reg File mux mux setup Load PC Inst Reg File mux Data Mem muxsetup Critical Path Store PC Inst Reg File mux Data Mem Branch PC Inst Reg File cmp mux Long Cycle Time All instructions take as much time as the slowest Real memory is not so nice as our idealized memory cannot always get the job done in one (short) cycle 36 multipath..7

8 Drawbacks of this Single Cycle Processor Long cycle time: Cycle time must be long enough for the load instruction: - PC s Clock -to-q + - Instruction Access Time + - Register File Access Time + - Delay (address calculation) + - Data Access Time + - Register File Setup Time + - Clock Skew Cycle time is much longer than needed for all other instructions. Examples: R-type instructions do not require data memory access Jump does not require operation nor data memory access 36 multipath..8

9 Overview of a Multiple Cycle Implementation The root of the single cycle processor s problems: The cycle time has to be long enough for the slowest instruction Solution: Break the instruction into smaller steps Execute each step (instead of the entire instruction) in one cycle - Cycle time: time it takes to execute the longest step - Keep all the steps to have similar length This is the essence of the multiple cycle processor The advantages of the multiple cycle processor: Cycle time is much shorter Different instructions take different number of cycles to complete - Load takes five cycles - Jump only takes three cycles Allows a functional unit to be used more than once per instruction 36 multipath..9

10 The Five Steps of a Load Instruction Instruction Fetch Instr Decode / Address Data Reg Wr Clk PC Rs,, Rd, Op, Func ctr Old Value Clk-to-Q New Value Old Value Old Value Reg. Fetch Instruction Access Time New Value Delay through Logic New Value ExtOp Old Value New Value Src Old Value New Value RegWr Old Value New Value Register File Access Time Old Value New Value Delay through Extender & busb Old Value New Value Delay Address Old Value New Value Data Access Time busw Old Value New 36 multipath.. Register File Write Time

11 Register File & Write Timing: vs. Reality In previous lectures, register file and memory are simplified: Write happens at the clock tick Address, data, and write enable must be stable one set-up time before the clock tick WrEn Adr Din Dout In real life: Neither register file nor ideal memory has the clock input The write path is a combinational logic delay path: - Write enable goes to and Din settles down - write access delay - Din is written into mem[address] Important: Address and Data must be stable BEFORE Write Enable goes to Clk WrEn Adr Din Dout 36 multipath..

12 Race Condition Between Address and Write Enable This real (no clock input) register file may not work reliably in the single cycle processor because: We cannot guarantee Rw will be stable BEFORE RegWr = There is a race between Rw (address) and RegWr (write enable) Ra RegWr Rb Reg File Rw busb busw The real (no clock input) memory may not work reliably in the single cycle processor because: We cannot guarantee Address will be stable BEFORE WrEn = There is a race between Adr and WrEn WrEn Adr Din Dout 36 multipath..2

13 How to Avoid this Race Condition? Solution for the multiple cycle implementation: Make sure Address is stable by the end of Cycle N Assert Write Enable signal ONE cycle later at Cycle (N + ) Address cannot change until Write Enable is disasserted 36 multipath..3

14 Dual-Port Dual Port Independent Read (RAdr, Dout) and Write (WAdr, Din) ports Read and write (to different location) can occur at the same cycle Read Port is a combinational path: Read Address Valid --> Read Access Delay --> Data Out Valid Write Port is also a combinational path: MemWrite = --> Write Access Delay --> Data In is written into location[wradr] 3 MemWr RAdr<:> <3:2> WrAdr Din Dout 36 multipath..

15 Questions and Administrative Matters 36 multipath..

16 Instruction Fetch Cycle: In the Beginning Every cycle begins right AFTER the clock tick: Clk mem[pc] PC<3:> + You are here! One Logic Clock Cycle PCWr=? Clk PC MemWr=? RAdr WrAdr Dout Din IRWr=? Instruction Reg op=? 36 multipath..6 Clk

17 Instruction Fetch Cycle: The End Every cycle ends AT the next clock tick (storage element updates): IR <-- mem[pc] PC<3:> <-- PC<3:> + Clk One Logic Clock Cycle PCWr= You are here! Clk PC MemWr= RAdr WrAdr Din Dout IRWr= Instruction Reg Op = Add Clk 36 multipath..7

18 PCWr= PC Instruction Fetch Cycle: Overall Picture RAdr WrAdr Din Dout Instruction Reg Ifetch Op=Add : PCWr, IRWr x: PCWrCond RegDst, Mem2R Others: s PCWrCond=x PCSrc= BrWr= IorD= MemWr= IRWr= SelA= Target busb 2 3 SelB= Op=Add 36 multipath..8

19 Register Fetch / Instruction Decode <- RegFile[rs] ; busb <- RegFile[rt] ; is not being used: ctr = xx PCWr= PC IorD=x PCWrCond= MemWr= RAdr WrAdr Din Dout Go to the Op Func IRWr= Instruction Reg 6 6 RegDst=x Rs Rd Imm 6 RegWr= Ra Rb Reg File Rw busw busb SelA=x PCSrc=x 2 3 SelB=xx Op=xx 36 multipath..9

20 Register Fetch / Instruction Decode (Continue) <- Reg[rs] ; busb <- Reg[rt] ; Target <- PC + SignExt(Imm6)* PCWr= PC Beq ype Ori IorD=x 36 multipath..2 PCWrCond= : MemWr= RAdr WrAdr Din Dout Op IRWr= Instruction Reg 6 Func 6 RegDst=x Rs Rd Imm 6 ExtOp= Extend RegWr= Ra Rb Reg File Rw Rfetch/Decode Op=Add : BrWr, ExtOp SelB= x: RegDst, PCSrc IorD, MemtoReg Others: s busw busb SelA= << 2 PCSrc=x 2 3 SelB= BrWr= Target Op=Add

21 Branch Completion if ( == busb) PCWr= PC PC <- Target IorD=x PCWrCond= MemWr= RAdr WrAdr Din Dout IRWr= Instruction Reg RegDst=x Rs Rd BrComplete Op=Sub SelB= x: IorD, Mem2Reg RegDst, ExtOp : PCWrCond SelA PCSrc RegWr= Ra Rb Reg File Rw busw busb SelA= << 2 PCSrc= 2 3 BrWr= Target 36 multipath..2 Imm 6 ExtOp=x Extend SelB= Op=Sub

22 Instruction Decode: We have a R-type! Next Cycle: R-type Execution PCWr= PC Beq ype Ori IorD=x 36 multipath..22 PCWrCond= : MemWr= RAdr WrAdr Din Dout Op IRWr= Instruction Reg 6 Func 6 RegDst=x Rs Rd Imm 6 ExtOp= Extend RegWr= Ra Rb Reg File Rw busw busb SelA= << 2 PCSrc=x 2 3 SelB= BrWr= Target Op=Add

23 R-type Execution Output <- op busb PCWr= PCWrCond= ExtOp PCSrc=x BrWr= IorD=x MemWr= IRWr= RegDst= RegWr= SelA= Target PC RAdr WrAdr Din Dout Instruction Reg Rs Rd RExec : RegDst SelA SelB= Op=ype x: PCSrc, IorD MemtoReg Ra Rb Reg File Rw busw busb << Imm 6 ExtOp=x Extend MemtoReg=x Op=ype SelB= 36 multipath..23

24 R-type Completion R[rd] <- Output PCWr= PCWrCond= ExtOp PCSrc=x BrWr= IorD=x MemWr= IRWr= RegDst= RegWr= SelA= Target PC RAdr WrAdr Din Dout Instruction Reg Rs Rd Rfinish Op=ype : RegDst, RegWr sela SelB= x: IorD, PCSrc Ra Rb Reg File Rw busw busb << Imm 6 ExtOp=x Extend MemtoReg= Op=ype SelB= 36 multipath..2

25 A Multiple Cycle Delay Path There is no register to save the results between: Register Fetch: <- Reg[rs] ; busb <- Reg[rt] R-type Execution: output <- op busb R-type Completion: Reg[rd] <- output Register here to save outputs of Rfetch? sela PCWr Instruction Reg Rs Rd Ra Rb Reg File Rw busw busb selb 2 3 Op Register here to save outputs of RExec? 36 multipath..2

26 A Multiple Cycle Delay Path (Continue) Register is NOT needed to save the outputs of Register Fetch: IRWr = : and busb will not change after Register Fetch Register is NOT needed to save the outputs of R-type Execution: and busb will not change after Register Fetch signals SelA, SelB, and Op will not change after R-type Execution Consequently output will not change after R-type Execution In theory (P. 36, P&H), you need a register to hold a signal value if: () The signal is computed in one clock cycle and used in another. (2) AND the inputs to the functional block that computes this signal can change before the signal is written into a state element. You can save a register if Cond is true BUT Cond 2 is false: But in practice, this will introduce a multiple cycle delay path: - A logic delay path that takes multiple cycles to propagate from one storage element to the next storage element 36 multipath..26

27 Pros and Cons of a Multiple Cycle Delay Path A 3-cycle path example: IR (storage) -> Reg File Read -> -> Reg File Write (storage) Advantages: Register savings We can share time among cycles: - If takes longer than one cycle, still a OK as long as the entire path takes less than 3 cycles to finish Instruction Reg Rs Rd Ra Rb Reg File Rw busw busb 2 3 selb 36 multipath..27

28 Pros and Cons of a Multiple Cycle Delay Path (Continue) Disadvantage: Static timing analyzer, which ONLY looks at delay between two storage elements, will report this as a timing violation You have to ignore the static timing analyzer s warnings Instruction Reg Rs Rd Ra Rb Reg File Rw busw busb 2 3 selb 36 multipath..28

29 Instruction Decode: We have an Ori! Next Cycle: Ori Execution PCWr= PC Beq ype Ori IorD=x 36 multipath..29 PCWrCond= : MemWr= RAdr WrAdr Din Dout Op IRWr= Intruction Reg 6 Func 6 RegDst=x Rs Rd Imm 6 ExtOp= Extend RegWr= Ra Rb Reg File Rw busw busb SelA= << 2 PCSrc=x 2 3 SelB= BrWr= Target Op=Add

30 Ori Execution output <- or Ext[Imm6] PCWr= PCWrCond= PCSrc=x BrWr= IorD=x MemWr= IRWr= RegDst= RegWr= SelA= Target PC RAdr WrAdr Din Dout Instruction Reg Rs Rd Ra Rb Reg File Rw Op=Or : SelA SelB= x: MemtoReg IorD, PCSrc busw busb << 2 OriExec multipath..3 Imm 6 ExtOp= Extend MemtoReg=x Op=Or SelB=

31 Ori Completion Reg[rt] <- output PCWr= PCWrCond= PCSrc=x BrWr= IorD=x MemWr= IRWr= RegDst= RegWr= SelA= Target PC RAdr WrAdr Din Dout Instruction Reg Rs Rd Op=Or x: IorD, PCSrc SelB= : SelA RegWr Ra Rb Reg File Rw busw busb OriFinish << multipath..3 Imm 6 ExtOp= Extend MemtoReg= Op=Or SelB=

32 Address Calculation output <- + SignExt[Imm6] PCWr= PCWrCond= PCSrc=x BrWr= IorD=x MemWr= IRWr= RegDst=x RegWr= SelA= Target PC RAdr WrAdr Din Dout Instruction Reg Rs Rd Ra Rb Reg File Rw : ExtOp SelA SelB= Op=Add x: MemtoReg PCSrc busw busb << 2 AdrCal multipath.. Imm 6 ExtOp= Extend MemtoReg=x Op=Add SelB=

33 Access for Store mem[ output] <- busb PCWr= PCWrCond= MemtoReg PCSrc=x BrWr= IorD=x MemWr= IRWr= RegDst=x RegWr= SelA= Target PC RAdr WrAdr Din Dout Instruction Reg Rs Rd : ExtOp MemWr SelA SelB= Op=Add x: PCSrc,RegDst Ra Rb Reg File Rw busw busb << 2 SWmem 2 3 Imm 6 ExtOp= Extend MemtoReg=x Op=Add SelB= 36 multipath..33

34 Access for Load Mem Dout <- mem[ output] PCWr= PCWrCond= PCSrc=x BrWr= IorD= MemWr= IRWr= RegDst= RegWr= SelA= Target PC RAdr WrAdr Din Dout Instruction Reg Rs Rd : ExtOp SelA, IorD SelB= Op=Add x: MemtoReg PCSrc Ra Rb Reg File Rw busw busb << 2 LWmem multipath..3 Imm 6 ExtOp= Extend MemtoReg=x Op=Add SelB=

35 Write Back for Load Reg[rt] <- Mem Dout PCWr= PCWrCond= IorD PCSrc=x BrWr= IorD=x MemWr= IRWr= RegDst= RegWr= SelA= Target PC RAdr WrAdr Din Dout Instruction Reg Rs Rd : SelA RegWr, ExtOp MemtoReg SelB= Op=Add x: PCSrc Ra Rb Reg File Rw busw busb LWwr << multipath..3 Imm 6 ExtOp= Extend MemtoReg= Op=Add SelB=

36 Putting it all together: Multiple Cycle Datapath PCWr PC IorD PCWrCond PCSrc BrWr MemWr IRWr RegDst RegWr SelA Target RAdr WrAdr Din Dout Instruction Reg Rs Rd Ra Rb Reg File Rw busw busb << Imm 6 ExtOp Extend MemtoReg SelB Op 36 multipath..36

37 Putting it all together: State Diagram AdrCal lw Ifetch : ExtOp SelA SelB= Op=Add x: MemtoReg PCSrc : ExtOp SelA, IorD SelB= Op=Add x: MemtoReg PCSrc LWwr LWmem Op=Add : PCWr, IRWr x: PCWrCond RegDst, Mem2R Others: s sw : SelA RegWr, ExtOp MemtoReg SelB= Op=Add x: PCSrc IorD lw or sw SWMem : ExtOp MemWr SelA SelB= Op=Add x: PCSrc,RegDst MemtoReg Rfetch/Decode Op=Add : BrWr, ExtOp SelB= x: RegDst, PCSrc IorD, MemtoReg Others: s RExec Rfinish ype Ori : RegDst SelA SelB= Op=ype x: PCSrc, IorD MemtoReg ExtOp beq Op=ype : RegDst, RegWr sela SelB= x: IorD, PCSrc ExtOp BrComplete Op=Sub SelB= x: IorD, Mem2Reg RegDst, ExtOp : PCWrCond SelA PCSrc Op=Or : SelA OriExec SelB= x: MemtoReg IorD, PCSrc Op=Or x: IorD, PCSrc SelB= : SelA RegWr OriFinish 36 multipath..37

38 Summary Disadvantages of the Single Cycle Processor 36 multipath..38 Long cycle time Cycle time is too long for all instructions except the Load Multiple Cycle Processor: Divide the instructions into smaller steps Execute each step (instead of the entire instruction) in one cycle Do NOT confuse Multiple Cycle Processor with Multiple Cycle Delay Path Multiple Cycle Processor executes each instruction in multiple clock cycles Multiple Cycle Delay Path: a combinational logic path between two storage elements that takes more than one clock cycle to complete It is possible (desirable) to build a MC Processor without MCDP: Use a register to save a signal s value whenever a signal is generated in one clock cycle and used in another cycle later