STC Overview & ITRI 3D-IC Program

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1 STC Overview & ITRI 3D-IC Program Cheng-Wen Wu General Director SoC Technology Center Industrial Technology Research Institute Oct. 8, 2008

2 SoC Technology Center Overview

3 SoC Technology Center (STC)

4 About STC at ITRI April 27, 2000: STC was founded as a task-force unit March 1, 2003: STC became an ITRI formal unit January 1, 2006: STC became one of five focus centers Major R&D Projects PAC PAC (Parallel Architecture Core) DSP DSP Core/Multicore & Platform MIMO Mobile WiMAX Technology for for PxD PxD

5 STC Core Technologies PMD (Personal Media Device) platform technologies Wireless communications chip technologies RF, AMS (Analog and Mixed-Signal), baseband PHY and MAC chip and system design Multicore DSP architecture & chip technologies, platforms, applications, etc. Low voltage, low power SoC design, verification, and testing technologies EDA (Electronic Design Automation) flow integration Electronic System Level (ESL) design technologies Heterogeneous SoC design integration and 3D IC packaging and testing technologies

Management Dept. Processor and Application Div. RF, Analog and Mixed- Signal Technology Div.

6 STC Orginzation Planning & Promotion Div. Project Mgt Sales & Promotion Planning General Director's Office GD Cheng-Wen Wu DGD Ginkou Ma DGD An-Yeu Wu Quality Management Dept. Processor and Application Div. RF, Analog and Mixed- Signal Technology Div. Wireless Broadband Technology Div. PAC DSP Platform IP/SOC WiMAX RF DVB-H Tuner Analog/Mixed Signal WiMAX BB WiMAX MAC WiMAX SOC Design Automation Technology Div. SOC BE EDA/DFT IP Total Employee: 291 (as of June 2008)

7 STC Global Network Stanford UIUC Elektrobit Waseda U. UC Santa Barbara CMU Fukuoka IST STC NCTU 交大 NTHU 清大 NSoC NCP NCKU 成大 NTU 台大 III 資策會 CIC 國家晶片中心台灣創毅 NCU 中央 Union U 聯大 SYSU 中山 TSIA 台灣半導體產業協會 Map image is from Wikimedia Commons

8 STC R&D Focus Key IPs for SOC/PxD DSP(PAC) Multicore DSP IP and Platform Wireless Communications WiMAX (802.16e m) Analog (ADC/DAC) and RF PAC Duo FPGA Platform Taiwan Dual Core Platform Design Technology ESL; Low-Voltage/Low-Power 3D Integration; Design-for- Reliability/Dependability Android SoC Prototype Demonstration WiMAX FPGA Demonstration DVB-H RF Tuner Demonstration WiMAX IOT Lab

9 Business Models Industrial Technology R&D Funding mainly from Ministry of Economy Affairs (MOEA), National SoC (NSoC) Program Technology Transfer/License Technical Service (for Companies) New Venture (Spin-off, Spin-in of R&D Team) Incubation Service Taipei Nan-Kang Park International Cooperation

10 ITRI 3DIC Program

Global Technology Trend:3DIC Traditional IC: Integrate multifunctional circus onto same chip 3DIC: Stack heterogeneous IC by TSV Longer wire => signal delay Large

11 Global Technology Trend:3DIC Traditional IC: Integrate multifunctional circus onto same chip 3DIC: Stack heterogeneous IC by TSV Longer wire => signal delay Large measure of area=> Decrease of yield rate Different circus requires different process and voltage=> design difficulty increase and yield rate decrease Source:ITRI, 2008,9

12 3D IC Consortium (Ad-STAC) hosted by ITRI, supported by Government Ad-STAC Join funding, Join development IDB Target System Design SIPO assist to promote 3D IC technology & Standard Material Equipment EDA Design Fab Package Testing Ad-STAC: Advanced Stacked-System Technology and Application Source:ITRI, 2008,9

13 Vision of Ad-STAC Consortium Advanced Stacked-System Technology and Application Innovative 3D IC technology & industry value-chain Mission Co-explore 3DIC technologies, products, and markets (among members) Collaborate with global organizations Leverage government resources Facilitate sharing of resources and IPs Establish certification test facilities and standards

14 ITRI 3D IC Technology Roadmap Silicon Chip Key Technology Key Technology Substrate Wafer Thinning & Chip Strength Improving Dry Etching Type Thinning Method TSV Forming Laser drilling / DRIE Via Filling Cu Plating Micro Bumping Pitch < 20μm / Lead free Chip to chip bonding (10 layers stacking) TSV Via size<30 um, t<50 um ITRI s Roadmap Chip to wafer bonding (8 ) Laser/DRIE TSV Via size<10 um, t<20 um Wafer to wafer bonding (8-12 ) Laser/DRIE TSV CCM stacking (Laser-based TSV) CCM stacking (pixel<1.4um) Via size<1 um, t<10 um Memory/Logic stacking (Laser/DRIE TSV) ~2014 Source:ITRI, 2008,9

15 EDA Requirements for 3D Integration Design Netlist Thermal Analysis Noise Reduction EMI & X talk Reliability & ESD DfT/BIST /Diagnosis Fault Tolerance Source:ITRI, 2008,9 System-Level Concurrent Design for 3DIC Cell Library Design Rule Technology, Library, Design Database 3D Layout Database 3D Model Hard/Firm IP 3D Timing/Power/ Analyzer (w/ TSV) Thermal/Timing Driven 3D Floorplanner Thermal/Timing Driven 3D Placer (w/ TSV) Thermal/Timing Driven 3D Router (w/ TSV) 3D Layout Management & DRC/LVS Tools Long Wire in 2D SoC Short Wire in 3D IC H G D E C B A Partition into 3D G H E D C A B

16 3D-IC Promotion in Taiwan 3D IC Lab (ITRI: EOL/STC) 3D IC Industrial information (IDB) Int l Technology Platform - Standardization (IDB) Ad-STAC - (IDB:ITRI: EOL/STC) 3D IC advanced Research (DoIT/ITRI) Integrate resources, Share risks Source:SIPO, 2008,9

17 17

Stacked Silicon Interconnect Technology (SSIT)

Stacked Silicon Interconnect Technology (SSIT) Suresh Ramalingam Xilinx Inc. MEPTEC, January 12, 2011 Agenda Background and Motivation Stacked Silicon Interconnect Technology Summary Background and Motivation