add rd, rs, rt Review: A Single Cycle Datapath We have everything Lecture Recap: Meaning of the Control Signals
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1 CS6C L27 Single-Cycle CPU Control () inst.eecs.berkeley.edu/~cs6c UC Berkeley CS6C : Machine Structures Lecture 26 Single-cycle CPU Control Ehausted TA Ben Sussman Qutrits Bring Quantum Computers Closer: An Australian group has built and tested logic gates that convert qubits into qutrits (three-level quantum states)! But who cares: new iphones soon? Ben hes so Review: A Single Cycle path We have everything ecept control signals CS6C L27 Single-Cycle CPU Control (2) RegWr Rs zero RegFile busb imm6 6 ruction<3:> <2:25> ctr In <6:2> <:5> WrEn <:5> Rs Imm6 Recap: Meaning of the Control Signals : + < + n net br < + + {SignEt(Im6), } Later in lecture: higher-level connection between mu and branch condition CS6C L27 Single-Cycle CPU Control (3) imm6 ress Recap: Meaning of the Control Signals : zero, sign src: regb; : write memory : ; Mem immed : rt ; rd ctr: ADD, SUB, OR RegWr: write register CS6C L27 Single-Cycle CPU Control () ctr RegWr Rs RegFile busb WrEn imm6 In 6 RTL: The ruction rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits add rd, rs, rt MEM[] Fetch the uction from memory R[rd] R[rs] + R[rt] The actual eration + Calculate the net uctionʼs address ruction at the Beginning of Fetch the uction from ruction memory: ruction MEM[] same for all uctions ress ruction<3:> imm6 CS6C L27 Single-Cycle CPU Control (5) CS6C L27 Single-Cycle CPU Control (6)
2 CS6C L27 Single-Cycle CPU Control (7) The Single Cycle path during rs rt rd shamt funct R[rd] R[rs] + R[rt] + Rs Imm6 ctradd RegWr Rs zero RegFile busb WrEn imm6 In 6 ruction<3:> <2:25> <6:2> <:5> <:5> ruction at the End of + This is the same for all uctions ecept: Branch and imm6 + ress CS6C L27 Single-Cycle CPU Control (8) Single Cycle path during Or Immediate? R[rt] R[rs] OR Et[Imm6] Rs Imm6 ctr RegWr Rs zero RegFile busb WrEn imm6 In 6 ruction<3:> <2:25> <6:2> <:5> <:5> Single Cycle path during Or Immediate? R[rt] R[rs] OR Et[Imm6] + Rs Imm6 ctror RegWr Rs zero RegFile busb WrEn imm6 In 6 zero ruction<3:> <2:25> <6:2> <:5> <:5> CS6C L27 Single-Cycle CPU Control (9) CS6C L27 Single-Cycle CPU Control () The Single Cycle path during Load? R[rt] {R[rs] + SignEt[imm6]} Rs Imm6 ctr RegWr Rs zero RegFile busb WrEn imm6 In 6 ruction<3:> <2:25> <6:2> <:5> <:5> The Single Cycle path during Load R[rt] {R[rs] + SignEt[imm6]} + Rs Imm6 ctradd RegWr Rs zero RegFile busb WrEn imm6 In 6 sign ruction<3:> <2:25> <6:2> <:5> <:5> CS6C L27 Single-Cycle CPU Control () CS6C L27 Single-Cycle CPU Control (2)
3 CS6C L27 Single-Cycle CPU Control (3) The Single Cycle path during Store? {R[rs] + SignEt[imm6]} R[rt] Rs Imm6 ctr RegWr Rs zero RegFile busb WrEn imm6 In 6 ruction<3:> <2:25> <6:2> <:5> <:5> The Single Cycle path during Store {R[rs] + SignEt[imm6]} R[rt] + Rs Imm6 ctradd RegWr Rs zero RegFile busb WrEn imm6 In 6 sign ruction<3:> <2:25> <6:2> <:5> <:5> CS6C L27 Single-Cycle CPU Control () The Single Cycle path during Branch? if (R[rs] - R[rt] ) then ; else ruction<3:> Rs Imm6 ctr RegWr Rs zero RegFile busb WrEn imm6 In 6 <2:25> <6:2> <:5> <:5> The Single Cycle path during Branch if (R[rs] - R[rt] ) then ; else ruction<3:> br Rs Imm6 ctrsub RegWr Rs zero RegFile busb WrEn imm6 In 6 <2:25> <6:2> <:5> <:5> CS6C L27 Single-Cycle CPU Control (5) CS6C L27 Single-Cycle CPU Control (6) ruction at the End of Branch if ( ) then + + SignEt[imm6]* ; else + imm6 MUX ctrl CS6C L27 Single-Cycle CPU Control (7) ruction<3:> What is encoding of? Direct MUX select? Branch inst. / not branch Letʼs pick 2nd tion zero? MUX Q: What logic gate? Administrivia Sorry about Proj woes Grading is rough stuff. Donʼt blame Ben, heʼs innocent. HW6 Due imminently! Students have claimed it takes a very long time Remember MODULAR DESIGN. This could save you a lot of time. HW7 Out Now! Get started soon. Proj3 is on its way, will be out soon after the weekend. CS6C L27 Single-Cycle CPU Control (8)
4 CS6C L27 Single-Cycle CPU Control (9) Step : Given path: RTL Control ruction<3:> <26:3> <:5> Op Fun <2:25> Rs <6:2> RegWrctr <:5> Control DATA PATH <:5> Imm6 inst A Summary of the Control Signals (/2) Register Transfer add R[rd] R[rs] + R[rt]; + src RegB, ctr ADD, rd, RegWr, + sub R[rd] R[rs] R[rt]; + src RegB, ctr SUB, rd, RegWr, + ori R[rt] R[rs] + zero_et(imm6); + src Im, Et Z,ctr OR, rt,regwr, + lw R[rt] MEM[ R[rs] + sign_et(imm6)]; + src Im, Et sn, ctr ADD,, rt, RegWr, + sw MEM[ R[rs] + sign_et(imm6)] R[rs]; + src Im, Et sn, ctr ADD,, + beq if ( R[rs] R[rt] ) then + sign_et(imm6)] else + br, ctr SUB CS6C L27 Single-Cycle CPU Control (2) A Summary of the Control Signals (2/2) See func We Don t Care :-) Appendi A add sub ori lw sw beq RegWrite ite nsel ctr<2:> Subtract Or Subtract R-type rs rt rd shamt funct add, sub I-type? ori, lw, sw, beq Boolean Epressions for Controller add + sub ori + lw + sw lw RegWrite add + sub + ori + lw ite sw nsel beq lw + sw ctr[] sub + beq (assume ctr is ADD, : SUB, : OR) ctr[] or where, rtype ~ 5 ~ ~ 3 ~ 2 ~ ~, ori ~ 5 ~ 3 2 ~ lw 5 ~ ~ 3 ~ 2 sw 5 ~ 3 ~ 2 beq ~ 5 ~ ~ 3 2 ~ ~ ~ 5 ~ ~ 3 ~ 2 ~ add rtype func 5 ~func ~func 3 ~func 2 ~func ~func sub rtype func 5 ~func ~func 3 ~func 2 func ~func How do we implement this in gates? CS6C L27 Single-Cycle CPU Control (2) CS6C L27 Single-Cycle CPU Control (22) Controller Implementation code func AND logic add sub ori lw sw beq OR logic RegWrite ite nsel ctr[] ctr[] Peer ruction ruction<3:> ruction RegWr Rs Rs Imm6 ctr -bit Registers busb WrEn imm6 6 A. MemToRegʻʼ & ctrʻsubʼ. SUB or BEQ? B. ctrʻaddʼ. Which signal is different for all 3 of: ADD, LW, & SW? or? C. Donʼt Care signals are useful because we can simplify our PLA personality matri. F / T? In <2:25> <6:2> <:5> <:5> ABC : SRF : SRT 2: SEF 3: SET : BRF 5: BRT 6: BEF 7: BET CS6C L27 Single-Cycle CPU Control (23) CS6C L27 Single-Cycle CPU Control (2)
5 CS6C L27 Single-Cycle CPU Control (25) Summary: Single-cycle Processor 5 steps to design a processor. Analyze uction set datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements. Analyze implementation of each uction to determine setting of control points that effects the register transfer. 5. Assemble the control logic Formulate Logic Equations Design Circuits Processor Control Input Bonus slides These are etra slides that used to be included in lecture notes, but have been moved to this, the bonus area to serve as a supplement. The slides will appear in the order they would have in the normal presentation path Output CS6C L27 Single-Cycle CPU Control (26) The Single Cycle path during 3 New { [3..28],, } ruction<3:> ruction RegWr Rs ctr Rs Imm6 TA26 -bit Registers busb WrEn imm6 6 In <2:25> <6:2> <:5> <:5> <:25> The Single Cycle path during 3 ruction<3:>? ruction RegWr Rs ctr Rs Imm6 TA26 -bit Registers busb WrEn imm6 6 New { [3..28],, } In <2:25> <6:2> <:5> <:5> <:25> CS6C L27 Single-Cycle CPU Control (27) CS6C L27 Single-Cycle CPU Control (28) ruction at the End of 3 New { [3..28],, } imm6 er er n_mux_sel ruction<3:> How do we modify this to account for s? ruction at the End of 3 New { [3..28],, } imm6 er n_mux_sel er TA 26 (MSBs) ruction<3:> Query Can still get asserted? Does need to be? If not, what? CS6C L27 Single-Cycle CPU Control (29) CS6C L27 Single-Cycle CPU Control (3)
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