of integration y e.g. TTL packages: Data Book for 100 s of different parts y Map your circuit to the Data Book parts

Transcription

1 x x x x x x volution of Implementation Technologies Gate rra Technolog (IM - s) iscrete devices: relas, transistors (s-s) trend toward iscrete logic gates (s-s) higher levels Integrated circuits (s-s) of integration e.g. T packages: ata ook for s of different parts Map our circuit to the ata ook parts Gate rras (IM s) ustom integrated circuit chips esign using a librar (like T) Transistors are alread on the chip lace and route software puts the chip together automaticall + Large circuits on a chip + utomatic design tools (no tedious custom laout) - Onl good if ou want s of parts ilinx FGs - Simple logic gates Use transistors to implement combinational and sequential logic Interconnect Wires to connect inputs and outputs to logic blocks I/O blocks Special blocks at peripher for external connections dd wires to make connections one when chip is fabed mask-programmable onstruct an circuit ilinx FGs - rogrammable Logic rogrammable Logic Technologies isadvantages of the ata ook method onstrained to parts in the ata ook arts are necessaril small and standard Need to stock man different parts rogrammable logic Use a single chip (or a small number of chips) rogram it for the circuit ou want No reason for the circuit to be small ilinx FGs - Fuse and anti-fuse Fuse makes or breaks link between two wires Tpical connections are - ohm One-time programmable (testing before programming?) Ver high densit ROM and ROM High power consumption Tpical connections are - ohm Fairl high densit RM-based Memor bit controls a switch that connects/disconnects two wires Tpical connections are.- ohm an be programmed and re-programmed in the circuit Low densit ilinx FGs - rogrammable Logic Making Large rogrammable Logic ircuits rogram a connection onnect two wires Setabittoor Regular structures for two-level logic (s-s) ll rel on two-level logic minimiation ROM connections - permanent ROM connections - erase with UV light ROM connections - erase electricall ROMs Ls Ls rogram connections in the plane rogram the connections in the plane lternative : L ut a lot of LS on a chip dd wires between them whose connections can be programmed Use fuse/rom technolog lternative : FG mulate gate arra technolog Hence Field rogrammable Gate rra ou need: wa to implement logic gates wa to connect them together rogram the connections in the plane ilinx FGs - ilinx FGs -

2 Field-rogrammable Gate rras Field-rogrammable Gate rras Ls, Ls = - Gate quivalents Field rogrammable Gate rras = FGs ltera M Famil ctel rogrammable Gate rra ilinx Logical ell rra - (s) of Gate quivalents! Logic blocks To implement combinational and sequential logic Interconnect Wires to connect inputs and outputs to logic blocks I/O blocks Special logic blocks at peripher of device for external connections ilinx FGs - e questions: How to make logic blocks programmable? How to connect the wires? fter the chip has been fabbed ilinx FGs - 8 Tradeoffs in FGs ltera L (rasable rogrammable Logic evices) Logic block - how are functions implemented: fixed functions (manipulate inputs) or programmable? Support complex functions, need fewer blocks, but the are bigger so less of them on chip Support simple functions, need more blocks, but the are smaller so more of them on chip Interconnect How are logic blocks arranged? How man wires will be needed between them? re wires evenl distributed across chip? rogrammabilit slows wires down are some wires specialied to long distances? How man inputs/outputs must be routed to/from each logic block? What utiliation are we willing to accept? %? %? %? ilinx FGs - Historical erspective Ls: same technolog as programmed once bipolar ROM Ls: MOS erasable programmable ROM (ROM) erased b UV light ltera building block = MROLL 8 roduct Term N-OR rra + rogrammable MU's N RR rogrammable polarit Invert ontrol L lk MU ilinx FGs - F/ MU Output MU pad rogrammable feedback I/O in Seq. Logic lock ltera L ltera Multiple rra Matrix (M) ltera Ls contain 8 to 8 independentl programmed macrocells Global L ersonalied lk Snchronous Mode MU b ROM bits: Flipflop controlled O/Local L b global clock signal local signal computes output enable ROM ell O/Local L Global L lk MU ROM ell snchronous Mode Flipflop controlled b locall generated clock signal + Seq Logic: could be, T positive or negative edge triggered + product term to implement clear function ilinx FGs - N-OR structures are relativel limited annot share signals/product terms among macrocells Logic rra locks (similar to macrocells) L L L L I ilinx FGs - L H L G L F L Global Routing: rogrammable Interconnect rra M8: 8 Fixed Inputs I/O ins 8 Ls Macrocells/L xpanders/l

3 INRMNT 8 8 FIRST FUS 88 NUMRS SNHRONOUS RST (TO LL RGISTRS) R 88 S R 8 LOGI MROLL - 8 R - 8 LOGI MROLL - 8 R - 8 LOGI MROLL - 8 R - 8 LOGI MROLL - 8 R INRMN T LOGI MROL L - 88 R - 8 LOGI MROL L - 8 R - 8 LOGI MROL L - 8 R - 8 LOGI MROL L - 8 R - 8 LOGI MROL L - 8 R SNHRONOUS RST (TO LL RGISTRS) L rchitecture V L Macrocell RR I/O lock I/O ad Macrocell -Terms I N U T S I xpander roduct Term RR I/O ad xpander -Terms xpander Terms shared among all macrocells within the L ilinx FGs - Supports large number of product terms per output Latches and muxes ilinx associated FGs - with output pins ctel rogrammable Gate rras ctel Logic Module Rows of programmable logic building blocks + rows of interconnect nti-fuse Technolog: rogram Once Use nti-fuses to build up long wiring runs from short segments I/O uffers, rogramming and Test Logic I/O uffers, rogramming and Test Logic I/O uffers, rogramming and Test Logic Logic Module Wiring Tracks I/O uffers, rogramming and Test Logic SO : MU : MU SO : MU xample: Implementation of S-R Latch S S "" "" asic Module is a Modified : Multiplexer : MU : MU R "" : MU 8 input, single output combinational logic blocks ilinx FGs - FFs constructed from discrete cross coupled gates ilinx FGs - S ctel Interconnect ctel Routing xample Logic Module Logic Module Input Horiontal Track nti-fuse Logic Module Output Logic Module Input Jogs cross an anti-fuse Vertical Track Interconnection Fabric ilinx FGs - minimie the # of jogs for speed critical circuits - hops for most interconnections ilinx FGs - 8

4 G G G G F F F F G Func. Gen. F Func. Gen. H Func. Gen. Switch Matrix H IN S/R S/R o ntr ol I N F' G' H' G' H' I N F' G' H' H' F' S R S/R o ntr ol S R Vcc Slew assive Rate ull-up, ontrol ull-own Output uffer Input uffer ela ad ilinx rogrammable Gate rras - onfigurable Logic lock -input, output function or -input, output functions IO IO IO IO optional register on outputs uilt-in fast carr logic an be used as memor Three tpes of routing direct general-purpose IO IO IO Wiring hannels rogrammable Interconnect I/O locks (IOs) long lines of various lengths RM-programmable IO onfigurable Logic locks (s) can be reconfigured ilinx FGs - The ilinx Two -input functions, registered output ilinx FGs - ilinx FGs - -input function, combinational output Used as RM ilinx FGs - ilinx FGs -

5 Fast arr Logic ilinx Interconnect ilinx FGs - ilinx FGs - Switch Matrix ilinx Interconnect etails ilinx FGs - ilinx FGs - 8 Global Signals - lock, Reset, ontrol ilinx IO ilinx FGs - ilinx FGs -

6 ilinx FG ombinational Logic xamples ilinx FG ombinational Logic e: General functions are limited to inputs ( even better - / ) No limitation on function complexit xamples N-input majorit function: whenever n/ or more inputs are N-input parit functions: input/ ; levels ield inputs! xample -bit comparator: = and > implemented with (GT) F = ' + ' + ' ' () G = ''''+ ' ' + ' '+ -input Majorit ircuit Input arit Logic an implement some functions of > input -input Majorit ircuit ilinx FGs - ilinx FGs - ilinx FG dder xample xample -bit binar adder - inputs:,,,, IN outputs: S, S, out out S out S S S S S in in S S ilinx FGs - Full dder, delas to final carr out x Two-bit dders ( s each) ields s to final carr out omputer-ided esign an't design FGs b hand Wa too much logic to manage, hard to make changes Hardware description languages Specif functionalit of logic at a high level Validation: high-level simulation to catch specification errors Verif pin-outs and connections to other sstem components Low-level to verif mapping and check performance Logic snthesis rocess of compiling HL program into logic gates and flip-flops Technolog mapping Map the logic onto elements available in the implementation technolog (LUTs for ilinx FGs) ilinx FGs - Tool ath (cont d) ilinx Tools lacement and routing ssign logic blocks to functions Make wiring connections Timing analsis - verif paths etermine delas as routed Look at critical paths and was to improve artitioning and constraining If design does not fit or is unroutable as placed split into multiple chips If design it too slow prioritie critical paths, fix placement of cells, etc. Few tools to help with these tasks exist toda Generate programming files - bits to be loaded into chip for configuration ilinx FGs - Verilog (or VHL) use to specif logic at a high-level ombine with schematics, librar components Snopss ompiles Verilog to logic Maps logic to the FG cells Optimies logic ilinx R - automatic place and route (simulated annealing) rovides controllabilit through constraints Handles global signals ilinx dela - measure dela properties of mapping and aid in iteration ilinx T - design editor to view final mapping results ilinx FGs -

7 pplications of FGs Implementation of random logic asier changes at sstem-level (one device is modified) an eliminate need for full-custom chips rototping nsemble of gate arras used to emulate a circuit to be manufactured Get more/better/faster debugging done than with simulation Reconfigurable hardware One hardware block used to implement more than one function Functions must be mutuall-exclusive in time an greatl reduce cost while enhancing flexibilit RM-based onl option Special-purpose computation engines Hardware dedicated to solving one problem (or class of problems) ccelerators attached to general-purpose computers ilinx FGs - ROM-based esign xample: to xcess Serial onverter onversion rocess its are presented in bit serial fashion starting with the least significant bit Single input, single output ilinx FGs - 8 xcess ode resent State S S S S S S S S / S /, / S /, / Next State = = S S S S S S S S S S S S S -- S / / / / Output = = -- Reset S /, / S / S / ilinx FGs - State Transition Table erived State iagram ROM ddress ROM-based Implementation ROM Outputs converter ROM L \Reset L LR ircuit Level Realiation = x positive edge triggered FFs Truth Table/ROM I/Os In ROM-based designs, no need to consider state assignment ilinx FGs - LS MS Timing ehavior for input strings ()and () L-based esign State ssignment with NOV LS LS S S S S S S S S S S S S S S S S S S S S S S S S S S NOV input file S = S = S = S = S = S = S = NOV derived state assignment product term implementation ilinx FGs - ilinx FGs -

8 .i.o.ilb x q q q.ob d d d.p e spresso Inputs spresso Outputs ilinx FGs -.i.o.ilb x q q q.ob d d d.p e = + = = = + L converter L \Reset ilinx FGs - L LR H8 L: inputs, 8 outputs, product terms per OR gate = = + = not used LH8 8 N Gate rra 8 8 ilinx FGs - ilinx FGs - Registered L rchitecture uffered Input or product term L O rogrammable Output olarit/or Ls L O uried Registers: decouple FF from the output pin + + dvantage of OR Ls: arit and rithmetic Operations = + Negative Logic Feedback = = ilinx FGs - = + Å Å Å ilinx FGs - 8 Å Å Å

9 FIRST FUS NUMR 8 INRMN T INRMN T 8 8 NOT: FUS NUMR = FIRST FUS NUMR + INRMNT 8 INRMN T 8 8 FIRST FUS NUMR S xample of OR L ilinx FGs - xample of Registered L Specifing Ls with L H8 L xplicit equations for partitioned output functions module bcdexcess title ' to xcess ode onverter State Machine' u device 'ph8'; "Input ins,,,,i,i pin,,,,,; "Output ins,o,o,,, pin,8,,,,; INSTT = [,, ]; S = [,, ]; S = [,, ]; S = [,, ]; S = [,, ]; S = [,, ]; S = [,, ]; S = [,, ]; equations = (! & ) # ( &!); = i # i; o = (! &! &! & ) # ( &! &!); o = (! & &!) # ( &!); =!; = ( & ) # (! &!); end bcdexcess; ilinx FGs - Specifing Ls with L Specifing Ls with L H L Simpler equations module bcdexcess title ' to xcess ode onverter State Machine' u device 'ph'; "Input ins,,, pin,,, ; "Output ins,,, pin, 8,, ; INSTT = [,, ]; OUTT = [,, ]; Sin = [,, ]; Sout = [,, ]; Sin = [,, ]; Sout = [,, ]; Sin = [,, ]; Sout = [,, ]; Sin = [,, ]; Sout = [,, ]; Sin = [,, ]; Sout = [,, ]; Sin = [,, ]; Sout = [,, ]; Sin = [,, ]; Sout = [,, ]; equations = (! & ) # ( &!); = (! &! &! & ) # ( &! &!) # (! & &!) # ( &!); =!; = ( & ) # (! &!); end bcdexcess; ilinx FGs - R L module bcdexcess title ' to xcess ode onverter' u device 'pr'; "Input ins lk, Reset,,!O pin,,, ; "Output ins,,, pin,,, ; SRG = [,, ]; S = [,, ]; S = [,, ]; S = [,, ]; S = [,, ]; S = [,, ]; S = [,, ]; S = [,, ]; state_diagram SRG state S: if Reset then S else if then S with = else S with = state S: if Reset then S else if then S with = else S with = state S: if Reset then S else if then S with = else S with = state S: if Reset then S else if then S with = else S with = state S: if Reset then S else if then S with = else S with = state S: if Reset then S else if then S with = else S with = state S: if Reset then S else if! then S with = end bcdexcess; ilinx FGs - FSM esign with ounters FSM esign with ounters Snchronous ounters: LR, L, NT xcess onverter Revisited Reset Four kinds of transitions for each state: () to State (LR) () to next state in sequence (NT) () to arbitrar next state (L) LR NT n no signals asserted L / / / / /, / Note the sequential nature of the state assignments () loop in current state n+ m /, / / / areful areful state state assignment assignment is is needed needed to to reflect reflect basic basic sequencing sequencing of of the the counter counter ilinx FGs - /, / / ilinx FGs -

10 FSM esign with ounters Implementing FSMs with ounters xcess onverter Inputs/urrent State Next State Outputs LR L N LR signal dominates L which dominates ount ilinx FGs -.i spresso Input File.o.ilb res x q q q.ob clr ld en c b a.p xcess onverter ilinx FGs -.e spresso Output File.i.o.ilb res x q q q.ob clr ld en c b a.p e FSM Implementation with ounters L ilinx L rchitecture excess L Reset \LR \L N T RO L LO LR Implementing the to xcess FSM += + += = = + No function more complex than variables FFs implies s xcess onverter Schematic Snchronous Meal Machine Global Reset to be used Snchronous Output Register ilinx FGs - lace +, + in once, in second maximie use of direct & general purpose interconnections ilinx FGs - 8 Implementing the to xcess FSM esign ase Stud lk lk Traffic Light ontroller ecomposition into primitive subsstems ontroller FSM next state/output functions state register I FG I FG Short time/long time interval counter FG FG ar Sensor RS RS Output ecoders and Traffic Lights ilinx FGs - ilinx FGs -

11 esign ase Stud esign ase Stud Traffic Light ontroller lock iagram Reset lk short time/ long time counter resent \resent + Subsstem Logic in R \Reset Light ecoders F F G a FG F FR HG H HR Reset (asnc) lk ar Sensor (snc) controller fsm Next State Output Logic State Register ilinx FGs - ST ncoded Light Light ecoders Signals F H + L ar etector Interval Timer L Reset ST LR + T RO L LO ilinx LR FGs - H H G b esign ase Stud esign ase Stud State ssignment: HG =, H =, FG =, F = = = + + ST= HL[] = + + Next State Logic HL[] = + FL[] = FL[] = + L/L Implementation: inputs, outputs, 8 product terms L V -- inputs, prog. IOs, 8 to prod terms per OR ROM Implementation: word b 8-bit ROM ( bits) Reset ma double ROM ilinx sie FGs - HG H FG F ST = ount ounter-based Implementation / ST / ST + / ST / ST \ G G S SO x : MU ST T RO L + LO \Reset LR T Implementation with MU and ounter an we reduce package count b using an 8: MU? ilinx FGs - esign ase Stud esign ase Stud ounter-based Implementation ispense with direct output functions for the traffic lights Wh not simpl decode from the current state? G a HG H HR FG F FR L-ased Implementation iscrete Gate Method: None of the functions exceed variables, ST are variable ( each), HL, HL, FL are variable (/ each) FL is variable (/ ) / s total! ST is a Snchronous Meal Output Light ontrollers are Moore Outputs ilinx FGs - ilinx FGs -

12 esign ase Stud esign ase Stud L-ased Implementation I F R I R F L-ased Implementation ounter/multiplexer Method: : MU, it Upcounter lacement of functions selected to maximie the use of direct connections I R I R H H MU: six variables ( data, control) but this is the kind of variable function that can be implemented in! nd to implement and+' ut note that ST/nt is reall a function of,,,, to implement this function of variables! it ounter: functions of variables ( bit state + count) lso implemented in one ilinx FGs - I ST R I R Traffic light decoders: functions of variables (, ) per = for the six lights Total count = s ilinx FGs - 8