NR002556F Page 1 of 25. Media Platforms and Services Group

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1 Medi Pltforms nd Services Group Blckfin Anomly list for Revision(s) BF , BF , BF , BF , BF Creted Tue Nov 2 10:28: (IM) These nomlies represent the currently known differences between revisions of Blckfin devices nd the functionlity specified in the Blckfin dt sheets nd User's Mnul. A revision number with the form "-x.x" is brnded on ll prts. Bits 31:28 of the BF535 s CHIP ID Register (CHIPID) differentites between pre-nd-post 1.0 revisions. For revisions prior to 1.0, bits 31:28 of the CHIPID register will red vlue of 0. For revisions 1.0 nd lter, bits 31:28 of the CHIPID register will red vlue of 1. Revision CHIPID[31:28] , 1.1, 1.2, Index ID Anomly Summry The Scrtchpd SRAM cn only be ccessed using DAG The ILAT register cnnot be clered without servicing n interrupt The AZ bit of the ASTAT register is undefined when using RND BF BF BF BF BF NR002556F Pge 1 of 25

2 Medi Pltforms nd Services Group Index ID Anomly Summry SIGNBITS opertion returns incorrect vlue SPORT: Improper behvior when RFS/TFS is ctive low in the lte frming mode Core current levels re higher thn necessry t 300MHz PCI: Extr BAR in Config Spce System Interrupt Controller Interrupt Msk Register polrity is different thn the polrity used in IMASK Undefined ASTAT bits Core Timer counts during emultion mode in revision 0.2 silicon Multi-issue instructions tht store to L1 dt memory nd lod from scrtchpd do not work properly BF BF BF BF BF x.... x.... x.... x.... x.... NR002556F Pge 2 of 25

3 Medi Pltforms nd Services Group Index ID Anomly Summry Tristte pins re outputs during power up IrDA functionlity does not function correctly UART THRE bit ltency Rev 0.2 nd 1.0 silicon re not PC133 complint Writing nd reding ILOC bits Boundry Scn does not work in Rev 0.2 silicon Icche Flush doesn't invlidte the Fill Buffer PLL trnsitions incorrect coming out of reset Icche bus error does not Flush the Fill Buffer Core hngs on specific condition Sport Trnsmit Underflow (TUVF) specil clering instructions Incorrect ASTAT flg BF BF BF BF BF x.... x.... x x... x.... x x x.. x.... NR002556F Pge 3 of 25

4 Medi Pltforms nd Services Group Index ID Anomly Summry opertions Shifter does not consider ll 32 bits when shift vlue is D register PCI register chnges Specultive fetch of illegl or undefined memory loction cuses HW error Accessing MMRs with Dt Cche disbled nd CPLBs enbled USB: On HOST OUT (PC-> BF535) disrm is not functioning correctly USB: EPLEN is not updting correctly t the end of short pcket Problems with dt cche writebck mode Setting brekpoints in n emultor session with cche enbled USB: ARM bit not clering BF BF BF BF BF x.... x x x.. x x x.. x x x.. NR002556F Pge 4 of 25

5 Medi Pltforms nd Services Group Index ID Anomly Summry on short pckets RTC integrity when core powered off Seril clock is not gted by SPORT enble bit V minimum VDDcore required SPORT Multichnnel Mode strting nd stopping CLI instruction cn llow n synchronous interrupt occur s it is committing Store to Lod Forwrding in Write Through Mode Dt cche dirty bit set when lodmiss-fill is in progress PLL clkout my be incorrect in multiplier mode coming out of reset Rev 1.2 nd 1.3 silicon do not meet TDCAD requirement of the PC133 spec BF BF BF BF BF x x x..... x x... x x Ltency in NR002556F Pge 5 of 25

6 Medi Pltforms nd Services Group Index ID Anomly Summry Writes to RND_MOD bit IDCODE register not JTAG IEEE complint Key: x = nomly exists in revision. = Not pplicble BF BF BF BF BF ANOMALIES The Scrtchpd SRAM cn only be ccessed using DAG0: The BF535 HW Reference indictes tht the L1 Scrtchpd memory cn be ccessed from either DAG0 or DAG1. On the BF535, n ttempted ccess by DAG1 to the Scrtchpd SRAM will result in n exception. Workround: The workround is to void n ccess to this memory spce by DAG1. To void doing this, do not plce ny dt into the L1 Scrtchpd memory if it will be ccessed by compiled code. In ddition, nything plced in L1 Scrtchpd memory must be declred s "voltile." For multi-issue ssembly instructions of the form: DSP32 Lod Store or DSP32 Lod Lod cre should be tken to void the cse where the Lod/Store instructions both ccess the Scrtchpd memory in single instruction or ny instruction where DAG1 mkes n ccess to the scrtchpd memory. BF , BF , BF , BF , BF The ILAT register cnnot be clered without servicing n interrupt: The BF535 HW Reference mnul indictes tht the ILAT register is Red/Write. In the current revisions of silicon, ILAT is red only. Workround: The only wy to cler ILAT is to ctully service the interrupt nd execute n RTI. BF , BF , BF , BF , BF NR002556F Pge 6 of 25

7 Medi Pltforms nd Services Group The AZ bit of the ASTAT register is undefined when using RND: The AZ bit of the ASTAT register is undefined fter using the RND option in n instruction, e.g. R1.L=R0 (RND); Workround: If the vlue of AZ is importnt to user code, the AZ bit must be checked prior to executing n instruction with the RND option. BF , BF , BF , BF , BF SIGNBITS opertion returns incorrect vlue: The SIGNBITS instruction returns the n incorrect vlue, e.g. R0.L= SIGNBITS A0; returns -8 thru 30 if A0=0x thru A0=0x returns 39 if A0=-1 returns 39 if A0=0 It should return 31 when A0=-1 nd A0=0 Workround: The SIGNBITS instruction will produce incorrect results for the cse described bove. Cre should be tken when using this instruction. BF , BF , BF , BF , BF SPORT: Improper behvior when RFS/TFS is ctive low in the lte frming mode: For SPORT0 nd SPORT1: 1. With internl RFS/TFS, the RFS/TFS won't frme the dt when RFS/TFS is ctive low, in lte frming mode. An ctive high RFS/TFS will frme the dt. 2. With internl RFS/TFS, the RFSDIV/TFSDIV must be set to fctor of 4 smller thn wht would be expected to chieve the desired RFS/TFS frequency. Workround: Do not use lte frming mode with ctive low. BF Core current levels re higher thn necessry t 300MHz: The core current level in the rev 0.2 silicon is higher thn necessry. Severl modifictions will be implemented in the production silicon which will reduce the core current significntly. Workround: The production silicon drws significntly less current. The rev 0.2 silicon cn be run t lower frequencies nd lower voltge levels to reduce power levels until the production silicon is vilble. NR002556F Pge 7 of 25

8 Medi Pltforms nd Services Group BF PCI: Extr BAR in Config Spce: 8. The Configurtion Spce registers in the PCI core hve n extr Bse Address Register. This cuses the System BIOS (in PCI system) to see the BF535 device s hving one extr Memory or IO window (type depends on BIOS design). The only side effect should be tht n invlid Memory window of size 16 bytes or n invlid IO window of size 4 bytes will be llocted in the system for the BF535 device. Agin, becuse of the nture of the register, the exct behvior is not covered by the PCI spec nd will be BIOS specific. In ny cse this extr window should not cuse problem if the BF535 device specific driver is written to ignore the extr window. Workround: The BF535 device specific driver should be written to ignore the extr window on revision 0.2 silicon. BF System Interrupt Controller Interrupt Msk Register polrity is different thn the polrity used in IMASK: The System Interrupt Controller Interrupt Msk Register (SIC_IMASK), s described in the BF535 Hrdwre Reference mnul, hs the following polrity: A bit vlue of 1 enbles the corresponding interrupt. A bit vlue of 0 disbles the corresponding interrupt. On the BF535 rev 0.2 silicon, the polrity of the SIC_IMASK register is inverted in tht vlue of 1 ctully disbles the interrupt nd vlue of 0 enbles the interrupt. In ddition, the BF535 Hrdwre Reference Mnul sttes the reset vlue of SIC_IMASK is equl to 0x0000 (ll interrupts disbled). Rev 0.2 silicon initilizes the SIC_IMASK register to "ll interrupts disbled" but due to the polrity inversion, the reset vlue of SIC_IMASK is 0x001FFFFF. The production version of the prt will correct the polrity of the SIC_IMASK bits nd reset vlue of the SIC_IMASK register to mtch the vlues s defined in the BF535 Hrdwre Reference Mnul. Workround: When using rev 0.2 BF535 silicon, vlue of 0 must be used to enble the peripherl interrupts vi the SIC_IMASK register. When the production prt is relesed, the BF535 will operte s described in the HW Reference Mnul. The following code sequence cn be used to write code tht will work properly on ny silicon revision. It checks the upper byte of the CHIP_ID register. Revision 0.2 silicon will hve vlue of 0 in the upper byte. All future revisions will hve non-zero vlue in the upper byte. //Check revision of silicon P0.L = 0x48C0; //Memory mpped ddress of CHIPID register P0.H = 0xFFC0; R0 = [P0]; R1.H = 0xf000; R1.L = 0x0000; R1 = R1 & R0; NR002556F Pge 8 of 25

9 Medi Pltforms nd Services Group CC = AZ; // If the CHIPID is non-zero, "1" in //SIC_IMASK will enble system interrupts if!cc jump new; old: P3.L = SIC_IMASK & 0xffff; P3.H = SIC_IMASK >> 16; R6 = [p3]; BITCLR(R6,17); //Unmsk the PF Interrupt A in System Interrupt Msk Register [ P3 ] = R6; jump set_pointer; new: P3.L = SIC_IMASK & 0xffff; P3.H = SIC_IMASK >> 16; R6 = [P3]; BITSET(R6,17); // ny rev of 1.0 or lter will hve system interrupts //enbled by writing 1 to the pproprite bit [ P3 ] = R6; strt: BF Undefined ASTAT bits: Chpter 2 of the HW Reference nd the Instruction Set Reference both refer to severl bits in the ASTAT register which re not vilble in the BF535 silicon. These bits re listed s follows: Bit 12: AC0 Bit 13: AC1 Bit 16: AV0 Bit 17: AV0S Bit 18: AV1 Bit 19: AV1S Bit 24: V Bit 25: VS These bits re undefined nd should not be used in the BF535. This dded functionlity will be vilble in future Blckfin prts. In future Blckfin prts, these bits will perform s described in the BF535 BLACKFIN DSP HARDWARE REFERENCE, REV 3.0, JULY 2004 nd ISR documenttion. Workround: Use the remining ASTAT bits described in the BF535 BLACKFIN DSP HARDWARE REFERENCE, REV 3.0, JULY BF , BF , BF , BF , BF Core Timer counts during emultion mode in revision 0.2 silicon: NR002556F Pge 9 of 25

10 Medi Pltforms nd Services Group The core timer continues to count when the processor is in emultion mode. As described in the Hrdwre Reference Mnul, the core timer should stop counting whenever the BF535 is servicing n emultion event. Workround: There is currently no wy for the core timer to stop utomticlly when n emultion event occurs. As result, the core timer will continue to count t the CCLK rte while the processor is servicing the emultion reset. The wtchdog timer on the BF535 does stop during emultion mode. BF Multi-issue instructions tht store to L1 dt memory nd lod from scrtchpd do not work properly: The following conditions will cuse incorrect behvior in multi-issue instruction: A store to L1 Dt memory A or B in prllel with lod from the scrtchpd memory Workround: Multi-issue instructions which perform store to either L1 Dt bnk A or B in prllel with lod from the scrtchpd memory should be voided. BF , BF , BF , BF , BF Tristte pins re outputs during power up: The bi-directionl pins of the BF535 hve their outputs enbled during the time tht VDD_IO (or VDD_PCI) is on nd VDD_INT is off. The pins will drive high or low rbitrrily. Therefore connecting the bi-directionl pins to ech other or to ground will cuse excessive current during power up. Workround: The workround is to void connecting bi-directionl signls to ech other or directly to outputs or to power or ground. The current drwn during this condition should be smll during most reset scenrios. BF IrDA functionlity does not function correctly: The IrDA functionlity on UART0 of the BF535 does not function properly. Workround: Use silicon revision 1.0 or lter BF UART THRE bit ltency: There is ltency issue with the Trnsmit Holding Register of the UART which cn cuse trnsmit dt overrun sitution to occur. In polling mode, the THR Empty (THRE) Bit within NR002556F Pge 10 of 25

11 Medi Pltforms nd Services Group the Line Sttus Register is clered too lte. This cn force subsequent polling opertion to fil. Workround: The Trnsmit Holding Register Empty (THRE) bit cn be polled in softwre to cknowledge tht the previous chrcter loded into the UART hs been sent; t this point, the Trnsmit Holding Register cn be loded with the new chrcter. The following code is required to llow error-free trnsmissions vi the UART by polling the THRE bit of the Line Sttus Register: /* p0 = 0xffc in cse of UART 0 p0 = 0xffc0.1c00 in cse of UART 1 */ #define THRE 0x05 #define LSR 0x0A #define THR 0x00 putc: putc_wit: [--sp] = r1; r1 = w[p0+lsr]; CC = BITTST(r1,THRE); if!cc jump putc_wit; w[p0+thr] = r0; putc_workround: r1 = w[p0+lsr]; CC = BITTST(r1,THRE); if CC jump putc_workround; r1 = [sp++]; rts; Plese note tht the putc_workround loop my fil, if interrupted nd delyed by ny interrupt service routine. BF , BF , BF , BF , BF Rev 0.2 nd 1.0 silicon re not PC133 complint: Rev 0.2 nd 1.0 silicon do not meet the PC133 specifiction. The Externl Bus Interfce Unit will not function relibly bove 100Mhz. Also, for revision 0.2 silicon, the TSDAT requirement (Dt setup prior to rising edge of CLKOUT) of the PC133 specifiction is not met. The prmeters out tht re out of specifiction re listed below: Nme Spec (mx) r0.2 Mrgin TSDAT 2.1ns -750ps For revision 1.0 silicon, tdo (dt output dely) is out of specifiction s follows: Nme Spec (mx) r1.0 Mrgin TDO 6.0ns -150ps NR002556F Pge 11 of 25

12 Medi Pltforms nd Services Group Workround: The BF535 rev 0.2 nd 1.0 silicon meet PC100 from both functionl nd timing stndpoint. BF , BF Writing nd reding ILOC bits: When using the IMEM_CONTROL register to initilize the ILOC bits (to lock the wys) with bit positions 3 through 6, the dt corresponding to these four bits re red bck from bit positions 4 to 7. Workround: The Wys cn still be locked using bits 3-6. If the bits need to be red bck, the vlue written to bit 3 will be red bck from bit 4. The vlue written to bit 4 will be red bck from bit 5. The vlue written to bit 5 will be red bck from bit 6. The vlue written to bit 6 will be red bck from bit 7. BF , BF , BF , BF , BF Boundry Scn does not work in Rev 0.2 silicon: The Boundry scn functionlity does not function correctly on Rev 0.2 silicon. Workround: Use revision 1.0 silicon or lter if Boundry Scn is required BF Icche Flush doesn't invlidte the Fill Buffer: When new cche line is fetched, the line will sty in the fill-buffer until new miss occurs. Thus, if the most recently-fetched line is flushed, nd no new misses occur before the instruction cche ttempts to fetch the sme line gin, the fetch will result in buffer hit. Workround: The workround for this problem is to force n instruction cche miss before the sme line is fetched gin. The problem occurs only if you try to flush line tht could be in the fill buffer. If the user does not flush the next 4 lines when the flush instruction is being executed, there is no possibility of the Flushed line being in the fill buffer. BF , BF , BF , BF , BF PLL trnsitions incorrect coming out of reset: A timing problem in the PLL digitl logic my cuse n undesired stte trnsition when coming out of reset. There re severl conditions tht must be met for this undesired trnsition to hppen. First, the reset must be initited by sserting the reset pin. Softwre resets will not cuse undesired stte trnsitions. Second, specific timing reltionship between the dessertion edge on the reset pin nd the BF535 internl SCLK must NR002556F Pge 12 of 25

13 Medi Pltforms nd Services Group exist. Under these conditions, the BF535 my either ) trnsition to the bypss stte when coming out of reset, b) come up with the incorrect CCLK vlue, or c) come up with the correct CCLK vlue but with n incorrect SCLK vlue. When CCLK is set to run t 300MHz, SCLK my come up incorrectly t 150MHz (SSEL = CCLK/2). If b) or c) hppens, the prt will not boot. The workround must be followed. Workround: A hrdwre nd softwre workround exists. The prt must be plced in bypss by pulling the externl bypss pin high. To ensure tht the prt does come up in bypss, the following circuit must be used for reset nd CLKIN. This circuit should do the following: Keep RESET_B to the DSP low, s n initil condition. RESET_B to the DSP must rise smoothly, shortly fter the flling edge of the DSP CLKIN. RESET_B must pss through negtive edge flip-flop clocked by CLKIN. Two flip-flops re used to reduce the chnce of met-stble outputs nd insure clen rise of the new RESET_B signl. The gte is used to insure the initil condition of RESET_B prior to the strt of CLKIN. The speed of this circuit is frequency nd duty cycle dependent. At the mximum CLKIN frequency of 33 MHz nd 60% duty cycle, the totl dely between CLKIN nd the new reset signl must be less thn 14 ns. Longer CLKIN cycle times provide for slower circuits tht hve longer propgtion dely. The softwre below will then trnsition the BF535 to the desired frequency of opertion. // Begin Bypss workround. // PLL is in Bypss mode when externl bypss pin pulled high // Setup Wtchdog Timer to generte wkeup event to bring DSP out of idle // Set wtchdog count vlue to llow enough time for trnsition nd PLL lock r7.l = 0xfff1; r7.h = 0x0000; p0.l = WDOGCNT & 0xffff; p0.h = WDOGCNT >> 16; [p0] = r7; // Progrm the PLLCTL register to multiply core nd system clock frequency by // setting MSEL nd SSEL bits. In this exmple, MSEL=15x nd SSEL=CCLK/2.5. // This cn be chnged to nother core nd system frequency of choice. r7.l = 0x1F00; r7.h = 0x0001; p0.l = PLLCTL & 0xffff; p0.h = PLLCTL >> 16; [p0] = r7; //After desired MSEL nd SSEL frequency rtios re progrmmed, turn bypss mode // off using the following code sequence. p0.l = PLLCTL & 0xffff; p0.h = PLLCTL >> 16; r7 = [p0]; // Red the vlue in PLLCTL bitclr(r7,8); // Set bypss mode off [p0] = r7; // set the PLLCTL to: PLL not bypssed NR002556F Pge 13 of 25

14 Medi Pltforms nd Services Group // The following code sequence relods the Wtchdog counter. r7.l = 0x0000; r7.h = 0x0000; p0.l = WDOGSTAT & 0xffff; p0.h = WDOGSTAT >> 16; [p0] = r7; // This enbles the wtchdog GP interrupt. r7.l = 0x0004; p0.l = WDOGCTL & 0xffff; p0.h = WDOGCTL >> 16; W[p0] = r7; // Enter IDLE mode to llow PLL to chnged to progrmmed frequency. // The progrmmed wtchdog wkeup event will bring the DSP out of IDLE. cli r7; idle; sti r7; // Cler WD flg nd disble WD events fter DSP comes of IDLE in new frequency. r7.l = 0x8006; p0.l = WDOGCTL & 0xffff; p0.h = WDOGCTL >> 16; W[p0] = r7; // End bypss workround BF , BF , BF Icche bus error does not Flush the Fill Buffer: If bus error occurs during line fetch, the line is not cched (s expected). It is however kept in the buffer until new miss occurs. Thus, if no new misses occur before the instruction cche ttempts to fetch the sme line gin, the fetch will result in buffer hit. Workround: The only known work round for this problem is to force n instruction cche miss to occur before the line obtined during the bus-error is re-fetched. BF , BF , BF , BF , BF Core hngs on specific condition: The core hngs when n interrupt occurs while the first store instruction is in the store buffer nd the conditionl jump instruction nd the second store instruction re still in the pipeline. NR002556F Pge 14 of 25

15 Medi Pltforms nd Services Group The fourth push instruction in the Interrupt Service Routine cuses the core to hng. Workround: Avoid this combintion of instructions fter jump instruction. BF Sport Trnsmit Underflow (TUVF) specil clering instructions: The BF535 BLACKFIN DSP HARDWARE REFERENCE, PRELIMINARY EDITION, NOVEMBER 2001 is not cler on the process steps necessry to cler SPORT trnsmit underflow error. TUVF is n underflow bit within the SPORT_STAT register, nd it is sticky. This sme vlue is sent to the DMA Controller, nd it is used to set the ERR IRQ sttus bit. The TUVF bit is clered on hrd reset. From tht moment on, if it is set, it stys set until the SPORT is reenbled. Tht is, the SPORT must be disbled nd then re-enbled gin. Once the SPORT is enbled, it tkes 4 trnsmit clocks to cler the TUVF. Once TUVF is cler, the DMA's ERR IRQ bit cn then be clered. (with write of "1" to the bit). Workround: The following sequence will cler SPORT trnsmit underflow condition: 1) write TSPEN = 0 nd wit > 1 TSCLK 2) write TSPEN = 1 nd wit > 5 TSCLK + 2 sclks 3) write TSPEN = 0 nd wit > 1 TSCLK BF , BF , BF , BF , BF Incorrect ASTAT flg opertions: AN Flg for Mx/Min is dependent on order of opernds. If R0=+1; R1=-1; R2 = MIN(R1,R0); sets AN R2 = MIN(R0,R1); does not set AN AN nd AZ flgs do not work properly for instructions of the form dreg=(dreg+dreg)<<1,2; The ABS instruction sometimes sets the AN flg even if neither the input or output re negtive. Problem with SIGNBITS instruction: R0.L = SIGNBITS A0; returns -8 through 30 if A0 =0x nd A0 = 0x if A0 = -1 (this is the bug) 39 if A0=0 (should mtch the bove "-1" cse) Workround: None BF , BF , BF , BF , BF Shifter does not consider ll 32 bits when shift vlue is D register: The rithmetic shift instruction msks nd ignores bits tht re greter thn 6 bits. Future NR002556F Pge 15 of 25

16 Medi Pltforms nd Services Group versions of Blckfin DSPs will support lrger shift vlues s described in the Arithmetic Shift section of the Blckfin DSP Instruction Set Reference. Workround: None BF , BF , BF , BF , BF PCI register chnges: The PCI Configurtion Device ID register(pci_cfg_dic) hs reset vlue of 0x in silicon revisions 1.0 nd lter. The PCI Configurtion Vendor ID Register(PCI_CFG_VIC)hs reset vlue of 0x000011D4 in silicon revisions 1.0 nd lter. The vlues of these registers re 0x0 for revision 0.2 silicon. The PCI Device Memory Br Msk Register(PCI_DMBARM) nd the PCI Device IO Br Msk Register(PCI_DIBARM) re not reset during PCI reset. Workround: Provided s info only BF Specultive fetch of illegl or undefined memory loction cuses HW error: A hrdwre error is generted when n illegl or undefined ddress ccess is ttempted, even if the offending instruction is not ctully executed. Given loop written in C of the form: while (p && p->some_vlue) p = p->next; the code generted is: loop_check: check p == 0 if true, skip out of loop lod [p+offset-to-some_vlue] check tht vlue == 0 if true, skip out of loop loop_body: lod [p+offset-to-next] goto loop_check which is correct. Although there is test to check whether p is zero, p->some_vlue is still pre-loded specultively, nd tht cuses hrdwre error if p does not point to vlid loction. Other illegl ccesses, such s n illegl MMR ccess, will result in similr behvior. Workround: In the exmple provided, the NULL pointer corresponds to the first SDRAM ddress, so if SDRAM bnk 0 is initilized, hrdwre error will not be generted. In generl ssembly progrms, CSYNC instruction cn be used to prevent the offending instruction from entering the pipeline. If compiled code is used nd SDRAM is not initilized, hrdwre errors should not be enbled. BF , BF , BF , BF , BF NR002556F Pge 16 of 25

17 Medi Pltforms nd Services Group Accessing MMRs with Dt Cche disbled nd CPLBs enbled: When the progrm is configured with DCPLBs enbled but with cche disbled nd in Write Bck mode, n exception (0x23 - dt ccess CPLB Protection Violtion) is generted on ll MMR ccesses. 1) This problem only occurs when cplbs re enbled nd cche is disbled. 2) DCPLBs MUST be turned off in emultion mode - so we end up getting n unrecoverble event with ny emultion brekpoints. Workround: Use Write Through mode in the DCPLB setup for ll MMR spce nd set s non-ccheble. BF , BF , BF , BF , BF USB: On HOST OUT (PC->BF535) disrm is not functioning correctly: On HOST OUT (PC->BF535), disrming n endpoint should not llow ny more trnsfers to occur on the endpoint. However, trnsfer does occur when endpoint is disrmed. Exmple: A Bulk Out trnsfer should NAK when endpoint is disrmed. But it does not nd the USB device ccepts the pcket. Workround: There re two wys tht the ARM bit in the USBD_EPCFGx should be clered * When the trnsfer is complete * When the Byte count goes to zero. The ppliction softwre would hve to be modified to tke the interrupts (USBD_BCSTAT nd USBD_TC interrupts) nd toggle the direction bit (USBD_DIR) in the USBD_EPCFGx register. This will NAK the trnsfers. BF , BF , BF USB: EPLEN is not updting correctly t the end of short pcket: On HOST OUT (PC -> Device), the EPLEN (endpoint length) register decrements by the pcket size rther thn the ctul number of bytes trnsferred. This is not true if the EPLEN ws progrmmed to be less thn pcket size. Exmple: Strting EPLEN = 320 Trnsferring 259 bytes Ending EPLEN = 0 ( since 320 is multiple of 64) Expected EPLEN = 61 Workround: A heder could be dded indicting the number of bytes tht re being trnsferred whenever doing HOST OUT trnsction. This will be fixed in the next silicon revision. NR002556F Pge 17 of 25

18 Medi Pltforms nd Services Group BF , BF , BF Problems with dt cche writebck mode: When dt write is mde to L2 memory with dt cche on nd configured s writebck, different vlue is sometimes red bck. Workround: Avoid using writebck mode in the referenced silicon revisions prior to rev 1.2. For silicon revisions of 1.2 or lter, n SSYNC instruction must be the first instruction of ny synchronous interrupt service routine whenever dt cche is configured s "write bck". BF , BF , BF , BF , BF Setting brekpoints in n emultor session with cche enbled: When debugging the BF535 with cche enbled, selecting "run" from brekpoint in VisulDSP++ does not dvnce the progrm counter. The brekpoint cn be stepped over using the single step key (f11). At this point, run cn be selected nd the progrm counter will dvnce. Workround: In ddition to the workround described in the problem description, two CPLB's cn be reserved for emultor use: 1 DCPLB for the MMR re, nd 1 ICPLB for the reset vector bsed on the boot mode. Plese dd these two memory res nd CPLB initiliztion vlues to your cche init routine. Attched is simple exmple using cche which shows where these two entries cn be used. // Addresses of the memory res we configure. cplb_ddrs:.byte4 = 0xFFC00000, // MMRs FOR EMULATOR 0xEF000000, // RESET VECTOR FOR EMULATOR <-- this ddress depends on the boot mode selected // Bits to set in the CPLBs cplb_set:.byte4 = (PAGE_SIZE_4MB CPLB_DIRTY CPLB_SUPV_WR CPLB_VALID), // MMRs FOR EMULATOR (PAGE_SIZE_4MB CPLB_DIRTY CPLB_SUPV_WR CPLB_VALID), // // RESET VECTOR FOR EMULATOR BF , BF , BF , BF , BF USB: ARM bit not clering on short pckets: On HOST OUT (PC -> Blckfin), the endpoint does not get disrmed t the end of trnsfer if the progrmmed endpoint length is greter thn the number of bytes received by the device. However the trnsfer complete interrupt is set indicting end of trnsfer. As long s the endpoint is disrmed, no trnsfer tkes plce on tht endpoint. The Host will receive NAKs indicting the device is not redy, nd will retrnsmit if required. By not NR002556F Pge 18 of 25

19 Medi Pltforms nd Services Group disrming, the endpoint is redy for next trnsfer. The firmwre will then hve problems distinguishing between subsequent pckets. Exmple: Strting EPLEN = 320 EPCFG = rmed for bulk out with pcket size of 64 Host send 259 bytes Ending EPCFG = rmed for bulk out with pcketsize of 64 EPINTR = TC is set, BC is not set, PC is set Workround: Tke the interrupt nd cler the ARM bit in the endpoint configurtion register. BF , BF , BF RTC integrity when core powered off: When power to the core is removed, the RTC cn lose ll settings even if the RTC bttery is still supplying power. If power to the core is removed, the RTC must be re-progrmmed with the correct vlues when power to the core is restored. Workround: None BF , BF , BF , BF , BF Seril clock is not gted by SPORT enble bit: If one of the seril clocks, TCLK or RCLK, is configured to be generted internlly, the clock is generted regrdless whether the SPORT module is enbled or not. The seril clock divider, which is updted only when the SPORT is enbled, cn produce unwnted clock pulses with the former SPORT frequency settings generted until the enble bit is set. If the SPORT is enbled for the first time fter reset, the observed frequency is SCLK/2 since the clock divide registers reset ll to zero. Even if the ICLK bit is set t the sme like the SPORT enble bit, set of unwnted clock pulses is generted due to the SPORT enble ltency. Note lso tht these leding clock pulses should not cuse ny issues if the SPORT is disbled nd re-enbled gin with the SCKDIV settings. Workround: To disble the internlly generted clock, first cler the enble bit. In subsequent, seprte write opertion, lso cler the ICLK bit. Connect devices tht tolerte the incorrect leding clock pulses. Note tht most of devices ignore these pulses nywys, since no vlid frme sync is generted during the criticl period. If the connected device cnnot tolerte incorrect clock pulse, the clock signl still cn be gted nd synchronized by off-chip logic controlled by generl-purpose flg pin during initil SPORT setup nd run-time reconfigurtions. BF , BF , BF , BF , BF NR002556F Pge 19 of 25

20 Medi Pltforms nd Services Group V minimum VDDcore required: For silicon revisions prior to 1.2, the prt will not operte properly if VDDcore is below 1.38V. Workround: For silicon revisions prior to 1.2, hve VDDcore bove 1.38V. Silicon revisions fter 1.2 cn operte properly with VDDcore below 1.38V s specified in the dtsheet. BF , BF , BF SPORT Multichnnel Mode strting nd stopping: If using the SPORTs in multichnnel mode, the dt will be corrupted if the SPORTs re first enbled, then disbled, nd re-enbled gin. 37. Workround: The following sequence provides correct dt trnsmission if enbling, disbling, nd reenbling the SPORTs re necessry: Disble SPORT -> Disble MCM opertion -> Set FLSH bit in DMA config register -> wit 4 SPORT clock cycles -> CLR FLSH bit in DMA config register -> Stop DMA This sequence must be completed before the next frme sync comes in. The SPORTs must be stopped on completion of DMA trnsfer. If they re stopped midwy through multichnnel mode DMA trnsfer, then on restrt you will get unpredictble results. Both RX nd TX re stopped seprtely. TX is stopped in the TX interrupt routine when it completes trnsmitting. RX is stopped in the RX interrupt routine when it completes receiving. The Disbling of MCM opertion MUST be done in the RX interrupt routine, this step should not be done in the TX Interrupt routine. BF , BF , BF , BF , BF CLI instruction cn llow n synchronous interrupt occur s it is committing: The CLI instruction is intended to block interrupt processing for criticl sections of code. The CLI instruction commits t the end of the pipe, nd strts blocking interrupts until n STI instruction re-enbles interrupt processing. If higher priority interrupt occurs just before the CLI commits, the interrupt my be serviced immeditely fter the CLI hs committed. This mens tht rther thn few criticl cycles before executing the STI, the entire higher priority interrupt service routine will be executed. If third, highest priority interrupt signls during this period, it will not be serviced until the STI is finlly executed. This dditionl ltency is unintended. Workround: The STI instruction should block interrupts just before its commit point, so tht it opertes tomiclly in the instruction strem. This is similr in behvior to the POP RETI instruction. A POP RETI cn be used s softwre workround. Replce ech CLI instruction with: RETI=[sp++]; // blocks new interrupts, sets IPEND<4> CLI R0; // modifies IMASK NR002556F Pge 20 of 25

21 Medi Pltforms nd Services Group [--sp]=reti; // restores stck to wht it ws, unsets IPEND<4>. Note tht we don't hve to ctully be pointing to vlid RETI on the stck for this to work; s long s there is stck, this will block interrupts for the CLI instruction. BF , BF , BF , BF , BF Store to Lod Forwrding in Write Through Mode: When the L1 Dt memory is configured s Cche in Write Through mode, under certin conditions when store is followed by lod to the sme ddress, the lod cn return incorrect dt. The conditions re detiled below: - DCACHE is configured in WT mode - A Lod strts line fill to certin ddress Between the bove Lod nd the below Store, one of the following events needs to occur: * Mispredicted Brnch * Interrupt * Exception * RTI/RTE/RTN/RTX instruction - A store to n ddress in the sme line is issued to the Store buffer. - The current store misses in the DCche s line fill to the line is in progress. - The store buffer writes the store to the Write Buffer - The line fill completes nd the dt is written into the Cche (Remember the line fill hs the dt without the ltest store) - A lod is issued to the sme ddress s in the Write Buffer - The lod "hits" in the Dt Cche nd provides incorrect dt. Workround: Plce n SSYNC instruction to seprte the Store from the first line fill. This will ensure the store gets out of the Store buffer fter the line fill is completed. OR Operte the Dt Cche in WB mode. This issue does not exist in WB mode BF , BF , BF , BF , BF Dt cche dirty bit set when lod-miss-fill is in progress: When Fill is in progress due to Lod Miss nd one of the following events occur : - Mispredicted Brnch - RTI, RTE, RTX, RTE, RTN instructions - Interrupts nd Exceptions NR002556F Pge 21 of 25

22 Medi Pltforms nd Services Group - Single Step Mode on completion of the Fill when the line is written into the Dt cche, the Dirty Bit for the line is incorrectly Set. The dirty bit is set in both Write Bck (WB) nd Write Through (WT) modes. Exmples of Code tht will expose the errt: ========================================== 1. r0 = 1; cc = r0; if cc jump 0x4; r0 = [p0] = r0; // Lod tht misses nd is Aborted // due to BRT 2. r0 = 1; cc = r0; [p0] = r0; if cc jump 0x4; // Lod tht misses nd // Genertes Kill EX3 fter // the lod completes // but before the Fill finishes 3. [p0] = r0; // Lod tht misses RTI; // Genertes Kill EX3 //fter the lod completes // but before the Fill finishes. 1. Since the Dirty bit is set, when tht line is either replced or "Flushed", it will cuse copy bck to the lower levels of memory, thereby, impcting the overll performnce. 2. Since the Dirty bit is set for Lods, when the line is either replced or Flushed, copy bck will be issued. This will lso occur for Red-Only sections of memory, therefore could hve impct to the functionlity of the system. 3. Since the Dirty bit is set for the WT mode s well, copy bck tht re issued my cuse coherency issues with lower level memory unless mnged by SW. Workround: When progrmming in C, mke sure ny buffer tht is mlloc'ed is "flushed" before re-using this memory spce. Also ensure the following conditions re met: - Mispredicted Brnch - Plce n SSYNC t the First Instruction of the Brnch Trget - Interrupt & Exceptions - Plce n SSYNC t the First instruction of the ISR - RTI/RTE/RTN/RTX instruction - Plce CSYNC fter every RTI/RTN/RTE/RTX instruction BF , BF , BF , BF , BF PLL clkout my be incorrect in multiplier mode coming out of reset: When powering up the Processor in multiplier mode (BYPASS pin low), the system clock my hve n incorrect duty-cycle or show n unexpected DC offset or both. This cn dversely ffect the Processor's opertion. NR002556F Pge 22 of 25

23 Medi Pltforms nd Services Group Workround: The recommended wy of powering up the Processor is by using the PLL's BYPASS mode (BYPASS pin high) nd setting the core nd system clocks in softwre s shown in the code exmple below. The MSEL nd DF pins re irrelevnt in this mode (the corresponding bits re set to zero in the PLL_CTL register) nd booting will execute t CLKIN/2 speed. If this is uncceptble, the Processor must be monitored in some wy. For instnce, the user code could set flg pin or communicte with host. Absence of such signl would trigger reset of the device. // Begin Bypss workround. // PLL is in Bypss mode when externl bypss pin pulled high // Setup Wtchdog Timer to generte wkeup event to bring DSP out of idle // Set wtchdog count vlue to llow enough time for trnsition nd PLL lock // The following sets the wtchdog to timeout fter pprox SCLK cycles. // This is conservtive number tht will work for ll combintions of // frequency settings. // It cn be dpted to the prticulr frequencies in your ppliction in the // following fshion: // A minimum time of 2000 CLKIN cycles is recommended s per the dtsheet. // The wtchdog is clocked by SCLK. SCLK is (CLKIN/2)/SSEL t powerup nd will // be CCLK/SSEL fter the trnsition. If we ssume tht the end vlue is // pplied for the entire durtion of the trnsition (worst cse), it follows // tht the correct vlue for the wtchdog counter is equl to: // counter_vlue = 2000 * CCLK_rtio / SSEL // where SSEL = 2, 2.5, 3, 4 nd // CCLK_rtio = rtio between CCLK nd CLKIN, defined by MSEL nd DF settings. r7.l = 0x6800; // cn be chnged ccording to formul bove r7.h = 0x0000; p0.l = WDOGCNT & 0xffff; p0.h = WDOGCNT >> 16; [p0] = r7; // Progrm the PLLCTL register to multiply core nd system clock frequency by // setting MSEL nd SSEL bits. In this exmple, MSEL=15x nd SSEL=CCLK/2.5. // This cn be chnged to nother core nd system frequency of choice. r7.l = 0x1F00; r7.h = 0x0001; p0.l = PLLCTL & 0xffff; p0.h = PLLCTL >> 16; [p0] = r7; NR002556F Pge 23 of 25

24 Medi Pltforms nd Services Group //After desired MSEL nd SSEL frequency rtios re progrmmed, turn bypss mode // off using the following code sequence. p0.l = PLLCTL & 0xffff; p0.h = PLLCTL >> 16; r7 = [p0]; // Red the vlue in PLLCTL bitclr(r7,8); // Set bypss mode off [p0] = r7; // set the PLLCTL to: PLL not bypssed // The following code sequence relods the Wtchdog counter. r7.l = 0x0000; r7.h = 0x0000; p0.l = WDOGSTAT & 0xffff; p0.h = WDOGSTAT >> 16; [p0] = r7; // This enbles the wtchdog GP interrupt. r7.l = 0x0004; p0.l = WDOGCTL & 0xffff; p0.h = WDOGCTL >> 16; W[p0] = r7; // Enter IDLE mode to llow PLL to chnged to progrmmed frequency. // The progrmmed wtchdog wkeup event will bring the DSP out of IDLE. cli r7; idle; sti r7; // Cler WD flg nd disble WD events fter DSP comes of IDLE in new frequency. r7.l = 0x8006; p0.l = WDOGCTL & 0xffff; p0.h = WDOGCTL >> 16; W[p0] = r7; // End bypss workround When the prt is booted in PLL bypss mode, it is importnt to run the workround code before connecting with n ICE. This is due to the fct tht CCLK must be t lest twice the JTAG frequency to mke successful connection. BF , BF Rev 1.2 nd 1.3 silicon do not meet TDCAD requirement of the PC133 spec: Rev 1.2 nd 1.3 silicon does not meet TDCAD requirement of the PC133 specifiction. NR002556F Pge 24 of 25

25 Medi Pltforms nd Services Group For 25 degrees C nd bove, Nme Spec Mesured Vlue TDCAD 0.6 ns 0.7 ns Workround: From functionl nd timing stndpoint, the SCLK speed cn be lowered in order to meet the TDCAD requirement. BF , BF Ltency in Writes to RND_MOD bit: For the cse when "move" is mde to ASTAT followed by multiply/mac instruction, the RND_MOD bit is used directly from the ASTAT register, nd the vlue does not chnge until the new ASTAT vlue is committed. The following exmple demonstrtes this issue. The result of the R0.L nd R1.L multiply is incorrect. R2 = ASTAT; //Red ASTAT register. BITSET(R2, ASTAT_RND_MOD_P); //Set the RND_MOD bit. ASTAT = R2; //Write result bck to ASTAT register. R0.L = R0.L*R1.L; //Perform multiply. R0 = R0.L (X); //Sign extend R0 Workround: Inserting two nops fter the write to the ASTAT register tkes cre of the ltency. In the exmple code bove tht demonstrtes this problem, the following exmple code resolves the issue. R2 = ASTAT; //Red ASTAT register. BITSET(R2, ASTAT_RND_MOD_P); //Set the RND_MOD bit. ASTAT = R2; //Write result bck to ASTAT register. nop; nop; //Insert two nops to resolve ltency issue. R0.L = R0.L*R1.L; //Perform multiply. R0 = R0.L (X); //Sign extend R0 In this exmple, the result of the R0.L nd R1.L multiply is correct. This workround hs lso been implemented in the mult_r() librry function, nd will be vilble in the August 2004 updte of the VisulDSP relese. BF , BF , BF , BF , BF IDCODE register not JTAG IEEE complint: The BF535 does not meet the JTAG IEEE spec for the IDCODE register. The JTAG IDCODE register on the BF535 shifts out the MSB first. However, the JTAG IEEE spec sttes tht the LSB must be scnned first. Workround: JTAG softwre should be chnged such tht it looks for bit-reversed IDCODE output. BF , BF , BF , BF , BF NR002556F Pge 25 of 25