Lecture 9: Microcontrolled Multi-Cycle Implementations

Transcription

1 8-447 Lectre 9: icroled lti-cycle Implementations James C. Hoe Dept of ECE, CU Febrary 8, 29 S 9 L9- Annoncements: P&H Appendi D Get started t on Lab Handots: Handot #8: Project (on Blackboard) Single-Cycle Implementations S 9 L9-2 atches natrally with the seqential and atomic semantics inherent to most ISAs instantiate programmer-visible state one-for-one map instrctions to combinational net-state logic Bt, contrived and inefficient all instrctions rn as slow as the slowest instrction mst provide worst-case combinational resorce in parallel as reqired by any instrction Not necessarily the simplest way to implement an ISA Imagine trying to bild a single-cycle implementation of a CISC ISA

2 Single-Cycle Datapath Analysis Assme memory nits (read or write): 2 ps ALU and adders: ps file (read or write): 5 ps other combinational logic: ps S 9 L9-3 steps IF ID EX E WB resorces mem RF ALU mem RF Delay R-type I-type LW SW Branch Jmp 2 2 Worksheet S 9 L9-4 [25 ] Shift Jmp address [3 ] left PCSrc =Jmp PC+4 [3 28] Add ALU reslt 4 Add RegDst Jmp Branch Shift left 2 PCSrc 2 =Br Taken [3 26] Control em emtoreg ALUOp em ALUSrc Reg PC address [3 ] memory [25 2] [2 6] [5 ] 2 Registers 2 bcond Zero ALU ALU reslt Address Data memory [5 ] 6 32 Sign etend ALU ALU operation [5 ] [Based on figres from P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.]

3 S 9 L9-5 lti-cycle Implementation: Ver. Why not let each instrction type take only as mch time as it needs Idea rn a 5 ps clock let each instrction type take as many clock cycles as needed programmer-visible state only pdates at the end of an instrction s cycle-seqence an instrction s s effect is still prely combinational from PVS to PVS A more realistic alternative to the variable-length clock design in the tetbook lti-cycle Datapath: Ver. S 9 L9-6 [25 ] Shift Jmp address [3 ] left PCSrc =Jmp PC+4 [3 28] Add ALU reslt 4 Add RegDst Jmp Branch Shift left 2 PCSrc 2 =Br Taken [3 26] Control em emtoreg ALUOp em ALUSrc Reg PC address [3 ] memory [25 2] [2 6] [5 ] 2 Registers 2 bcond Zero ALU ALU reslt Address Data memory [5 ] 6 32 Sign etend ALU PVSEn [5 ] [Based on figres from P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.]

4 Seqential Control: Ver. S 9 L9-7 IF IF 2 IF 3 IF 4 ID Jmp / PVSEn EX WB Branch / PVSEn I-type or R-type EX 2 LW or SW LW SW / PVSEn E 4 E 3 E 2 E What abot the rest of the signals? icroseqencer: Ver. S 9 L9-8 RO as a combinational logic lookp table ** RO size grows as O(2 n ) as the nmber of inpts literally holds the trth table Combinational logic 2 n rows address Inpts n / inpt Otpts PVSEn Datapath otpts ** RO size grows as O(m) as the nmber of otpts ealy or oore? Inpts from instrction opcode field State Net state [Based on figres from P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.]

5 icrocoding: Ver. S 9 L9-9 state label cntrl flow conditional targets R/I- type LW SW Br Jmp IF net IF 2 net IF 3 net IF 4 branch ID ID ID ID IF ID net EX net EX 2 branch WB E E IF - E net E 2 net E 3 net E 4 net - WB IF - - WB branch IF IF IF IF IF A systematic approach to FS seqencing/ icroler A stripped-down processor for seqencing and states are like µpc µpc indeed into a µprogram RO to select an µinstrction well-formed -flow architectre fields in the µinstrction maps to signals Why not also spport µprogram-visible states and ALU ops? Very elaborate mlers have been bilt some µlers had fll-fledged ISAs µisas for CISC machines in many ways inspired RISC ISA Adder icrocode storage Inpt Otpts icroprogram conter Address select logic Inpts from instrction opcode field Seqencing S 9 L9- Datapath otpts [Based on figres from P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.]

6 Performance Analysis S 9 L9- T wall-clock = No.s CPI T clk No. is fied for a given ISA and application mi For a fied ISA and application mi it is meaningfl to compare T avg-inst = CPI T clk or IPS = IPC f clk million instrctions per second freqency in Hz instrctions per cycle Performance Analysis S 9 L9-2 Single-Cycle Implementation,667Hz = 667 IPS lti-cycle Implementation IPC avg 2, Hz = 2235 IPS what is average behavior? Assme: 25% LW, % SW, 45% ALU, 5% Branch and 5% Jmps weighted arithmetic mean of CPI 8.95 weighted harmonic mean of IPC.7

7 S 9 L9-3 Redcing Datapath by Resorce Rese Add How to rese the same adder for both additions in the same instrction PC address memory 4 25:2 2:6 5: RegDest isitype 2 Registers Reg Sign etend 3 ALU operatio Zero ALU ALU reslt ALUSrc isitype Previos eample of rese by mtally eclsive conditions [Based on figres from P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.] Redcing Datapath by Seqential Rese S 9 L9-4 Add PC address memory 4 IR 25:2 2:6 2 Registers 5: d 2 Reg 4 3 ALU Zero ALU ALU reslt to IR or not to IR? [Based on figres from P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.]

8 Removing Redndancies S 9 L9-5 PC Address emory Data or emory Data Register # Registers Register # Register # A B ALU ALUOt - Cold also redce down to a single read-write port! - Do we want to remove all redndancies? [Based on figres from P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.] Control Points S 9 L9-6 PCCond PCSorce PC Address emory emdata [3-26] [25 2] [2 6] [5 ] [5 ] emory PC IorD em em emtoreg IR [25 ] [5 ] Otpts Control Op [5 ] ALUOp ALUSrcB ALUSrcA Reg RegDst 6 2 Registers Sign etend 2 32 Shift left 2 A B Shift left 2 ALU PC [3-28] Zero ALU ALU reslt Jmp address [3-] ALUOt 2 [5 ] [Based on figres from P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.]

9 New Seqential Control Signals S 9 L9-7 When De-asserted When asserted ALUSrcA IorD IR PC PCCond st ALU inpt from PC st ALU inpt from st RF read port (latched in A) PC spplies memory ALUOt spplies memory address address IR latching disabled no effect IR latching enabled PC latching enabled nconditionally no effect PC latching enabled only if branch condition is satisfied When both PC and PCCond are de-asserted, PC latching is disabled New Seqential Control Signals S 9 L9-8 signal ALUSrcB[:] PCSorce[:] effect 2 nd ALU inpt from 2 nd RF read port (latched in B) 2 nd ALU inpt is 4 (for PC increment) 2 nd ALU inpt is sign-etended IR[ 5: ] 2 nd ALU inpt is sign-etended IR[ 5: ], net PC from ALU net PC from ALUOt net PC from IR (jmp target) t)

10 Old Control Signals (similar to single-cycle) S 9 L9-9 RegDest Reg When De-asserted RF write select according to IR[2:6] RF write disabled When asserted RF write select according to IR[5:] RF write enabled em em emory read disabled emory read port retrn load vale emory write disabled emory write enabled emtoreg Steer ALU reslt (latched in ALUOt) to RF write port steer memory load reslt (latched in DR) to RF write port Synchronos Register Transfers S 9 L9-2 Synchronos state with latch enables PC, IR, RF, E Synchronos state that always latch A, B, ALUOt, DR One can enmerate all possible combinational transfers in the path For eample starting from PC IR E[ PC ] reqires IR=, IorD=, em= PC PC,JmpTarget reqires PC=, PCSorce=2 b PC PC+ALUSrcB DR E[ PC ] ALUOt PC + ALUSrcB

11 Usefl Register Transfers S 9 L9-2 PC PC+4 PC ALUOt (if PCCond is asserted) PC PC[ 3:28 ],IR[ 25: ],2 b IR E[ PC ] A RF[ IR[ 25:2 ] ] B RF[ IR[ 2:6 ] ] ALUOt A + B ALUOt A + sign-etend (IR[ 5: ]) ALUOt PC + ( sign-etend (IR[ 5: ]) <<2 ) DR E[ ALUOt ] E[ ALUOt ] B RF[ IR[ 5: ] ] ALUOt, RF[ IR[ 2:6 ] ] ALUOt RF[ IR[ 2:6 ] ] DR RT Seqencing: R-Type ALU S 9 L9-22 IF ID IR E[ PC ] PC PC+4 A RF[ IR[ 25:2 ] ] B RF[ IR[ 2:6 ] ] EX ALUOt A + B E WB if E[PC] == ADD rd rs rt GPR[rd] GPR[rs] + GPR[rt] PC PC + 4 RF[ IR[ 5: ] ] ALUOt

12 RT Datapath Conflicts S 9 L9-23 PC PC+4 PC ALUOt RF[ IR[ 5: ] ] ALUOt, RF[ IR[ 2:6 ] ] ALUOt PC PC[ 3:28 ],IR[ 25: ],2 b RF[ IR[ 2:6 ] ] DR IR E[ PC ] B RF[ IR[ 2:6 ] ] ALUOt A + sign-etend (IR[ 5: ]) ALUOt A + B A RF[ IR[ 25:2 ] ] ALUOt PC + ( sign-etend (IR[ 5: ]) <<2 ) E[ ALUOt ] B DR E[ ALUOt ] Can tilize each resorce only once per step (cycle) RT Seqencing: R-Type ALU S 9 L9-24 IF ID EX IR E[ PC ] PC PC+4 A RF[ IR[ 25:2 ] ] B RF[ IR[ 2:6 ] ] ALUOt A + B E WB RF[ IR[ 5: ] ] ALUOt step step 2 step 3 step 4

13 RT Seqencing: LW IF ID IR E[ PC ] PC PC+4 A RF[ IR[ 25:2 ] ] B RF[ IR[ 2:6 ] ] EX ALUOt A + sign-etend (IR[ 5: ]) E DR E[ ALUOt ] WB RF[ IR[ 2:6 ] ] DR S 9 L9-25 if E[PC]==LW rt offset 6 (base) EA = sign-etend(offset) + GPR[base] GPR[rt] E[ translate(ea) ] PC PC + 4 RT Seqencing: Branch IF ID EX IR E[ PC ] PC PC+4 A RF[ IR[ 25:2 ] ] B RF[ IR[ 2:6 ] ] ALUOt PC+( sign-etend (IR[ 5: ])<<2 ) PC ALUOt (only if condition is met) E S 9 L9-26 WB if E[PC]==BEQ rs rt immediate 6 target = PC + sign-etend(immediate) 4 +4 if GPR[rs]==GPR[rt] then PC target else PC PC + 4

14 Combined RT Seqencing S 9 L9-27 com mmon steps opcode d ependent steps R-Type LW SW Branch Jmp start: IR E[ PC ] PC PC+4 A RF[ IR[ 25:2 ] ] B RF[ IR[ 2:6 ] ] ALUOt PC + ( sign-etend case (IR[ 5: ]) <<2 ) opcode net PC ALUOt A + ALUOt A + signetend (IR[ 5: ]) etend (IR[ 5: ]) gotoir[25:],2 b net net net start start ALUOt A + sign- PC ALUOt PC[3:28], B RF[ IR[5:] ] DR E[ALUOt] B ALUOt E[ALUOt] goto goto net start start RF[IR[5:]] DR goto start RTs in each state corresponds to some setting of the signals Horizontal icrocode S 9 L9-28 icrocode storage Otpts n-bit µpc inpt Inpt ALUSrcA IorD Datapath IR otpts PC PCCond. k-bit otpt Adder icroprogram conter Seqencing Address select logic Inpts from instrction opcode field [Based on figres from P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.] Control Store: 2 n k bit (not inclding seqencing)

15 Vertical icrocode icrocode storage Otpts n-bit µpc inpt Inpt PC PC+4 PC ALUOt Datapath PC PC[ 3:28 ],IR[ 25: ],2 b IR E[ PC ] otpts A RF[ IR[ 25:2 ] ] B RF[ IR[ 2:6 ] ].. S 9 L9-29 -bit signal means do this RT (or combination of RTs) m-bit inpt Adder icroprogram conter Seqencing RO Address select logic k-bit otpt [Based on figres from P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.] Inpts from instrction opcode field ALUSrcA IorD IR PC PCCond. If done right (i.e., m<<n, and m<<k), two ROs together (2 n m+2 m k bit) shold be smaller than horizontal microcode RO (2 n k bit) icrocoding for CISC S 9 L9-3 Can we etend the µler and path to spport a new instrction I haven t thoght of yet to spport a comple instrction, e.g. polyf to spport a comple instrction, e.g. polyf Yes, and probably more if I can seqence an arbitrary RISC instrction then I can seqence an arbitrary RISC program as a µprogram seqence will need some µisa state (e.g. loop conters) for more elaborate µprograms l b ISA f l k lif i more elaborate µisa featres also make life easier µcoding allows very simple path do very powerfl comptation a path as simple as a Trning machine is niversal µcode enables a minimal path to emlate any ISA yo like (with a commensrate slow down)

16 Nanocode and illicode Nanocode a level below µcode µprogrammed for sb-systems (e.g., a complicated cat floating-point nt modle) that acts as a slave in a µled path e.g., the polyf seqence may be generated by a separate nanoler in the FPU illicode a level above µcode ISA-level sbrotines hardcoded into a RO that can be called by the µler t to handle really complicated operations e.g., to add polyf to IPS, one may code p polyf as a software rotine that is called by the µler when the polyf opcode is decoded In both cases, we avoid complicating the main µler with polyf spport The power of abstractions!! S 9 L9-3 Nanocode Concept Illstrated S 9 L9-32 a mcoded processor implementation RO PC processor path We refer to this as nanocode when a mcoded sbsystem is embedded in a mcoded system a mcoded FPU implementation RO PC arithmetic path