EEC 483 Computer Organization

Transcription

1 EEC 83 Compter Organization Chapter.6 A Pipelined path Chans Y Pipelined Approach 2 - Cycle time, No. stages - Resorce conflict E E A B C D 3 E E 5 E c.y9@csohio.ed

2 Resorces sed in 5 Stages (revisit) Stages Instrction Fetch () Instrction Decode/Register Fetch () Eecte, ress comptation, Brach/Jmp completion () emory access or R-type completion (E) emory read completion () Register File ALU emory 3 Now, what are the problems? And what are the soltions? c.y9@csohio.ed Resorce Conflicts (revisit) Step name Instrction fetch Instrction decode/ fetch Action for R-type instrctions Action for -reference Action for instrctions branches IR = emory[] = + A = Reg [IR[25-2]] B = Reg [IR[2-6]] ALUOt = + (sign-etend (IR[5-]) << 2) Action for jmps Eection, address ALUOt = A op B ALUOt = A + sign-etend if (A ==B) then = [3-28] II comptation, branch/ (IR[5-]) = ALUOt (IR[25-]<<2) jmp completion emory access or R-type Reg [IR[5-]] = Load: DR = emory[aluot] completion ALUOt or Store: emory [ALUOt] = B emory read completion Load: Reg[IR[2-6]] = DR ALU conflict emory conflict Register file conflict (read or write) c.y9@csohio.ed 2

3 Resorce Conflicts ALU : sed in,, and stages (at time 5, instrctions??? collide) emory : sed in and E stages (at time 5, instrctions??? collide) Register : sed in, E and stages (at time 5, instrctions??? collide) E 2 E 3 E E 5 E c.y9@csohio.ed Soltions to Resorce Conflicts ALU : sed in,, and stages 2 additional adders as in single cycle implementation emory : sed in and E stages Two independent memories : instrction and as in single cycle implementation Register : sed in, E and stages ing (s) in stage Writing into a in E stage Writing into a in stage conflict??? conflict??? 6 c.y9@csohio.ed 3

4 Basic Pipeline : Instrction fetch : Instrction decode/ file read : Eecte/ address calclation E: emory access : back ress Instrction Instrction Registers 6 2 etend reslt reslt ress Instrctions and move generally from left to right throgh the five stages as they complete eection ecept two cases. - stage - selection 7 c.y9@csohio.ed Basic Pipeline Step name Instrction fetch Instrction decode/ fetch Action for R-type instrctions Action for -reference Action for instrctions branches IR = emory[] = + A = Reg [IR[25-2]] B = Reg [IR[2-6]] ALUOt = + (sign-etend (IR[5-]) << 2) Action for jmps Eection, address ALUOt = A op B ALUOt = A + sign-etend if (A ==B) then = [3-28] II comptation, branch/ (IR[5-]) = ALUOt (IR[25-]<<2) jmp completion emory access or R-type Reg [IR[5-]] = Load: DR = emory[aluot] completion ALUOt or Store: emory [ALUOt] = B emory read completion Why move?? ZF is available dring stage, anyway. Why do we still need 2 ALUs at stage? (one for A-B and the other for +IR) Load: Reg[IR[2-6]] = DR 8 c.y9@csohio.ed

5 Basic Pipeline : Instrction fetch : Instrction decode/ file read : Eecte/ address calclation reslt E: emory access : back Now, don t we have any other resorce conflicts? ress Instrction Instrction Registers 6 2 etend reslt ress => We actally remove strctral hazards only, bt there still are other types of hazards. 9 c.y9@csohio.ed Basic Pipeline : Instrction fetch ress Instrction Instrction : Instrction decode/ file read Registers 6 2 etend : Eecte/ address calclation reslt reslt E: emory access ress : back At time 5, inst. ses resorces in stage, inst. 2 ses resorces in E stage,.. inst. 5 ses resorce in stage. c.y9@csohio.ed 5

6 Pipelined path / / /E E/ reslt to the basic pipeline in order to actally split the path into stages. ress Instrction Instrction Registers 6 2 etend reslt ress The info. mst be placed in a pipeline ; otherwise, it is lost when the net instrction enters that pipeline stage. For store instrction, (?) => / pipeline => /E pipeline => (?) c.y9@csohio.ed Pipelined path / / /E E/ reslt ress Instrction Instrction Registers 2 reslt ress 6 etend Can yo find a problem even if there are no dependencies? What instrctions can we eecte to manifest the problem? 2 c.y9@csohio.ed 6

7 Corrected path / / /E E/ reslt ress Instrction Instrction Registers 2 6 etend reslt ress??? 3 c.y9@csohio.ed Eample Five instrctions go throgh the IPS pipeline: lw $, 2($) (8c2a ) sb$, $2, $3 (3 582) and$2, $, $5 (85 626) or $3, $6, $7 (c7 6827) add$, $8, $9 (9 72) $pc = 5 [ ] = $ = [ ] = $9 = 9 c.y9@csohio.ed 7

8 5 6 8

9 7 8 9

10 9 2 c.y9@csohio.ed

11 Content of Pipeline Registers Which shold be passed throgh stages? I.e., what are the contents of pipeline s? In / pipeline (), Inst. () In / pipeline (), Reg. (), Reg. 2 (), Offset (), Reg. no. 2 and 3 () In /E pipeline (), ZF (), ALUOt (), Reg. 2 (), Reg. no. (5) In E/ pipeline emory (), ALUOt (), Reg. no. (5) 2 c.y9@csohio.ed Graphically Representing Pipelines Program eection order (in instrctions) lw $, 2($) Time (in clock cycles) CC CC 2 CC 3 CC CC 5 CC 6 I Reg ALU D Reg sb $, $2, $3 I Reg ALU D Reg Can help with answering qestions like: how many cycles does it take to eecte this code? what is the ALU doing dring cycle? se this representation to help nderstand paths 22 c.y9@csohio.ed

12 Five instrctions go throgh the IPS pipeline lw $, 2($) (8c2a ) sb$, $2, $3 (3 582) and$2, $, $5 (85 626) or $3, $6, $7 (c7 6827) add$, $8, $9 (9 72) Register contents emory contents $pc = 5 [ ] = $ = [ ] = $9 = 9 23 c.y9@csohio.ed add $, $8, $9 or $3, $6, $7 and $2, $, $5 sb $, $2, $3 lw $, 2($) / / /E E/ (a) (j) (m) (b) reslt (q) (t) ress Instrction (c) Instrction (d) (k) (e) Registers (f) (l) 2 (g) (n) (o) reslt (r) () ress (v) () (y) (g) (z) (h) 6 etend (p) (i) (s) (w) (f) 2 c.y9@csohio.ed 2