1048: Computer Organization

Transcription

1 48: Compter Organization Lectre 5 Datapath and Control Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-

2 Recap: A Single-Cycle Processor PCSrc 4 Add Shift left 2 Add ALU reslt PC address memory register register 2 Write register Write data Registers data data 2 RegWrite 6 Sign 32 etend ALUSrc 4 3 ALU operation Zero ALU ALU reslt Address Write data em emwrite data Data memory emtoreg CPI= Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-2

3 What s Wrong with Single-cycle? Arithmetic & Logical PC Inst emory Reg File m ALU m setp Load PC Inst emory Reg File m ALU Data em m Critical Path Store PC Inst emory Reg File m ALU Data em setp Branch PC Inst emory Reg File cmp m Long cycle time All instrctions take same time as the slowest path Real memory is not so ideal cannot always get job done in one (short) cycle An FU can only be sed once => higher cost Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-3

4 lticycle Approach Break p the instrctions into steps, each step takes a cycle balance the amont of work to be done restrict each cycle to se only one major fnctional nit share fnction nits within the eection of a single instrctions Add mltipleor for sharing datapath At the end of a cycle store vales for se in later cycles (easiest thing to do) introdce additional internal registers Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-4

5 Otline Part A: Designing a Single-Cycle Processor Part B: Designing a lticycle Processor Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-5

6 Part B Otline A mlticycle implementation lticycle datapath lticycle eection steps lticycle control (Appendi C.3) icroprogramming: simplifying control (Appendi C.4) Eceptions Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-6

7 lticycle Implementation Redce cycle time Diff. Inst. take diff. cycles Share fnctional nits storage element storage element Acyclic Combinational Logic => Acyclic Combinational Logic (A) storage element Acyclic Combinational Logic (B) storage element storage element 5B-7

8 Partition Single-Cycle Datapath Add registers between smallest steps Ins. fetch RF access ALU operation memory access PCSrc 4 Add Shift left 2 Add ALU reslt PC address memory register register 2 Write register Write data Registers data data 2 RegWrite 6 Sign 32 etend ALUSrc 4 3 ALU operation Zero ALU ALU reslt Address Write data em emwrite data Data memory emtoreg

9 lticycle Datapath memory (instr. & data), ALU (addr, PC+4, add, ), registers (IR, DR, A, B, ALUOt) Storage for sbseqent inst. (arch.-visible) vs. storage for same inst. bt in a sbseqent cycle Fig PC Address emory Data or data register emory data register Data Register # Registers Register # Register # A B ALU ALUOt Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-9

10 lticycle Datapath for Basic Instr. IorD em emwrite IRWrite RegDst RegWrite ALUSrcA PC Address Write data emory emdata [25 2] [2 6] [5 ] register [5 ] emory data register [5 ] 6 register register 2 Registers Write register Write data Sign etend data data 2 32 Shift left 2 A B ALU control Zero ALU ALU reslt ALUOt [5 ] Fig emtoreg ALUSrcB ALUOp IR and PC need write control, bt others don t UX to select 2 sorces to memory; memory needs read signal PC and A to one ALU inpt; for sorces to another inpt 5B-

11 Adding Branch/Jmp Fig PC Address Write data emory emdata [3-26] [25 2] [2 6] [5 ] register [5 ] emory data register PCWriteCond PCWrite IorD Otpts em emwrite Control emtoreg IRWrite [25 ] [5 ] Op [5 ] PCSorce ALUOp ALUSrcB ALUSrcA RegDst 6 RegWrite register register 2 Registers Write register Write data Sign etend data data 2 32 Shift left 2 A B Shift 28 left 2 ALU control PC [3-28] Zero ALU ALU reslt Jmp address [3-] ALUOt 2 [5 ] Three sorces to PC Two PC write signals 5B-

12 Different Register Types Data reqired by sbseqent instrctions stored in programmable-visible state elements register file ($s, $t, ), PC, data memory Data sed by the same instrction in later cycles stored in additional temporary registers not programmer-visible implementation-independent Where to insert additional temporary registers? to evenly partition the combinational logic (ideal case) what data are needed in later cycles Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-2

13 Otline A mlticycle implementation lticycle datapath lticycle eection steps lticycle control (Appendi C.3) icroprogramming: simplifying control (Appendi C.4) Eceptions Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-3

14 Five Eection Steps Fetch Decode and Register Fetch Eection, emory Address Comptation, or Branch Completion emory Access or R-type Completion emory Completion (Write-back) INSTRUCTIONS TAKE FRO 3 ~ 5 CYCLES! Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-4

15 Step : Fetch Use PC to get instrction and pt it in the Register (IR) Increment the PC by 4 and pt the reslt back in the PC Can be described sccinctly sing RTL (Register-Transfer Langage) IR = emory[pc]; PC = PC + 4; Can yo figre ot the vales of the control signals? What is the advantage of pdating the PC now? Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-5

16 Step 2: Decode and Register Fetch registers rs and rt in case needed Compte the branch address in case the instrction is a branch RTL: A = Reg[IR[25-2]]; B = Reg[IR[2-6]]; ALUOt=PC+(sign-et(IR[5-])<<2); We aren't setting any control lines based on the instrction type yet (we are bsy "decoding" it in control logic) Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-6

17 Step 3: Eection ALU is performing one of three fnctions, based on instrction type: emory Reference: ALUOt = A + sign-etend(ir[5-]); R-type: ALUOt = A op B; Branch: if (A==B) PC = ALUOt; Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-7

18 Step 4: R-type or emory-access Loads and stores access memory DR = emory[aluot]; or emory[aluot] = B; R-type instrctions finish Reg[IR[5-]] = ALUOt; The write actally takes place at the end of the cycle on the edge Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-8

19 Step 5: Write-back Loads write to register Reg[IR[2-6]]= DR; What abot all the other instrctions? Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-9

20 Smmary of the Steps Step name fetch decode/register fetch Action for R-type instrctions Action for memory-reference Action for instrctions branches IR = emory[pc] PC = PC + 4 A = Reg [IR[25-2]] B = Reg [IR[2-6]] ALUOt = PC + (sign-etend (IR[5-]) << 2) Action for jmps Eection, address ALUOt = A op B ALUOt = A + sign-etend if (A ==B) then PC = PC [3-28] II comptation, branch/ (IR[5-]) PC = ALUOt (IR[25-]<<2) jmp completion emory access or R-type Reg [IR[5-]] = Load: DR = emory[aluot] completion ALUOt or Store: emory [ALUOt] = B emory read completion Load: Reg[IR[2-6]] = DR Fig. 5.3 Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-2

21 Cycle of add IR = emory[pc]; PC = PC + 4; IorD em emwrite IRWrite RegDst RegWrite ALUSrcA PC Address Write data emory emdata [25 2] [2 6] [5 ] register [5 ] emory data register [5 ] 6 register register 2 Registers Write register Write data Sign etend data data 2 32 Shift left 2 A B ALU control Zero ALU ALU reslt ALUOt [5 ] emtoreg ALUSrcB ALUOp

22 Cycle 2 of add A=Reg[IR[25-2]]; B=Reg[IR[2-6]]; ALUOt=PC+(sign-et(IR[5-])<<2); IorD em emwrite IRWrite RegDst RegWrite ALUSrcA PC Address Write data emory emdata [25 2] [2 6] [5 ] register [5 ] emory data register [5 ] 6 register register 2 Registers Write register Write data Sign etend data data 2 32 Shift left 2 A B ALU control Zero ALU ALU reslt ALUOt [5 ] emtoreg ALUSrcB ALUOp

23 Cycle 3 of add ALUOt = A op B; IorD em emwrite IRWrite RegDst RegWrite ALUSrcA PC Address Write data emory emdata [25 2] [2 6] [5 ] register [5 ] emory data register [5 ] 6 register register 2 Registers Write register Write data Sign etend data data 2 32 Shift left 2 A B ALU control Zero ALU ALU reslt ALUOt [5 ] emtoreg ALUSrcB ALUOp

24 Cycle 4 of add Reg[IR[5-]] = ALUOt; IorD em emwrite IRWrite RegDst RegWrite ALUSrcA PC Address Write data emory emdata [25 2] [2 6] [5 ] register [5 ] emory data register [5 ] 6 register register 2 Registers Write register Write data Sign etend data data 2 32 Shift left 2 A B ALU control Zero ALU ALU reslt ALUOt [5 ] emtoreg ALUSrcB ALUOp

25 Simple Qestion How many cycles will it take to eecte this code? lw $t2, ($t3) lw $t3, 4($t3) assme not beq $t2, $t3, Label add $t5, $t2, $t3 sw $t5, 8($t3) Label:... What is going on dring the 8th cycle of eection? In what cycle does the actal addition of $t2 and $t3 takes place? Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-25

26 Simple Qestion How many cycles will it take to eecte this code? lw $t2, ($t3) assme not lw $t3, 4($t3) beq $t2, $t3, Label add $t5, $t2, $t3 sw $t5, 8($t3) Label:... What is going on dring the 8th cycle of eection? In what cycle does the actal addition of $t2 and $t3 takes place? Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-26

27 Otline A mlticycle implementation lticycle datapath lticycle eection steps lticycle control (Appendi C.3) icroprogramming: simplifying control (Appendi C.4) Eceptions Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-27

28 Implementing the Control Vale of control signals is dependent pon: What instrction is being eected Which step is being performed Control mst specify both the signals to be set in any step and the net step in the seqence Control specification Use a finite state machine (graphically) Use microprogramming Implementation can be derived from the specification and se gates, RO, or PLA Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-28

29 Controller Design: An Overview Several possible initial representations, seqence control and logic representation, and control implementation => all may be determined indep. Initial Rep. Finite State Diagram icroprogram Seqencing Eplicit Net State icroprogram Control Fnction Conter + Dispatch ROs Logic Rep. Logic Eqations Trth Tables Implementation PLA RO hardwired control microprogrammed control 5B-29

30 Review: Finite State achines Finite state machines: a set of states and net state (set by crrent state and inpt) otpt (set by crrent state and possibly inpt) Crrent state Net-state fnction Net state Inpts Clock Otpt fnction Otpts We will se a oore achine (otpt based only on the crrent state) Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-3

31 Or Control odel State specifies control points for RT Transfer at eiting state (same falling edge) One state takes one cycle inpts (conditions) Net State Logic Control State State X Register Transfer Control Points Depends on Inpt Otpt Logic otpts (control points) 5B-3

32 Smmary of the Steps Step name fetch decode/register fetch Action for R-type instrctions Action for memory-reference Action for instrctions branches IR = emory[pc] PC = PC + 4 A = Reg [IR[25-2]] B = Reg [IR[2-6]] ALUOt = PC + (sign-etend (IR[5-]) << 2) Action for jmps Eection, address ALUOt = A op B ALUOt = A + sign-etend if (A ==B) then PC = PC [3-28] II comptation, branch/ (IR[5-]) PC = ALUOt (IR[25-]<<2) jmp completion emory access or R-type Reg [IR[5-]] = Load: DR = emory[aluot] completion ALUOt or Store: emory [ALUOt] = B emory read completion Load: Reg[IR[2-6]] = DR Fig. 5.3 Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-32

33 Control Specification for lticycle IR = E[PC] PC = PC + 4 A = R[rs] B = R[rt] S = PC+s(Imm6) fetch Decode/register fetch R-type lw/sw beq jmp S = A op B S = A + s(imm6) lw sw If zero PC = S PC = IR... Eecte R[rd] = S = E[S] E[S] = B emory access R[rt] = emory read Completion Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-33

34 Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-34

35 Organization of lticycle Processor PC Address Write data emory emdata [25 2] [2 6] [5 ] register [5 ] emory data register PCWriteCond PCWrite IorD Otpts em emwrite Control emtoreg IRWrite [5 ] Op [5 ] PCSorce ALUOp ALUSrcB ALUSrcA RegDst 6 RegWrite [25 ] 26 Shift 28 left 2 [3-26] PC [3-28] register register 2 Registers Write register Write data Sign etend data data 2 32 Shift left 2 A B ALU control Zero ALU ALU reslt Jmp address [3-] ALUOt 2 [5 ] Fig Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-35

36 Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-36

37 Control Signals Fig Single Bit Control ltiple Bit Control Signal name Effect when deasserted Effect when asserted ALUSrcA st ALU operand = PC st ALU operand = Reg[rs] RegWrite None Reg file is written emtoreg Reg. data inpt = ALU Reg. write data inpt = DR RegDst Reg. write dest. no. = rt Reg. write dest. no. = rd em None emory at address is read emwrite None emory at address is written IorD emory address = PC emory address = ALUot IRWrite None IR = emory PCWrite None PC = PCSorce PCWriteCond None If zero then PC = PCSorce Signal name Vale Effect ALUOp ALU adds ALU sbtracts ALU operates according to fnc code ALUSrcB 2nd ALU inpt = B 2nd ALU inpt = 4 2nd ALU inpt = sign etended IR[5-] 2nd ALU inpt = sign et., shift left 2 IR[5-] PCSorce PC = ALU (PC + 4) PC = ALUot (branch target address) PC = PC+4[3-28] : IR[25-] << 2 5B-37

38 apping RT to Control Signals fetch and decode portion of every instrction is identical: IR = E[PC] PC = PC + 4 Start (Op = 'LW') or (Op = 'SW') fetch em ALUSrcA = IorD = IRWrite ALUSrcB = ALUOp = PCWrite PCSorce = (Op = R-type) (Op = 'BEQ') decode/ Register fetch ALUSrcA = ALUSrcB = ALUOp = (Op = 'JP') Fig A = R[rs] B = R[rt] S = PC+ s(imm6) emory reference FS (Figre 5.38) R-type FS (Figre 5.39) Branch FS (Figre 5.4) Jmp FS (Figre 5.4) Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-38

39 apping RT to Control Signals FS for controlling memory reference instrctions: 2 From state ALUSrcA = ALUSrcB = ALUOp = (Op = 'LW') or (Op = 'SW') emory address comptation Fig (Op = 'LW') emory access (Op = 'SW') 5 emory access em IorD = emwrite IorD = 4 Write-back step RegWrite emtoreg = RegDst = To state (Figre 5.37) 5B-39

40 Complete FS Fig emory address com ptation ALUSrcA = ALUSrcB = ALUOp = Start ( O p = 'L W ') o r ( O p = 'S W ') 6 em ALUSrcA = Io rd = IR W rite ALUSrcB = ALUOp = PCWrite PCSorce = Eection ALUSrcA = ALUSrcB = ALUOp= In strc tion fe tc h 8 (O p = R -ty p e ) Branch com pletion ALUSrcA = ALUSrcB = ALUOp = PCWriteCond PCSorce = decode/ register fetch (Op = 'BE Q ') 9 ALUSrcA = ALUSrcB = ALUOp = (Op = 'J') Jmp completion PCWrite PCSorce = 3 (Op = 'LW') emory access (O p = 'S W ') 5 emory access 7 R -ty pe c om p le tio n em IorD = emwrite Io rd = RegDst = RegWrite emtoreg = 4 W rite-back step RegDst= RegWrite emtoreg= State nmber assignment 5B-4

41 From FS to Trth Table Please reference the logic eqations in Fig. C.3.3 and the trth table in Fig. C.3.6 Otpt Eqation PCWrite state + state9 PCWriteCond state8 IorD state3 + state5 NetState Otpt state4 + state5 + state7 Crrent + state8 states +state NetState PCWrite state NetState2 PCWriteCond state ((op = lw ) + (op = sw )) NetState3 IorD state2 (op = lw )... Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-4

42 inpt otpt Trth Table op S Datapath control NS Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-42

43 Designing FS Controller state op cond net state control points Trth Table zero 6 net state control points 4 state Control signals op datapath state 5B-43

44 The Control Unit Fig. C.3.2 Control logic Otpts PCW rite PCW ritecond Io rd em emwrite IR W rite emtoreg PCSorce ALUOp ALUSrcB ALUSrcA RegWrite RegDst Op5 Op4 Op3 Op2 Op register opcode field Inpts Op S3 S2 S S State register NS3 NS2 NS NS Seqence Control 5B-44

45 PLA Implementation Fig. C.3.9 Op5 Op4 Op3 Op2 Op Op S3 S2 S S Seqence Control PCWrite PCWriteCond IorD em emwrite IRW rite emtoreg PCSorce PCSorce ALUOp ALUOp ALUSrcB ALUSrcB ALUSrcA RegWrite RegDst NS3 NS2 NS NS 5B-45

46 RO Implementation? RO = " Only emory" vales of memory locations are fied ahead of time A RO can be sed to implement a trth table if the address is m-bits, we can address 2 m entries in the RO. or otpts are the bits of data that the address points to. m n m is the "height", and n is the "width"

47 RO Implementation (Trth Table) Address RO content op S Datapath control NS -bit 6-bit 4-bit RO is 2 2 = 2K bits Rather wastefl, since for lots of entries, otpts are same or don t-care Cold break p into two smaller ROs (Fig. C.3.7, C.3.8) Control table: Inpt: 4-bit state Otpt:6 controls Net state table: Inpt: 4-bit state and 6- bit op-code Otpt: 4-bit state 5B-47

48 RO vs PLA RO: se two smaller ROs (Fig. C.3.7, C.3.8) 4 state bits give the 6 otpts, bits of RO bits (op + state) give 4 net state bits, 2 4 bits of RO Total = 4.3K bits of RO (compared to 2 2 bits of single RO implementation) PLA is mch smaller can share prodct terms only need entries that prodce an active otpt can take into accont don't-cares Size is (#inpts #prodct-terms) + (#otpts #prodct-terms) For this eample = (7)+(27) = 46 PLA cells PLA cells sally abot the size of a RO cell (slightly bigger) Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-48

49 Otline A mlticycle implementation lticycle datapath lticycle eection steps lticycle control (Appendi C.3) icroprogramming: simplifying control (Appendi C.4) Eceptions Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-49

50 Controller Design: An Overview Several possible initial representations, seqence control and logic representation, and control implementation => all may be determined indep. Initial Rep. Finite State Diagram icroprogram Seqencing Eplicit Net State icroprogram Control Fnction Conter + Dispatch ROs Logic Rep. Logic Eqations Trth Tables Implementation PLA RO hardwired control microprogrammed control 5B-5

51 icroprogram Control is the hard part of processor design Datapath is fairly reglar and well-organized emory is highly reglar Control is irreglar and global Bt, the state diagrams that define the controller for an instrction set processor are highly strctred Use this strctre to constrct a simple microseqencer Control redces to programming this simple device => microprogramming micro-pc seqencer control microinstrction seqencer datapath control.. control signals Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-5

52 icroinstrction Control signals : Think of the set of control signals that mst be asserted in a state as an instrction Eecting a microinstrction has the effect of asserting the control signal specified by the microinstrction Seqencing What microinstrction shold be eected net? Eecte seqentially (net state nconditionally) Branch (net state also depends on inpts) A microprogram is a seqence of microinstrctions eecting a program flow chart (finite state machine) Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-52

53 Designing a icroinstrction Set ) Start with a list of control signals 2) Grop signals together that make sense (vs. random): called fields 3) Places fields in some logical order (e.g., ALU operation & ALU operands first and microinstrction seqencing last) 4) Create a symbolic legend for the microinstrction format, showing name of field vales and how they set control signals Use compters to design compters 5) To minimize the width, encode operations that will never be sed at the same time Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-53

54 icroinstrction Interpretation ain emory eection nit ADD SUB AND DATA... User program pls Data this can change! one of these is mapped into one of these CPU control memory AND microseqence e.g., Fetch Calc Operand Addr Fetch Operand(s) Calclate Save Answer(s) 5B-54

55 icroprogramming Using RO Ease of design Fleibility Each to adapt to changes in organization, timing, technology Can make changes late in design cycle, or even in the field Generality Implement mltiple inst. sets on same machine Can tailor instrction set to application Can implement very powerfl instrction sets (jst more control memory) Compatibility any organizations, same instrction set Costly to implement and Slow Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-55

56 Smmary of Control Control is specified by a finite state diagram Specialized state-diagrams easily captred by microseqencer simple increment and branch fields datapath control fields Control can also be specified by microprogramming Control is more complicated with: comple instrction sets restricted datapaths Simple instrction set and powerfl datapath => simple control cold redce hardware Or go for speed => many instrctions at once! Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-56

57 Otline A mlticycle implementation lticycle datapath lticycle eection steps lticycle control (Appendi C.3) icroprogramming: simplifying control (Appendi C.4) Eceptions Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-57

58 Eceptions User Program Eception System Eception Handler retrn from eception Normal control flow: seqential, jmps, branches, calls, retrns Eception = nprogrammed control transfer system takes action to handle the eception mst record address of the offending instrction shold know case and transfer to proper handler if retrns to ser, mst save & restore ser state Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-58

59 User/System odes By providing two modes of eection (ser/system), compter may manage itself OS is a special program that rns in the privileged system mode and has access to all of the resorces of the compter Presents virtal resorces to each ser that are more convenient than the physical resorces files vs. disk sectors virtal memory vs. physical memory protects each ser program from others Eceptions allow the system to take action in response to events that occr while ser program is eecting OS begins at the handler Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-59

60 Two Types of Eceptions Interrpts: cased by eternal events and asynchronos to eection => may be handled between instrctions simply sspend and resme ser program Eceptions: cased by internal events and synchronos to eection, e.g., eceptional conditions (overflow), errors (parity), falts instrction may be retried or simlated and program contined or program may be aborted Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-6

61 IPS Convention of Eceptions IPS convention: eception means any nepected change in control flow, withot distingishing internal or eternal se interrpt only when the event is eternally cased Type of event From where? IPS terminology I/O device reqest Eternal Interrpt Invoke OS from ser program Internal Eception Hardware malfnctions Either Eception/Interrpt Arithmetic overflow Internal Eception Using an ndefined inst. Internal Eception Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-6

62 Precise Interrpts Precise: machine state is preserved as if program eected pto the offending inst. Same system code will work on different implementations of the architectre Position clearly established by IB, and taken by IPS Difficlt in the presence of pipelining, ot-ot-order eection,... Imprecise: system software has to figre ot what is where and pt it all back together Performance goals often lead designers to forsake precise interrpts system software developers, ser, markets etc., sally wish they had not done this Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-62

63 Handling Eceptions in or design Consider two types of eceptions: ndefined instrction & arithmetic overflow Basic actions on eception: Save state: save the address of the offending instrction in the eception program conter (EPC) Transfer control to OS at some specified address => need to know the case for the eception => then know the address of eception handler After service, OS can terminate the program or contine its eection, sing EPC to retrn Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-63

64 Saving States: General Approaches Psh it onto the stack Va, 68k, 886 Save it in special registers IPS EPC, BadVaddr, Stats, Case Shadow Registers 88k Save state in a shadow of the internal pipeline registers Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-64

65 Addressing the Eception Handler Traditional approach: interrpt vector The case of eception is a vector giving the address of the handler PC <- E[ IV_base + case ] 68, Va, 886,... iv_base case handler code RISC Handler Table PC <- IV_base + case Saves state and jmps Sparc, PA, 88K,... IPS approach: fied entry se a stats register (case register) to hold a field to indicate the case PC <- EXC_addr iv_base handler entry code case 5B-65

66 Datapath with Eception Handling Fig PC Address emory emdata Write data [25 2] [2 6] [5 ] register [5 ] emory data register PCWriteCond PCWrite IorD em emwrite emtoreg IRWrite [5 ] Otpts Control Op [5 ] [25 ] 26 Shift 28 left 2 [3-26] PC [3-28] 6 CaseWrite IntCase EPCWrite PCSorce ALUOp ALUSrcB ALUSrcA RegWrite RegDst register register 2 Registers Write register Write data Sign etend data data 2 32 Shift left 2 A B ALU control Zero ALU ALU reslt Jmp address [3-] CO 3 ALUOt 2 EPC Case [5 ] Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-66

67 Remarks EPC: reg. to hold address of affected inst. Case: reg. to record case of eception Assme LSB encodes the two possible eception sorces: ndefined instrction= and arithmetic overflow= Two control signals to write EPC (EPCWrite) and Case (CaseWrite), and one control signal (IntCase) to set LSB of Case register Be able to write eception address into PC, assming at C he => needs a 4-way UX to PC ay ndo PC = PC + 4 (PC = PC - 4), since want EPC to point to offending inst. (not its sccessor) Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-67

68 Eception Detection Undefined instrction: detected when no net state is defined from state for the op vale Handle this by defining the net state vale for all op vales other than lw, sw, (R-type), jmp, and beq as a new state, other Arithmetic overflow: detected with the Overflow signal ot of the ALU This signal is sed in the modified FS to specify an additional possible net state Note: challenge in designing control of a real machine is to handle different interactions between instrctions and other eception-casing events sch that control logic remains small and fast Comple interactions makes the control nit the most challenging aspect of hardware design Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-68

69 FS with Eception Handling Fig. 5.4 emory address comptation 2 ALUSrcA = ALUSrcB = ALUOp = Start (Op = 'LW') or (Op = 'SW') fetch em ALUSrcA = IorD = IRWrite ALUSrcB = ALUOp = PCWrite PCSorce = 6 Eection ALUSrcA = ALUSrcB = ALUOp = (Op = R-type) Branch completion 8 ALUSrcA = ALUSrcB = ALUOp = PCWriteCond PCSorce = decode/ Register fetch (Op = 'BEQ') 9 ALUSrcA = ALUSrcB = ALUOp = (Op = 'J') Jmp completion PCWrite PCSorce = (Op = other) 3 (Op = 'LW') em IorD = emory access 5 (Op = 'SW') emwrite IorD = emory access 7 R-type completion IntCase = CaseWrite RegDst = RegWrite emtoreg = Overflow ALUSrcA = ALUSrcB = ALUOp = EPCWrite PCWrite PCSorce = IntCase = CaseWrite ALUSrcA = ALUSrcB = ALUOp = EPCWrite PCWrite PCSorce = 4 Write-back step Overflow RegWrite emtoreg = RegDst = 5B-69

70 Smmary Specialize state diagrams easily captred by microseqencer simple increment and branch fields datapath control fields Control design redces to microprogramming Eceptions are the hard part of control Need to find convenient place to detect eceptions and to branch to state or microinstrction that saves PC and invokes OS Harder with pipelined CPUs that spport page falts on memory accesses, i.e., the instrction cannot complete AND yo mst restart program at eactly the instrction with the eception Lectre5B - mlticycle implementation (cwli@twins.ee.nct.ed.tw) 5B-7