Lab 8 (All Sections) Prelab: ALU and ALU Control

Transcription

1 Lab 8 (All Sections) Prelab: and Control Name: Sign the following statement: On my honor, as an Aggie, I have neither given nor received nathorized aid on this academic work Objective In this lab yo will be implementing the modle and its control block. For this lab yo are expected to be familiar with the design (see Chapter C.5 of the textbook). In addition, yo shold have a thorogh nderstanding of the IPS instrction set. 2 Introdction In this lab, yo will design the 32-bit Arithmetic Logic Unit () as described in Chapter C.5 of the textbook. Yor will become an important part of the IPS microprocessor that yo will bild in later labs, so it is advised to do this lab careflly.

2 Compter Architectre and Design, PreLab and CONTROL Blocks As yo know, the is the most crcial element in any processor data-path. Almost every instrction ses for some processing. For example, ADD and ADDI se the for addition, SUB for sbtraction, and I for logical, etc. 4 Ctrl BsA Zero BsW BsB Fig. : Block As shown in Figre, an modle takes two 32-bit inpts (BsA and BsB), performs an operation as specified by the 4-bit Ctrl field, and otpts the reslt on the 32 bit otpt bs BsW. When the vale on BsW is, the Zero signal is set to, otherwise it is set to. The basic operations performed by an are:. Addition 2. Sbtraction AND 5. Set on less than (compare and set) In this lab, we will be extending the to implement 2 additional operations:. Shift left 2. Shift right The shift left operation takes two vales, A and B, each of which is 32-bits. A is shifted left B bits (A << B), and written to W. Shift right works in an similar manner bt shifts to the right instead of the left.

3 Compter Architectre and Design, PreLab Qestions Assming yor can perform basic operations, as well as the 2 additional operations yo will add.. What is the operation that yor performs with the following instrctions? Instrction LW (Load Word) SW (Store Word) BEQ (Branch of Eqal) SLT (Set on Less Than) SLL SRL Action 2. Control The control block takes 2 inpts The fnction field from an R-TYPE instrction (bits [5:] of the instrction). OP(2 bits) from the main control nit The otpt of the control nit is a 4-bit signal, which directly controls the. Give the Ctrl vales for the following operations: Note: For Shift operations (shift left and shift right), yo may sed any nassigned vale. For the prposes of this lab, se for shift right, and for shift left. Operation Addition AND Sbtract Set on Less Than N SRL SLL Control lines

4 Compter Architectre and Design, PreLab How wold yo extend the datapath in Figre 2 to implement the SLL and SRL instrctions. Note: The needs the first port to contain the vale to shift and the second to contain the amont to shift by. Pay special attention to the data path for these vales. PCSrc 4 Add RegWrite Shift left 2 Add reslt x PC address Instrction [25:2] register Instrction [2:6] data Src register 2 Zero Instrction [3:] Write data 2 reslt Instrction Instrction [5:] x register memory x Write data Registers RegDst Instrction [5:] 6 Sign 32 extend control emwrite Address Write data Data memory em data emtoreg x Instrction [5:] Op Fig. 2: Datapath PAT5F5.eps

5 Compter Architectre and Design, PreLab The OP takes 3 vales: Implicit Add (Used by load and store and addi). Implicit Sbtract (sed by beq). Use Fnction Field (sed by R-Type instrctions). Implicit (Used by ori) Complete the following table for mapping the OP and FUNCT fields to CTRL signals. Instrction OP Fnct Field operation Control (2 bits) Instrct[5:] (4 bits) LW XXXXXX SW XXXXXX BEQ XXXXXX ADD addition SUB sbtraction AND AND I SLT SLL SRL Note: Yo will se the above mapping to implement the control block dring inlab.

6 Compter Architectre and Design, PreLab 8 6 Test # Test Ctrl A B W Zero (4 bits) (32 bits) (32 bits) (32 bits) ADD, 2 x x x 2 ADD, 2 x xffffffff xffffffff 3 ADD, 2 xffffffff x x 4 ADD F F, 2 xff 5 SUB, 6 x x x 6 SUB, 7 SUB, 8 SLT, 7 x x x 9 SLT, x SLT, x SLT, 2 SLT, xffffffff 3 AND xffffffff, xffffffff xffffffff 4 AND xffffffff, xffffffff xcafebabe xcafebabe xcafebabe 5 AND x, xffffffff 6 AND x , x x xffff, xffff xffff xffff 8 x , x SLL x ,x2 x x2 2 SLL x8,x3 x8 2 SRL x,x3 x x3 22 SRL x234,x6 x234 x6 Tab. : Test Vectors 5. Dring the in-lab, yo will be implementing the block. As part of the design process, yo need to develop an appropriate set of test vectors to verify basic fnctionality. Complete Table (sbmit hardcopy or via ) to verify that all 7 operations work as designed. Note that all vales are expressed in hexadecimal. Yo will se this table to test the Verilog code that yo will implement dring the in-lab (make sre to keep a copy of yor sbmitted answers).