MIPS Architecture. An Example: MIPS. From the Harris/Weste book Based on the MIPS-like processor from the Hennessy/Patterson book

Transcription

1 An Eample: IPS From the Harris/Weste book Based on the IPS-like processor from the Hennessy/Patterson book IPS Architectre w Eample: sbset of IPS processor architectre n Drawn from Patterson & Hennessy w IPS is a 32-bit architectre with 32 s n Consider 8-bit sbset sing 8-bit path n Only implement 8 s ($ - $7) n $ hardwired to n 8-bit program conter Ø

2 Set Set What s missing from this instrction set? Ø 2

3 Set What s missing from this instrction set? Lots of things! One in particlar: Spport for sbrotine calls (JAL, STPC, etc.) Encoding w 32-bit instrction encoding (still 8-bit ) n Reqires for cycles to fetch on 8-bit path format eample encoding R add $rd, $ra, $rb ra rb rd fnct 5 5 I beq $ra, $rb, imm op ra rb imm 2 J j dest op dest Ø 3

4 Fibonacci (C) f = ; f - = - f n = f n- + f n-2 f =,,, 2, 3, 5, 8, 3, Fibonacci (Assembly) w st statement: int n = 8; w How do we translate this to assembly? n Decide which shold hold its vale n Load an immediate vale into that n Bt, there s no load immediate instrction n Bt, there is an addi instrction, and there s a convenient that s always pinned to w addi $3, $, 8 ; load +8 into 3 Ø 4

5 Fibonacci (Assembly) Fibonacci (Binary) w st statement: addi $3, $, 8 w How do we translate this to machine langage? n Hint: se instrction encodings below format eample encoding R add $rd, $ra, $rb ra rb rd fnct 5 5 I beq $ra, $rb, imm op ra rb imm 2 J j dest op dest Ø 5

6 Fibonacci (Binary) w achine langage program Fibonacci (Binary) format eample encoding R add $rd, $ra, $rb ra rb rd fnct 5 5 I beq $ra, $rb, imm op ra rb imm 2 J j dest op dest Ø

7 IPS icroarchitectre w lticycle microarchitectre from Patterson & Hennessy PCEn PCCond PC IorD em em emtoreg Otpts Control PCSorce ALUOp ALUSrcB ALUSrcA Reg PC Address emory emdata [3:2] [25 : 2] [2 : ] [5 : ] [7: ] emory IR[3:] [5: ] Op [5 : ] RegDst [5 : ] 8 Shift 2 Registers 2 A B 2 3 ALU control left 2 Zero ALU ALU reslt ALUControl Jmp address ALUOt 2 [5 : ] lticycle Controller fetch em ALUSrcA = IorD = IR3 ALUSrcB = ALUOp = PC PCSorce = em ALUSrcA = IorD = IR2 ALUSrcB = ALUOp = PC PCSorce = 2 em ALUSrcA = IorD = IR ALUSrcB = ALUOp = PC PCSorce = 3 em ALUSrcA = IorD = IR ALUSrcB = ALUOp = PC PCSorce = decode/ fetch 4 ALUSrcA = ALUSrcB = ALUOp = Reset emory address comptation 5 ALUSrcA = ALUSrcB = ALUOp = (Op = 'L B ') or (Op = 'S B ') Eection 9 ALUSrcA = ALUSrcB = ALUOp= (Op = R-type) Branch completion ALUSrcA = ALUSrcB = ALUOp = PCCond PCSorce = (Op = 'BEQ') (Op = 'J') Jmp completion 2 PC PCSorce = (Op = 'L B') (Op = 'S B') emory access 8 emory access R-type completion em IorD = em IorD = RegDst = Reg emtoreg = 7 -back step RegDst = Reg emtoreg = Ø 7

8 Logic Design w Start at top level n Hierarchically decompose IPS into nits w Top-level interface crystal oscillator Clk reset memread memwrite IPS processor adr write mem eternal memory Verilog Code // top level design incldes both mips processor and memory modle mips_mem #(parameter WIDTH = 8, REGBITS = 3)(clk, reset); inpt clk, reset; wire memread, memwrite; wire [WIDTH-:] adr, write; wire [WIDTH-:] mem; crystal oscillator Clk reset memread memwrite IPS processor adr write mem eternal memory // instantiate the mips processor mips #(WIDTH,REGBITS) mips(clk, reset, mem, memread, memwrite, adr, write); // instantiate memory for code and emem #(WIDTH) emem(clk, memwrite, adr, write, mem); Ø 8

9 PC PCEn Address emory emdata [3:2] [25 : 2] [2 : ] [5 : ] [7: ] emory PCCond PC IorD em em emtoreg IR[3:] [5: ] Otpts Control Op [5 : ] PCSorce ALUOp ALUSrcB ALUSrcA Reg RegDst [5 : ] 8 Shift 2 Registers [5 : ] 2 A B 2 3 ALU control left 2 Zero ALU ALU reslt ALUControl Jmp address ALUOt 2 Block Diagram memwrite memread controller alop[:] alcontrol ph op[5:] zero alsrca alsrcb[:] pcen pcsorce[:] memtoreg regdst iord regwrite irwrite[3:] fnct[5:] alcontrol[2:] ph2 reset adr[7:] path write[7:] mem[7:] // simplified IPS processor modle mips #(parameter WIDTH = 8, REGBITS = 3) (inpt clk, reset, inpt [WIDTH-:] mem, otpt memread, memwrite, otpt [WIDTH-:] adr, write); memwrite memread Top-level code controller alop[:] alcontrol wire [3:] instr; wire zero, alsrca, memtoreg, iord, pcen; wire regwrite, regdst; wire [:] alop,pcsorce,alsrcb; wire [3:] irwrite; wire [2:] alcont; ph ph2 reset adr[7:] write[7:] mem[7:] op[5:] zero alsrca alsrcb[:] pcen pcsorce[:] memtoreg regdst iord regwrite irwrite[3:] path fnct[5:] alcontrol[2:] controller cont(clk, reset, instr[3:2], zero, memread, memwrite, alsrca, memtoreg, iord, pcen, regwrite, regdst, pcsorce, alsrcb, alop, irwrite); alcontrol ac(alop, instr[5:], alcont); path #(WIDTH, REGBITS) dp(clk, reset, mem, alsrca, memtoreg, iord, pcen, regwrite, regdst, pcsorce, alsrcb, irwrite, alcont, zero, instr, adr, write); Ø 9

10 modle controller(inpt clk, reset, inpt [5:] op, inpt zero, otpt reg memread, memwrite, alsrca, memtoreg, iord, otpt pcen, otpt reg regwrite, regdst, otpt reg [:] pcsorce, alsrcb, alop, otpt reg [3:] irwrite); Controller (FS) fetch parameter FETCH = 4'b; parameter FETCH2 = 4'b; parameter FETCH3 = 4'b; parameter FETCH4 = 4'b; parameter DECODE = 4'b; parameter EADR = 4'b; parameter LBRD = 4'b; Reset parameter LBWR = 4'b; parameter SBWR = 4'b; parameter RTYPEEX = 4'b; parameter RTYPEWR = 4'b; parameter BEQEX = 4'b; parameter JEX = 4'b; parameter ADDIWR = 4'b; // added for ADDI parameter LB = 'b; parameter SB = 'b; parameter RTYPE = 'b; parameter BEQ = 'b; parameter J = 'b; parameter ADDI = 'b; /// added for ADDI reg [3:] state, netstate; reg pcwrite, pcwritecond; em ALUSrcA = IorD = IR3 ALUSrcB = ALUOp = PC PCSorce = em ALUSrcA = IorD = IR2 ALUSrcB = ALUOp = PC PCSorce = emory address comptation 5 ALUSrcA = ALUSrcB = ALUOp = (Op = 'L B') emory access em IorD = (Op = 'S B') -back step 7 RegDst = Reg emtoreg = 2 3 em em decode/ ALUSrcA = ALUSrcA = fetch IorD = IorD = 4 IR IR ALUSrcB = ALUSrcB = ALUSrcA = ALUOp = ALUOp = ALUSrcB = PC PC ALUOp = PCSorce = PCSorce = (Op = 'L B ') or (Op = 'S B ') Eection 9 ALUSrcA = ALUSrcB = ALUOp= emory access R-type completion 8 RegDst = em Reg IorD = emtoreg = (Op = R-type) Branch completion ALUSrcA = ALUSrcB = ALUOp = PCCond PCSorce = (Op = 'BEQ') (Op = 'J') Jmp completion 2 PC PCSorce = modle controller(inpt clk, reset, inpt [5:] op, inpt zero, otpt reg memread, memwrite, alsrca, memtoreg, iord, otpt pcen, otpt reg regwrite, regdst, otpt reg [:] pcsorce, alsrcb, alop, otpt reg [3:] irwrite); parameter FETCH = 4'b; parameter FETCH2 = 4'b; parameter FETCH3 = 4'b; parameter FETCH4 = 4'b; parameter DECODE = 4'b; parameter EADR = 4'b; parameter LBRD = 4'b; parameter LBWR = 4'b; parameter SBWR = 4'b; parameter RTYPEEX = 4'b; parameter RTYPEWR = 4'b; parameter BEQEX = 4'b; parameter JEX = 4'b; parameter ADDIWR = 4'b; // added for ADDI parameter LB = 'b; parameter SB = 'b; parameter RTYPE = 'b; parameter BEQ = 'b; parameter J = 'b; parameter ADDI = 'b; /// added for ADDI reg [3:] state, netstate; reg pcwrite, pcwritecond; State Encodings... Opcodes... Local reg variables... Controller Parameters Ø

11 ain state machine NS logic // state clk) if(reset) state <= FETCH; else state <= netstate; // net state logic (combinational) case(state) FETCH: netstate <= FETCH2; FETCH2: netstate <= FETCH3; FETCH3: netstate <= FETCH4; FETCH4: netstate <= DECODE; DECODE: case(op) LB: netstate <= EADR; SB: netstate <= EADR; ADDI: netstate <= EADR; RTYPE: netstate <= RTYPEEX; BEQ: netstate <= BEQEX; J: netstate <= JEX; // shold never happen defalt: netstate <= FETCH; case EADR: case(op) LB: netstate <= LBRD; SB: netstate <= SBWR; ADDI: netstate <= ADDIWR; // shold never happen defalt: netstate <= FETCH; case LBRD: netstate <= LBWR; LBWR: netstate <= FETCH; SBWR: netstate <= FETCH; RTYPEEX: netstate <= RTYPEWR; RTYPEWR: netstate <= FETCH; BEQEX: netstate <= FETCH; JEX: netstate <= FETCH; ADDIWR: netstate <= FETCH; // shold never happen defalt: netstate <= FETCH; case Setting Control Signal Otpts // set all otpts to zero, then // conditionally assert jst the // appropriate ones irwrite <= 4'b; pcwrite <= ; pcwritecond <= ; regwrite <= ; regdst <= ; memread <= ; memwrite <= ; alsrca <= ; alsrcb <= 2'b; alop <= 2'b; pcsorce <= 2'b; iord <= ; memtoreg <= ; case(state) FETCH: memread <= ; irwrite <= 4'b; alsrcb <= 2'b; pcwrite <= ; FETCH2: memread <= ; irwrite <= 4'b; alsrcb <= 2'b; pcwrite <= ; FETCH3: memread <= ; irwrite <= 4'b; alsrcb <= 2'b; pcwrite <= ; FETCH4: memread <= ; irwrite <= 4'b; alsrcb <= 2'b; pcwrite <= ; DECODE: alsrcb <= 2'b;... case Ø

12 IPS icroarchitectre - Datapath PC PCEn Address emory emdata [3:2] [25 : 2] [2 : ] [5 : ] [7: ] PCCond PC IorD em em emtoreg IR[3:] [5: ] Otpts Control Op [5 : ] PCSorce ALUOp ALUSrcB ALUSrcA Reg RegDst [5 : ] 8 Shift 2 Registers 2 A B 2 3 left 2 Zero ALU ALU reslt Jmp address ALUOt 2 emory ALU control ALUControl [5 : ] modle path #(parameter WIDTH = 8, REGBITS = 3) (inpt clk, reset, inpt [WIDTH-:] mem, inpt alsrca, memtoreg, iord, pcen, regwrite, regdst, inpt [:] pcsorce, alsrcb, // m select bits inpt [3:] irwrite, // InstReg write flags inpt [2:] alcont, // ALU control bits otpt zero, // ALU otpt is zero flag otpt [3:] instr, // 32-bit instrction otpt [WIDTH-:] adr, write); // 8-bit address and write- s // the size of the parameters mst be changed to match the WIDTH parameter localparam CONST_ZERO = 8'b; localparam CONST_ONE = 8'b; wire [REGBITS-:] ra, ra2, wa; // address bits wire [WIDTH-:] pc, netpc, md, rd, rd2, wd, a, src, src2, alreslt, alot, const4; // shift left constant field by 2 assign const4 = {instr[width-3:],2'b}; Verilog: Datapath // file address fields assign ra = instr[regbits+2:2]; assign ra2 = instr[regbits+5:]; m2 #(REGBITS) regm(instr[regbits+5:], instr[regbits+:], regdst, wa); Ø 2

13 // indepent of bit width, load instrction into for 8-bit s over for cycles flopen #(8) ir(clk, irwrite[], mem[7:], instr[7:]); flopen #(8) ir(clk, irwrite[], mem[7:], instr[5:8]); flopen #(8) ir2(clk, irwrite[2], mem[7:], instr[23:]); flopen #(8) ir3(clk, irwrite[3], mem[7:], instr[3:24]); // path flopenr #(WIDTH) pcreg(clk, reset, pcen, netpc, pc); flop #(WIDTH) wrd(clk, rd2, write); flop flop #(WIDTH) mdr(clk, mem, md); #(WIDTH) res(clk, alreslt, alot); flop #(WIDTH) areg(clk, rd, a); Verilog: Datapath 2 m2 #(WIDTH) adrm(pc, alot, iord, adr); m2 #(WIDTH) srcm(pc, a, alsrca, src); m4 #(WIDTH) src2m(write, CONST_ONE, instr[width-:], const4, alsrcb, src2); m4 #(WIDTH) pcm(alreslt, alot, const4, CONST_ZERO, pcsorce, netpc); m2 #(WIDTH) wdm(alot, md, memtoreg, wd); regfile #(WIDTH,REGBITS) rf(clk, regwrite, ra, ra2, wa, wd, rd, rd2); al #(WIDTH) alnit(src, src2, alcont, alreslt); zerodetect #(WIDTH) zd(alreslt, zero); IPS icroarchitectre - ALU PC PCEn Address emory emdata [3:2] [25 : 2] [2 : ] [5 : ] [7: ] PCCond PC IorD em em emtoreg IR[3:] [5: ] Otpts Control Op [5 : ] PCSorce ALUOp ALUSrcB ALUSrcA Reg RegDst [5 : ] 8 Shift 2 Registers 2 A B 2 3 left 2 Zero ALU ALU reslt Jmp address ALUOt 2 emory ALU control ALUControl [5 : ] Ø 3

14 modle al #(parameter WIDTH = 8) (inpt [WIDTH-:] a, b, inpt [2:] alcont, otpt reg [WIDTH-:] reslt); wire [WIDTH-:] b2, sm, slt; Verilog: al assign b2 = alcont[2]? ~b:b; // pre-compte B-inv for sbtraction assign sm = a + b2 + alcont[2]; // A + B or A + Binv + (i.e. sbtraction) // slt shold be if most significant bit of sm is assign slt = sm[width-]; always@(*) case(alcont[:]) 2'b: reslt <= a & b; 2'b: reslt <= a b; 2'b: reslt <= sm; 2'b: reslt <= slt; case // compte ALU reslt (based on alcont bits) IPS icroarchitectre - ALUctl PC PCEn Address emory emdata [3:2] [25 : 2] [2 : ] [5 : ] [7: ] PCCond PC IorD em em emtoreg IR[3:] [5: ] Otpts Control Op [5 : ] PCSorce ALUOp ALUSrcB ALUSrcA Reg RegDst [5 : ] 8 Shift 2 Registers 2 A B 2 3 left 2 Zero ALU ALU reslt Jmp address ALUOt 2 emory ALU control ALUControl [5 : ] Ø 4

15 Verilog: alcontrol modle alcontrol(inpt [:] alop, inpt [5:] fnct, otpt reg [2:] alcont); case(alop) 2'b: alcont <= 3'b; // add for lb/sb/addi 2'b: alcont <= 3'b; // sb (for beq) defalt: case(fnct) // R-Type instrctions 'b: alcont <= 3'b; // add (for add) 'b: alcont <= 3'b; // sbtract (for sb) 'b: alcont <= 3'b; // logical and (for and) 'b: alcont <= 3'b; // logical or (for or) 'b: alcont <= 3'b; // set on less (for slt) defalt: alcont <= 3'b; // shold never happen case case IPS icroarchitectre - Regfile PC PCEn Address emory emdata [3:2] [25 : 2] [2 : ] [5 : ] [7: ] PCCond PC IorD em em emtoreg IR[3:] [5: ] Otpts Control Op [5 : ] PCSorce ALUOp ALUSrcB ALUSrcA Reg RegDst [5 : ] 8 Shift 2 Registers 2 A B 2 3 left 2 Zero ALU ALU reslt Jmp address ALUOt 2 emory ALU control ALUControl [5 : ] Ø 5

16 Verilog: regfile modle regfile #(parameter WIDTH = 8, REGBITS = 3) (inpt clk, inpt regwrite, inpt [REGBITS-:] ra, ra2, wa, inpt [WIDTH-:] wd, otpt [WIDTH-:] rd, rd2); reg [WIDTH-:] RA [(<<REGBITS)-:]; // three ported file // read two ports (combinational) // write third port on rising edge of clock clk) if (regwrite) RA[wa] <= wd; assign rd = ra? RA[ra] : ; // is hardwired to assign rd2 = ra2? RA[ra2] : ; // is hardwired to Verilog: Spport Strctres modle zerodetect #(parameter WIDTH = 8) (inpt [WIDTH-:] a, otpt y); assign y = (a==); modle flop #(parameter WIDTH = 8) (inpt clk, inpt [WIDTH-:] d, otpt reg [WIDTH-:] q); clk) q <= d; modle flopen #(parameter WIDTH = 8) (inpt clk, en, inpt [WIDTH-:] d, otpt reg [WIDTH-:] q); clk) if (en) q <= d; modle flopenr #(parameter WIDTH = 8) (inpt clk, reset, en, inpt [WIDTH-:] d, otpt reg [WIDTH-:] q); clk) if (reset) q <= ; else if (en) q <= d; modle m2 #(parameter WIDTH = 8) (inpt [WIDTH-:] d, d, inpt s, otpt [WIDTH-:] y); assign y = s? d : d; modle m4 #(parameter WIDTH = 8) (inpt [WIDTH-:] d, d, d2, d3, inpt [:] s, otpt reg [WIDTH-:] y); case(s) 2'b: y <= d; 2'b: y <= d; 2'b: y <= d2; 2'b: y <= d3; case Ø

17 Logic Design w Start at top level n Hierarchically decompose IPS into nits w Top-level interface crystal oscillator Clk reset memread memwrite IPS processor adr write mem eternal memory Verilog: ememory simlation // eternal memory accessed by IPS modle ememory #(parameter WIDTH = 8) (clk, memwrite, adr, write, mem); inpt clk; inpt memwrite; inpt [WIDTH-:] adr, write; otpt reg [WIDTH-:] mem; reg [3:] RA [(<<WIDTH-2)-:]; wire [3:] word; initial $readmemh("memfile.dat",ra); // read and write bytes from 32-bit word clk) if(memwrite) case (adr[:]) 2'b: RA[adr>>2][7:] <= write; 2'b: RA[adr>>2][5:8] <= write; 2'b: RA[adr>>2][23:] <= write; 2'b: RA[adr>>2][3:24] <= write; case assign word = RA[adr>>2]; case (adr[:]) 2'b: mem <= word[7:]; 2'b: mem <= word[5:8]; 2'b: mem <= word[23:]; 2'b: mem <= word[3:24]; case Ø 7

18 Synthesized memory? w If yo synthesize the Verilog, yo ll get a memory n Bt it will be hge! n It will be made of yor DFF cells n pls synthesized address decoders n Cstom memory is mch smaller n bt mch trickier to get right n see details in VGA slides Verilog: ememory // eternal memory accessed by IPS modle emem #(parameter WIDTH = 8) (clk, memwrite, adr, write, mem); inpt inpt inpt otpt clk; memwrite; [WIDTH-:] adr, write; [WIDTH-:] mem; wire memwriteb, clkb; // UC RA has active low write enable... not(memwriteb, memwrite); // Looks like yo need to clock the memory early // to make it work with the crrent control... not(clkb, clk); // Instantiate the UC SPRA modle UC3SPRA_8_8 mips_ram (.CK(clkB),.CEN('b),.WEN(memwriteB),.OEN('b),.ADR(adr),.DI(write),.DOUT(mem)); Ø 8

19 IPS (8-bit) size comparison One big EDI rn of the whole thing With some work, cold probably get this in a single TCU... IPS (8-bit) size comparison Separate EDI for controller, alcontrol, path and cstom RF, assembled with ccar Ø 9

20 IPS (8-bit) whole chip Incldes poly/m/m2/m3 fill, and logos Roted to the pads sing ccar System Verilog w Enhanced version of classic Verilog n ore types l typedef, strct, nion, enm n Some OO featres n Adds better spport for verification w Backward compatible with Verilog Ø 2

21 New type: logic w logic as a type is like a reg n Bt can be sed everywhere, not jst in seqential blocks (always, initial) n It mst have a single driver only one gate driving the vale (like a logic vale!) n If yo have more than one driver (think tri-state), then it mst be a wire logic [7:] my_var; // 8-bit logic type variable mips modle definition // simplified IPS processor modle mips #(parameter WIDTH = 8, REGBITS = 3) (inpt logic clk, reset, inpt logic [WIDTH-:] mem, otpt logic memread, memwrite, otpt logic [WIDTH-:] adr, write); logic [3:] instr; logic zero, alsrca, memtoreg, iord, pcen, regwrite, regdst; logic [:] pcsrc, alsrcb; logic [3:] irwrite; logic [2:] alcontrol; logic [5:] op, fnct; assign op = instr[3:2]; assign fnct = instr[5:]; controller cont(clk, reset, op, fnct, zero, memread, memwrite, alsrca, memtoreg, iord, pcen, regwrite, regdst, pcsrc, alsrcb, alcontrol, irwrite); path #(WIDTH, REGBITS) dp(clk, reset, mem, alsrca, memtoreg, iord, pcen, regwrite, regdst, pcsrc, alsrcb, irwrite, alcontrol, zero, instr, adr, write); Ø 2

22 C-type Data Strctring w Enmerated types allow nmeric qantities to be assigned meaningfl names n Like parameters in Verilog typedef enm logic [2:] { RED, GREEN, BLUE, CYAN, AGENTA, YELLOW } color_t; color_t my_color = GREEN; initial $display("the color is %s, my_color.name()); // note the se of the name() bilt-in fnction C-type Data Strctring w Strcts are like C strcts typedef strct { byte a; reg b; shortint nsigned c; } mystrct; modle strct_ (); // Define a local strct. strct { byte a; reg b; shortint nsigned c; } mylocalstrct = '{,,}; Disclaimer I don t know mch abot how these interact with synthesis // When defined typedef, we can be sed as new type mystrct object = '{,,}; initial $display ("a = %b b = %b c = %h", object.a, object.b, object.c); $display ("a = %b b = %b c = %h", mylocalstrct.a, mylocalstrct.b, mylocalstrct.c); # $finish; Ø 22

23 modle controller(inpt clk, reset, inpt [5:] op, inpt zero, otpt reg memread, memwrite, alsrca, memtoreg, iord, otpt pcen, otpt reg regwrite, regdst, otpt reg [:] pcsorce, alsrcb, alop, otpt reg [3:] irwrite); parameter FETCH = 4'b; parameter FETCH2 = 4'b; parameter FETCH3 = 4'b; parameter FETCH4 = 4'b; parameter DECODE = 4'b; parameter EADR = 4'b; parameter LBRD = 4'b; parameter LBWR = 4'b; parameter SBWR = 4'b; parameter RTYPEEX = 4'b; parameter RTYPEWR = 4'b; parameter BEQEX = 4'b; parameter JEX = 4'b; parameter ADDIWR = 4'b; // added for ADDI parameter LB = 'b; parameter SB = 'b; parameter RTYPE = 'b; parameter BEQ = 'b; parameter J = 'b; parameter ADDI = 'b; /// added for ADDI reg [3:] state, netstate; reg pcwrite, pcwritecond; State Encodings... Opcodes... Local reg variables... Controller Parameters: Verilog System Verilog Version // states and instrctions typedef enm logic [3:] {FETCH = 4'b, FETCH2, FETCH3, FETCH4, DECODE, EADR, LBRD, LBWR, SBWR, RTYPEEX, RTYPEWR, BEQEX, JEX} statetype; typedef enm logic [5:] {LB = 'b, SB = 'b, RTYPE = 'b, BEQ = 'b, J = 'b} opcode; typedef enm logic [5:] {ADD = 'b, SUB = 'b, AND = 'b, OR = 'b, SLT = 'b} fnctcode; Ø 23

24 SystemVerilog Version modle controller(inpt logic clk, reset, inpt logic [5:] op, fnct, inpt logic zero, otpt logic memread, memwrite, alsrca, otpt logic memtoreg, iord, pcen, otpt logic regwrite, regdst, otpt logic [:] pcsrc, alsrcb, otpt logic [2:] alcontrol, otpt logic [3:] irwrite); statetype state; logic pcwrite, branch; logic [:] alop; // control FS statelogic statelog(clk, reset, op, state); otptlogic otptlog(state, memread, memwrite, alsrca, memtoreg, iord, regwrite, regdst, pcsrc, alsrcb, irwrite, pcwrite, branch, alop); // other control decoding aldec ac(alop, fnct, alcontrol); assign pcen = pcwrite (branch & zero); // program conter enable w Old: Verilog n n New Seqential Blocks // combinational clk) // seqential (latch or ff) w New: SystemVerilog n n n always_comb // combinational clk) // seqential with ff always_latch // level-sensitive latch // gate inferred from the code // don t se this one Ø 24

25 NS logic: Verilog // state clk) if(reset) state <= FETCH; else state <= netstate; // net state logic (combinational) case(state) FETCH: netstate <= FETCH2; FETCH2: netstate <= FETCH3; FETCH3: netstate <= FETCH4; FETCH4: netstate <= DECODE; DECODE: case(op) LB: netstate <= EADR; SB: netstate <= EADR; ADDI: netstate <= EADR; RTYPE: netstate <= RTYPEEX; BEQ: netstate <= BEQEX; J: netstate <= JEX; // shold never happen defalt: netstate <= FETCH; case EADR: case(op) LB: netstate <= LBRD; SB: netstate <= SBWR; ADDI: netstate <= ADDIWR; // shold never happen defalt: netstate <= FETCH; case LBRD: netstate <= LBWR; LBWR: netstate <= FETCH; SBWR: netstate <= FETCH; RTYPEEX: netstate <= RTYPEWR; RTYPEWR: netstate <= FETCH; BEQEX: netstate <= FETCH; JEX: netstate <= FETCH; ADDIWR: netstate <= FETCH; // shold never happen defalt: netstate <= FETCH; case NS logic: SystemVerilog modle statelogic(inpt logic clk, reset, inpt logic [5:] op, otpt statetype state); statetype netstate; clk) if (reset) state <= FETCH; else state <= netstate; always_comb case (state) FETCH: netstate = FETCH2; FETCH2: netstate = FETCH3; FETCH3: netstate = FETCH4; FETCH4: netstate = DECODE; DECODE: case(op) LB: netstate = EADR; SB: netstate = EADR; RTYPE: netstate = RTYPEEX; BEQ: netstate = BEQEX; J: netstate = JEX; defalt: netstate = FETCH; // shold never happen case EADR: case(op) LB: netstate = LBRD; SB: netstate = SBWR; defalt: netstate = FETCH; // shold never happen case LBRD: netstate = LBWR; LBWR: netstate = FETCH; SBWR: netstate = FETCH; RTYPEEX: netstate = RTYPEWR; RTYPEWR: netstate = FETCH; BEQEX: netstate = FETCH; JEX: netstate = FETCH; defalt: netstate = FETCH; // shold never happen case Ø 25

26 Otpts: Verilog // set all otpts to zero, then // conditionally assert jst the // appropriate ones irwrite <= 4'b; pcwrite <= ; pcwritecond <= ; regwrite <= ; regdst <= ; memread <= ; memwrite <= ; alsrca <= ; alsrcb <= 2'b; alop <= 2'b; pcsorce <= 2'b; iord <= ; memtoreg <= ; case(state) FETCH: memread <= ; irwrite <= 4'b; alsrcb <= 2'b; pcwrite <= ; FETCH2: memread <= ; irwrite <= 4'b; alsrcb <= 2'b; pcwrite <= ; FETCH3: memread <= ; irwrite <= 4'b; alsrcb <= 2'b; pcwrite <= ; FETCH4: memread <= ; irwrite <= 4'b; alsrcb <= 2'b; pcwrite <= ; DECODE: alsrcb <= 2'b;... case Otpts: SystemVerilog modle otptlogic(inpt statetype state, otpt logic memread, memwrite, alsrca, otpt logic memtoreg, iord, otpt logic regwrite, regdst, otpt logic [:] pcsrc, alsrcb, otpt logic [3:] irwrite, otpt logic pcwrite, branch, otpt logic [:] alop); always_comb // set all otpts to zero, then // conditionally assert jst the appropriate ones irwrite = 4'b; pcwrite = ; branch = ; regwrite = ; regdst = ; memread = ; memwrite = ; alsrca = ; alsrcb = 2'b; alop = 2'b; pcsrc = 2'b; iord = ; memtoreg = ; case (state) FETCH: memread = ; irwrite = 4'b; alsrcb = 2'b; pcwrite = ; FETCH2: memread <= ; irwrite <= 4'b; alsrcb <= 2'b; pcwrite <= ; FETCH3: memread <= ; irwrite <= 4'b; alsrcb <= 2'b; pcwrite <= ; FETCH4: memread <= ; irwrite <= 4'b; alsrcb <= 2'b; pcwrite <= ; DECODE: alsrcb <= 2'b;... case Ø 2

27 Otpts: SystemVerilog modle aldec(inpt logic [:] alop, inpt logic [5:] fnct, otpt logic [2:] alcontrol); always_comb case (alop) 2'b: alcontrol = 3'b; // add for lb/sb/addi 2'b: alcontrol = 3'b; // sbtract (for beq) defalt: case(fnct) // R-Type instrctions ADD: alcontrol = 3'b; SUB: alcontrol = 3'b; AND: alcontrol = 3'b; OR: alcontrol = 3'b; SLT: alcontrol = 3'b; defalt: alcontrol = 3'b; // shold never happen case case Flops, etc.: SystemVerilog modle flop #(parameter WIDTH = 8) (inpt logic clk, inpt logic [WIDTH-:] d, otpt logic [WIDTH-:] q); clk) q <= d; modle flopen #(parameter WIDTH = 8) (inpt logic clk, en, inpt logic [WIDTH-:] d, otpt logic [WIDTH-:] q); clk) if (en) q <= d; Ø 27