Quiz #1 EEC 483, Spring 2019

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1 Qiz # EEC 483, Spring 29 Date: Jan 22 Name: Eercise #: Translate the following instrction in C into IPS code. Eercise #2: Translate the following instrction in C into IPS code. Hint: operand C is stored in ; ths, yo first need to read this from (load word or lw) and save it into a temporary register.

2 Eercise #3: Translate the following instrction in C into IPS code. Hint: operand B & C are stored in ; ths, yo first need to read these from (load word or lw) and save it into a temporary register. Reslt location ( A ) is also in. The final operation shold be write to (sw). Eercise #4: Translate the following instrction in C into IPS code. Eercise #5: add $3, $3, $4 is interpreted as $3=$3+$4. How is addi $3, $3, 4 interpreted?

3 Qiz #2 EEC 483, Spring 29 Date: Jan 29 Name: Eercise #. (a) Translate the following 32-bit binary integer to decimal nmber. Hint: Yo can jst say, for eample, (b) Translate the following 32-bit integer to headecimal nmber. Eercise #2: Translate the following instrction in C into IPS code. Hint: operand C is stored in ; ths, yo first need to read this from (load word or lw) and save it into a temporary register.

4 Eercise #3. Let s consider translating the following IPS code into a machine instrction. add $2, $3, $4 (a) format consists of 6-bit opcode, 5-bit rs, 5-bit rt, 5-bit rd, 5-bit shamt, and 6-bit fnction code. The opcode and fnction code for add are and. Answer the followings in binary format. 5-bit rs =, 5-bit rt =, 5-bit rd =, 5-bit shamt = (b) Answer the 32-bit IPS instrction for the add instrction in 32-bit binary format. (c) Answer the 32-bit IPS instrction for the add instrction in 32-bit headecimal format. (d) This 32-bit nmber represents the add instrction. Assme instead it is an integer. Translate the integer to decimal nmber. Eercise #4. It is desired to load A[3] into $8. In other words, $8 <== A[3]. Assme $ points to the base address of array A. (a) What is the IPS instrction for this? Which one is correct? (Circle the correct one.) (i) lw $8, 2($) (ii) lw $, 3($8) (iii) lw $8, 3($) (iv) sw $8, 2($) (v) sw $, 3($8) (vi) sw $8, 3($) (b) Assme that a similar IPS instrction is represented as follows. Rewrite this instrction in binary format. 35 reg reg 6-bit address (c) Answer the 32-bit IPS instrction in 32-bit headecimal format. Eercise #5. Project # is implemented in the following 6 modles written in VHDL - microcompter.vhd, mips.vhd, inst_mem_28b.vhd, _mem_64b.vhd, ALU.vhd, and ALU_32.vhd. Draw a conceptal drawing showing the relationship between the modles. E.g., the ALU modle is inside the ALU_32 modle.

5 Qiz #3 EEC 483, Spring 29 Date: Feb 2 Name:. It is desired to load A[] into $8, i.e., lw $8, X($9). Assme $9 contains the base address of array A. emory content 4 8 lw $8, X($9) c 4 8 c A[] $9 contains the based address of array A 2 A[] (i.e., $9 = c) (a) What is the address for A[]? Answer in headecimal nmber. Hint: Remember that A[] is at c, A[] is at 2, etc. (b) What shold be the offset (X) in the lw instrction where $9 contains the base address of array A, i.e., A[]? Answer in headecimal nmber. Hint: The location of A[] is eqal to $9 + X. What is X? (c) What is the machine code representation of the lw $8, X($9) instrction? Opcode for lw =. Answer in binary format. The format of the lw instrction is as follows. 23 rs rt 6-bit offset (d) Answer the 32-bit IPS instrction in 32-bit headecimal format.

6 2. (a) ake path connections which will be sed when eecting add $8, $4, $7 instrction. regis te r regis te r 2 Reg isters Wri te regis te r Wri te da ta da ta da ta 2 ALU AL U re slt A ddress me mo ry opcode rs rt rd shamt fnct (b) Repeat the same qestion as above for sw $8, ($4) instrction. regis te r regis te r 2 Reg isters Wri te regis te r Wri te da ta da ta da ta 2 ALU AL U re slt A ddress me mo ry opcode rs rt 6-bit offset (c) Repeat the same qestion as above for lw $8, ff($4) instrction. regis te r regis te r 2 Reg isters Wri te regis te r Wri te da ta da ta da ta 2 ALU AL U re slt A ddress me mo ry opcode rs rt 6-bit offset

7 Qiz #4 EEC 483, Spring 29 Date: Feb 2 Name:. In reference to the IP cp shown in the below, fill ot the blanks with,, or X (don t care) in the table in the below. Note that a mltipleor control signal PCSrc is derived from Branch & flag. Note also the location of and in each of the 4 mltipleors to answer correctly. RegDst ALUSrc emtoreg PCSrc Reg em em ALUOp ALUOp R-type lw sw beq PCSrc 4 Reg Shift left 2 ALU PC address [3 ] [25 2] [2 6] [5 ] RegDst [5 ] register register 2 register 2 Registers 6 Sign 32 etend ALUSrc ALU control ALU ALU em em emtoreg [5 ] ALUOp

8 2. The following three figre show the 32-bit ALU that performs AND, OR, ADD, SUB, SLT and BEQ instrctions by connecting 32 -bit ALU s. Figre (c) shows the completed 32-bit ALU and Figres (a) and (b) show -bit ALU s. Note that Figre (a) is -bit ALU for bit~3 and Figre (b) is -bit ALU for bit3. Binvert and Bnegate are sed interchangeably. Binvert CarryIn Operation a Bnegate Operation b 2 Reslt a b CarryIn ALU Less CarryOt Reslt Less 3 a. CarryOt a b CarryIn ALU Less CarryOt Reslt a Binvert CarryIn Operation a2 b2 CarryIn ALU2 Less CarryOt Reslt2 b 2 Reslt Less 3 Set a3 b3 CarryIn ALU3 Less Reslt3 Set Overflow b. Overflow detection Overflow (i) What are the control signals (Binvert and Operation) for AND operation? (ii) What are the control signals (Binvert and Operation) for SUB operation? (iii) Which instrction is otpt for? (iv) What are the control signals (Binvert and Operation) for SLT operation? (v) What does SLT $, $2, $3 mean? (vi) In case of SLT operation, Operation 3 is selected. ark on Fig. (a) and (b), which inpt is chosen when the mltipleor control (Operation) is 3. (E.g., draw lines over one of the eisting lines in the figre.) (vii) In case of SLT operation, Operation 3 is selected. In Fig (c), what are Reslt, Reslt2,, Reslt3 when the mltipleor control (Operation) is 3? (viii) Note that Set otpt from bit3-alu is connected to Less inpt to bit-alu. ark this connection on Fig (c).

9 Qiz #5 EEC 483, Spring 29 Date: Febrary 28 (TH) Name: A pipelined CPU eectes the following 5 instrctions starting at PC= 6. Assme $2=2, $3=3, $4=4, and $=b. 6 sb $, $3, $2 64 and $2, $, $4 68 or $3, $6, $ 6c add $4, $8, $9 6 sw $5, ($2) Encoding of the above five instrctions are as follows. 6 or or or cb c or or ac4f 64. Dring the st cycle of eection, sb instrction enters the pipeline and is eected in IF stage. sb $,$3,$2 IF/ID ID/EX EX/E E/WB (a) (j) (m) (b) 4 (q) (t) Shift left 2 PC (c) (d) (e) register register 2 Registers 2 register (k) (l) (n) (o) ALU ALU (r) () (v) () (y) (z (h) 6 Sign etend 32 (p) (i) (s) (w) What is the vale of line (a)? (Hint: Consider what the crrent PC is.) What is the vale of line (c)? (Hint: 32-bit instrction word. Answer in headecimal.)

10 2. Dring the 2 nd cycle of eection, sb moves to ID stage and and enters to IF stage. and $2,$,$4 sb $,$3,$2 IF/ID ID/EX EX/E E/WB (a) (j) (m) (b) 4 (q) (t) Shift left 2 PC (c) (d) (e) register register 2 Registers 2 register (k) (l) (n) (o) ALU ALU (r) () (v) () (y) (z (h) 6 Sign etend 32 (p) (i) (s) (w) What is the vale of line (j)? (Hint: This shold be the same as (a) in the st cycle.) What is the vale of line (a)? What is the vale of line (c)? What is the vale of line (d)? What is the vale of line (e)? What is the vale of line (k)? What is the vale of line (l)? Hint: Note that we assmed $2=2, $3=3, $4=4, and $=b. What is the vale of line (h)? Hint: As noted earlier, the 32-bit encoding of sb instrction is or What is the vale of line (i)?

11 3. Dring the 3 rd cycle of eection, sb moves to EX, and moves to ID, and or in IF. or $3,$6,$ and $2,$,$4 sb $,$3,$2 IF/ID ID/EX EX/E E/WB (a) (j) (m) (b) 4 (q) (t) Shift left 2 PC (c) (d) (e) register register 2 Registers 2 register (k) (l) (n) (o) ALU ALU (r) () (v) () (y) (z (h) 6 Sign etend 32 (p) (i) (s) (w) What is the vale of line (m)? What is the vale of line (j)? What is the vale of line (a)? What is the vale of line (n)? (Hint: This mst be the same as (k) in the 2 nd cycle.) What is the vale of line (o)? (Hint: This mst be the same as (l) in the 2 nd cycle.) What is the vale of line (r)? What is the vale of line (d)? What is the vale of line (e)? What is the vale of line (k)? What is the vale of line (l)? Hint: Note that we assmed $2=2, $3=3, $4=4, and $=b. What is the vale of line (p)? (Hint: This mst be based on (h) in the 2 nd cycle.) What is the vale of line (h)? Hint: As noted earlier, the 32-bit encoding of and instrction is or What is the vale of line (s)? (Hint: This mst be the same as (i) in the 2 nd cycle.) What is the vale of line (i)? OPTIONAL: What is the vale of line (q)?

12 4. Dring the 4 th cycle, sb in E (do nothing), and in EX, or in ID, and add in IF. add $4,$8,$9 or $3,$6,$ and $2,$,$4 sb $,$3,$2 IF/ID ID/EX EX/E E/WB (a) (j) (m) (b) 4 (q) (t) Shift left 2 PC (c) (d) (e) register register 2 Registers 2 register (k) (l) (n) (o) ALU ALU (r) () (v) () (y) (z (h) 6 Sign etend 32 (p) (i) (s) (w) What is the vale of line (m)? What is the vale of line (j)? What is the vale of line (a)? What is the vale of line (n)? What is the vale of line (o)? What is the vale of line ()? What is the vale of line (r)? Line (n) does not carry the semantically correct vale. What is the correct vale? And which line can it be fed from? What is the vale of line (w)? What is the vale of line (s)? What is the vale of line (i)? OPTIONAL: What is the vale of line (t)? What is the vale of line (p)? What is the vale of line (q)?

13 5. Dring the 5 th cycle, sb in WB, and in E, or in EX, add in ID, and sw in IF. sw $5, ($2) add $4, $8, $9 or $3, $6, $ and $2, $, $4 sb $, $3, $2 IF/ID ID/EX EX/E E/WB (a) (j) (m) (b) 4 (q) (t) Shift left 2 PC (c) (d) (e) register register 2 Registers 2 register (k) (l) (n) (o) ALU ALU (r) () (v) () (y) (z (h) 6 Sign etend 32 (p) (i) (s) (w) What is the vale of line (d) (Rs in ID stage)? What is the vale of line (e) (Rt in ID stage)? What is the vale of line (Rd in WB stage)? What is the vale of line (w) (Rd in E stage)? What is the vale of line (s) (Rd in EX stage)? What is the vale of line (i) (Rd in ID stage)? * Note that the first for are referred to as IF/ID.Rs, IF/ID.Rt, EX/E.Rd and E/WB.Rd, respectively, where IF/ID is the pipeline register between IF and ID stage. Similarly, EX/E and E/WB are pipeline registers between two sccessive pipeline stages. What is the vale of line (o)? Line (o) does not carry the semantically correct vale. What is the correct vale? And which line can it be fed from?

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