CSE Introduction to Computer Architecture Chapter 5 The Processor: Datapath & Control

Transcription

1 CSE Introdction to Compter Architectre Chapter 5 The Processor: Datapath & Control Dr. Izadi

2 Data Processor Register # PC Address Registers ALU memory Register # Register # Address Data memory Data We're ready to look at an implementation of the IPS Simplified to contain only: memory-reference instrctions: lw, sw arithmetic-logical instrctions: add, sb, and, or, slt control flow instrctions: beq, j Generic Implementation: se the program conter (PC) to spply instrction address get the instrction from memory read (write) from (to) registers the op-code determines eactly what to do All instrctions se the ALU after reading the registers Why? memory-reference? arithmetic? control flow? 2

3 ore Implementation Details Abstract / Simplified View: Data Register # PC Address Registers ALU memory Register # Register # Address Data memory Two types of fnctional nits: Elements that operate on vales (combinational) ALU Elements that contain state (seqential) Registers and memory Data 3

4 State Elements Unclocked vs. Clocked Clocks sed in synchronos logic when shold an element that contains state be pdated? Falling edge Clock period cycle time Rising edge 4

5 An Unclocked State Element The set-reset latch Otpt depends on present inpts and also on past inpts S R Q Q - R S Q Q 5

6 D-latch D Q(t+) D C Q Two inpts: the vale to be stored (D) the clock signal (C) indicating when to read & store D Two otpts: the vale of the internal state (Q) and it's complement C D Q _ Q 6

7 Latches and Flip-flops Otpt is eqal to the stored vale inside the element (don't need to ask for permission to look at the vale) Change of state (vale) is based on the clock Latches: whenever the clock is asserted (high or low) and the inpt changes Flip-flop: whenever the clock is asserted (low to high or high to low transition) and the inpt changes (edge-triggered methodology) Note: "logically tre cold mean electrically low 7

8 D flip-flop Otpt changes only on the clock edge D D C D latch Q D C D latch Q Q Q Q C D C Q 8

9 Or Implementation An edge triggered methodology Typical eection: read contents of some state elements, send vales throgh some combinational logic write reslts to one or more state elements State element Combinational logic State element 2 Clock cycle 9

10 Clocking ethodology A clocking methodology defines when signals can be read and written woldn't want to read a signal at the same time it was being written Clk Setp Hold Setp Hold Don t Care All storage elements are clocked by the same clock edge Cycle Time CLK-to-Q + Longest Delay Path + Setp + Clock Skew (CLK-to-Q + Shortest Delay Path - Clock Skew) > Hold Time......

11 Abstraction ake sre yo nderstand the abstractions! Sometimes it is easy to think yo do, when yo Select don t 32 A 32 B Select 32 C A3 B3 A3 B3.. C3 C3 A B C

12 Register File operation sing D flip-flops and UX s register nmber Register register nmber register nmber 2 Register... Register n 2 register Register file 2 Register n register nmber 2 2 What is the fnction of above? 2

13 Register File and register nmber register nmber 2 register nmber register nmber 2 register Register Register Register n Register n Register file 2 Register n-to- decoder n n C Register D C Register D C Register n D 2 Data C Registern D How many registers can we read and write at the same time? Does this spport IPS instrctions reqirements? 3

14 Bilding the Datapath Inclde the fnctional nits we need for each instrction address em memory PC Add Sm Address Data memory 6 Sign 32 etend Register nmbers Data a. memory b. Program conter 5 3 register 5 5 register 2 Registers register 2 Reg Data c. Adder ALU control ALU ALU reslt a. Registers b. ALU Use mltipleors to stitch them together Zero em a. Data memory nit ALU Control: AND OR add sbtract set-on-less-than b. Sign-etension nit 4

15 Datapath for Fetch and R-s Portion of path for fetching instrctions and pdating PC Add 4 PC address memory R-format instrctions: read two registers and write one register ALU control register register 2 Registers register 2 Reg 3 Zero ALU ALU reslt ALU Control: AND OR add sbtract set-on-less-than 5

16 Datapath for lw and sw Instrctions lw $t, offset_vale($t2) or sw $t, offset_vale ($t2) Compte memory address Sign etend 6 bit to 32 bit Registers re giste r da ta re giste r 2 3 ALU operation Zero em re giste r 2 ALU ALU re s lt Address Rea RegW rite da ta Data memory 6 32 Sign etend em 6

17 Bilding beq beq $t, $t2, offset Compare registers, se ALU to affect Z flag If not eqal, net PC <= PC +4 If eqal, sign etend the offset and shift by two PC + 4 Net instrction address Shift left 2 Add ALU reslt register re gister 2 register Reg Registers 2 6 Sign 32 etend ALU operation 3 Zero ALU Branch control 7

18 A Simple Implementation of a Datapath Covers: lw, sw, beq, add, sb, and, or, set-on-less-than Use mltipleors to stitch them together register register 2 register Reg Registers Sign etend ALUSrc 3 ALU operation Zero ALU ALU reslt Address em em Data memory emtoreg 8

19 Implementation of the Datapath PCSrc Add 4 Shift left 2 Add ALU reslt PC address memory register register 2 register Registers 2 Reg 6 Sign 32 etend ALUSrc 3 ALUoperation Zero ALU ALU reslt Address em em Data memory emtoreg 9

20 Three Classes R-Type op rs rt rd shamt fnct rd: destination Load and Store s op rs rt 6 bit offset rt: destination Branch op rs rt 6 bit offset rt: destination 2

21 Completed Data Path PCSrc Add ALU reslt Add Shift left 2 4 Reg PC address memory [3 ] [25 2] [2 6] [5 ] [5 ] RegDst register register 2 Registers register Sign etend ALUSrc Zero ALU ALU reslt ALU Control em Address Data memory em emtoreg 2

22 Control Using the op-code from the instrction, the control isses signals to: Selecting the operations to perform (ALU, read/write, etc.) Controlling the flow of (mltipleer inpts) ALU's operation based on instrction type and fnction code Eample: what shold the ALU do with the instrction add $8, $7, $8 op rs rt rd shamt fnct 22

23 Control Eample: what shold the ALU do with the instrction lw $, ($2) 35 2 op rs rt 6 bit offset Why is the ALU code for sbtract is and not? 23

24 ALU Control st describe hardware to compte 3-bit ALU control inpt Given instrction type = lw, sw = beq, = arithmetic ALUOp Fnction code for arithmetic compted from instrction type ALUOp Fnct field Operation ALUOp ALUOp F5 F4 F3 F2 F F X X X X X X add X X X X X X sb (X) X X add (X) X X sb (X) X X and (X) X X or (X) X X slt ALU Control: AND OR add sbtract set-on-less-than 24

25 ALU Control F(5 ) F3 F2 F F Inpts ALUOp Fnct field Operation ALUOp ALUOp F5 F4 F3 F2 F F 2 X X X X X X add X X X X X X sb X X add X X sb X X and X X or X X slt ALUOp ALUOp ALUOp ALU control block Operation2 Operation Operation Operation Otpts li-level decoding can redce size of control nit and increase its speed. 25

26 A Simple Control PCSrc Add ALU reslt Add Shift left 2 4 Reg PC address memory [3 ] [25 2] [2 6] [5 ] RegDst register register 2 Registers register 2 ALUSrc Zero ALU ALU reslt Address em Data memory emtoreg [5 ] 6 32 Sign etend ALU control em [5 ] ALUop 26

27 Control 4 Add [3 26] Control RegDst Branch em emtoreg ALUOp em ALUSrc Reg Shift left 2 Add ALU reslt PC address memory [3 ] [25 2] [2 6] [5 ] register register 2 Registers 2 register Zero ALU ALU reslt Address Data memory [5 ] 6 32 Sign etend ALU control [5 ] emto- Reg em em Opcode RegDst ALUSrc Reg Branch ALUOpALUOp R-format lw sw X X beq X X 27

28 Single Cycle Control Simple combinational logic Inpts ALUOp ALUOp ALUOp ALU control block Op5 Op4 Op3 Op2 Op Op F(5 ) F3 F2 F F Operation2 Operation Operation Operation R-format Iw sw beq Otpts RegDst ALUSrc emtoreg Reg em em Branch ALUOp ALUOpO 28

29 Or Simple Control Strctre All of the logic is combinational We wait for everything to settle down, and the right thing to be done ALU might not prodce right answer right away we se write signals along with clock to determine when to write Cycle time determined by length of the longest path Content of PC Combinational logic Content of PC Clock 29

30 Single Cycle Implementation Calclate cycle time assming negligible delays ecept: memory (2ns), ALU and adders (2ns), register file access (ns) PCSrc Add 4 Reg Shift left 2 Add ALU reslt PC address [3 ] memory [25 2] [2 6] [5 ] RegDst [5 ] register register 2 register 2 Registers 6 Sign 32 etend ALUSrc ALU control Zero ALU ALU reslt em Address Data memory em emtoreg [5 ] ALUOp 3

31 Single Cycle Implementation Calclate cycle time assming negligible delays ecept: memory (2ns), ALU and adders (2ns), register file access (ns) PCSrc 4 Add Reg Shift left 2 Add ALU res lt PC address In str ction [3 ] memory In strctio n [25 2 ] In strctio n [2 6] In strctio n [5 ] RegDst In strctio n [5 ] register register 2 register d ata d ata 2 Registers 6 Sign 32 etend ALUSrc ALU control ALU Zero ALU reslt em Address Data memory em emtoreg [5 ] ALUOp Instr. emory Register ALU Op. Data emory Reg. Total R-format ns lw ns sw ns beq ns 3

32 Single Cycle Problems: Cycle time shold accommodate the longest instrction. What if we had more complicated instrctions like floating point? Can se a nit only once dring a cycle ay need mltiple copies of some fnctional nits (wastefl of area) One Soltion: se a smaller cycle time have different instrctions take different nmbers of cycles a mlti-cycle path: 32

33 lti-cycle Approach We will be resing fnctional nits ALU sed to compte address and the new PC vale Same memory sed for instrction and Break p the instrctions into steps, each step takes a cycle Balance the amont of work to be done Restrict each cycle to se only one major fnctional nit Or control signals will not be determined solely by instrction, bt also by the crrent step e.g., what shold the ALU do for an add instrction? At the end of a cycle (step) Store vales for se in later steps Introdce additional internal registers 33

34 lti-cycle Approach Added components IR and DR both needed dring the same cycle A and B registers to hold operand vales ALUOt register PC Address emory Data or register emory register Data Register # Registers Register # Register # A B ALU ALUOt 34

35 lticycle Approach Internal registers ecept IR are pdated every clock cycle; No write control Need to add new UX s and epand eisting UX s PC Address emory emdata [25 2] [2 6] [5 ] register [5 ] [5 ] register register 2 Registers register 2 A B Zero ALU ALU reslt ALUOt emory register 6 Sign etend 32 Shift left2 35

36 Control Signals REGDst PCSorce em em IorD IR REG 26 Shift left2 ALUSrcA 32 2 PC PC PCCond Address emory emdata Zero (ALU) [25 2] [2 6] [5 ] register [5 ] emory register [5 ] 6 register register 2 Registers register emtoreg 2 32 Sign etend Shift left2 A B Zero ALU ALU reslt ALUSrcB ALU control ALUOp ALUOt 36

37 s from ISA Perspective Consider each instrction from perspective of ISA. Eample: The add instrction changes a register. Register specified by bits 5: of instrction. specified by the PC. New vale is the sm ( op ) of two registers. Registers specified by bits 25:2 and 2:6 of the instrction Reg[emory[PC][5:]] <= Reg[emory[PC][25:2]] op Reg[emory[PC][2:6]] In order to accomplish this we mst break p the instrction. (kind of like introdcing variables when programming) 37

38 Breaking Down of an ISA definition of arithmetic: Reg[emory[PC][5:]] <= Reg[emory[PC][25:2]] op Reg[emory[PC][2:6]] Cold break down to: IR <= emory[pc] A <= Reg[IR[25:2]] B <= Reg[IR[2:6]] ALUOt <= A op B Reg[IR[5:]] <= ALUOt We forgot an important part of the definition of arithmetic! PC <= PC

39 Idea Behind lticycle Approach We define each instrction from the ISA perspective (do this!) Break it down into steps following or rle that flows throgh at most one major fnctional nit (e.g., balance work across steps) Introdce new registers as needed (e.g, A, B, ALUOt, DR, etc.) Finally try and pack as mch work into each step (avoid nnecessary cycles) while also trying to share steps where possible (minimizes control, helps to simplify soltion) Reslt: Or book s mlticycle Implementation! 39

40 Five Eection Steps. fetch 2. decode and register fetch 3. Eection, memory address comptation, or branch completion 4. emory access or R-type instrction completion 5. -back step INSTRUCTIONS TAKE FRO 3-5 CYCLES!

41 Step : Fetch Use PC to get instrction and pt it in the Register. Increment the PC by 4 and pt the reslt back in the PC sing RTL "Register-Transfer Langage" IR <= emory[pc]; em ALUSrcA = IorD = IR ALUSrcB = ALUOp = PC PCSorce = PC <= PC + 4; PC PC PCCond em em IorD Address emory emdata Zero (ALU) IR [25 2] [2 6] [5 ] register [5 ] emory register REGDst [5 ] 6 emto Reg REG register register2 Registers register 2 Sign 32 etend Shift left2 A B 26 4 Shift left ALUSrcB PCSorce ALUSrcA ALU Zero ALU reslt ALU control 2 ALUOt ALUOp 4

42 Step 2: Decode and Register Fetch registers rs and rt (in case we need them) and pt them in A & B Compte the branch address in case the instrction is a branch; pt it in ALUOt A <= Reg[IR[25-2]]; B <= Reg[IR[2-6]]; ALUOt <= PC + (sign-etend(ir[5-]) << 2); ALUSrcA = ALUSrcB = ALUOp = lw or sw 3 R-type 2 beq 3 3 j 3 PC PC PCCond em em IorD Address emory emdata Zero (ALU) IR [25 2] [2 6] [5 ] register register register 2 Registers register 2 We are Looking at the instrction and determine what to do in the net cycle We aren't setting any control lines based on the instrction type [5 ] emory register REGDst [5 ] 6 emto Reg REG Sign 32 etend Shift left2 A B 26 4 Shift left ALUSrcB PCSorce ALUSrcA ALU Zero ALU reslt ALU control 2 ALUOt ALUOp 42

43 Step 3: Dependent ALU is performing one of three fnctions, based on instrction type (ignore j instrction for now) emory Reference: (lw or sw) R-type: Branch: beq ALUOt <= A + sign-etend(ir[5-]); ALUOt <= A op B; if (A==B) PC <= ALUOt (compte address) (eecte) (complete branch) lw ALUSrcA = ALUSrcA = ALUSrcA = ALUSrcB = ALUSrcB = ALUSrcB = ALUOp = ALUOp = ALUOp = go to step 4 PCCond PCSorce = sw end of eection fetch net instrction 43

44 For beq REGDst PCSorce em em IorD IR REG 26 Shift left 2 ALUSrcA 32 2 PC PC PCCond Address emory emdata Zero (ALU) [25 2] [2 6] [5 ] register [5 ] emory register [5 ] 6 register register 2 Registers register emtoreg 2 32 Sign etend Shift left 2 A B Zero ALU ALU reslt ALUSrcB ALU control ALUOp ALUOt For lw and sw 44

45 Step 4: R-type or emory Access Lw sw R-type DR = emory[aluot]; emory[aluot] = B; Reg[IR[5-]] = ALUOt; (read from memory) (write to memory) (store reslt) em em RegDst = IorD = IorD = REG emtoreg = end of eection fetch net instrction end of eection fetch net instrction 45

46 lw sw REGDst PCSorce PC PC PCCond em em IorD Address emory emdata Zero (ALU) IR [25 2] [2 6] [5 ] register [5 ] emory register [5 ] 6 register register 2 Registers register emtoreg REG 2 32 Sign etend Shift left 2 26 A B 4 Shift left ALUSrcA 28 Zero ALU ALU reslt ALUSrcB ALU control 32 ALUOp 2 ALUOt R-type 46

47 Step 5 Back Only for lw instrctions to store read from memory into a register Reg[IR[2-6]]= DR; RegDest = Reg emtoreg = PC PC PCCond em em IorD Address emory emdata Zero (ALU) IR [25 2] [2 6] [5 ] register [5 ] emory register REGDst [5 ] 6 emto Reg REG register register 2 Registers register 2 Sign 32 etend Shift left2 A B 26 4 Shift left ALUSrcB PCSorce ALUSrcA ALU Zero ALU reslt ALU control 2 ALUOt ALUOp 47

48 Control Smmary Step name fetch decode/register fetch Action for R-type instrctions Action for memory-reference Action for instrctions branches IR = emory[pc] PC = PC + 4 A = Reg [IR[25-2]] B = Reg [IR[2-6]] ALUOt = PC + (sign-etend (IR[5-]) << 2) Action for jmps Eection, address ALUOt = A op B ALUOt = A + sign-etend if (A ==B) then PC = PC [3-28] II comptation, branch/ (IR[5-]) PC = ALUOt (IR[25-]<<2) jmp completion emory access or R-type Reg [IR[5-]] = Load: DR = emory[aluot] completion ALUOt or Store: emory [ALUOt] = B emory read completion Load: Reg[IR[2-6]] = DR 48

49 Implementing the Control Vale of control signals is dependent pon: what instrction is being eected which step is being performed Use the information we ve accmlated to specify a finite state machine specify the finite state machine graphically, or se microprogramming Implementation can be derived from specification 49

50 Review: Finite State achines Finite state machines: A set of states and Net state fnction (determined by crrent state and the inpt) Otpt fnction (determined by crrent state and possibly inpt) Crrent state Net-state fnction Net state Inpts Clock Otpt fnction Otpts We ll se a oore machine (otpt based only on crrent state) How does oore machine varios from ealy machine? 5

51 Review: finite state machines Eample: A friend wold like yo to bild an electronic eye for se as a fake secrity device. The device consists of three lights lined p in a row, controlled by the otpts Left, iddle, and Right, which, if asserted, indicate that a light shold be on. Only one light is on at a time, and the light moves from left to right and then from right to left, ths scaring away thieves who believe that the device is monitoring their activity. Draw the graphical representation for the finite state machine sed to specify the electronic eye. Note that the rate of the eye s movement will be controlled by the clock speed (which shold not be too great) and that there are essentially no inpts. 5

52 Graphical Specification of FS don t care if not mentioned asserted if name only otherwise eact vale How many state bits will we need? 2 3 emory address comptation ALUSrcA = ALUSrcB = ALUOp = (Op ='LW') emory access (O p = 'SW') 5 Start (Op = 'LW ') or (O p = 'SW ') emory access fetch em ALUSrcA = IorD = IRW rite ALUSrcB = ALUOp = PC PCSorce = 6 7 Eection ALUSrcA = ALUSrcB = ALUOp= 8 R-type completion (Op = R-type) Branch completion ALUSrcA = ALUSrcB = ALUOp = PCCond PCSorce = (Op = 'BEQ') decode/ register fetch 9 ALUSrcA = ALUSrcB = ALUOp = (Op = 'J') Jmp completion PC PCSorce = em IorD = em IorD = RegDst = Reg emtoreg = 4 -back step RegDst= Reg emtoreg=

53 Simple Qestions How many cycles will it take to eecte this code? lw $t2, ($t3) lw $t3, 4($t3) beq $t2, $t3, Label add $t5, $t2, $t3 sw $t5, 8($t3) Label:... #assme not What is going on dring the 8th cycle of eection? In what cycle does the actal addition of $t2 and $t3 takes place? 53

54 ltiple Cycle Datapath PCWr PC IorD PCWrCond PCSrc BrWr Zero emwr IRWr RegDst RegWr ALUSelA Target 32 RAdr Ideal emory WrAdr Din Dot 32 Reg 32 Rs Rt Rt Rd 5 5 Ra Rb Reg File Rw bsa bsw bsb << Zero ALU ALU Control 32 ALU Ot Imm 6 EtOp Etend 32 emtoreg ALUSelB ALUOp 54

55 [3 26] PC Address [25 2] register emory emdata PCCond [2 6] [5 ] register [5 ] emory register PC IorD em em emtoreg IR [25-] Otpts Control Op [5 ] [5 ] PCSorce ALUOp ALUSrcB ALUSrcA Reg RegDst register 2 Registers register 6 Sign 32 etend 2 A Shift left 2 B Shift 28 left 2 PC [3 28] Zero ALU ALU reslt ALU control Jmp address [3 ] ALUOt 2 [5 ]

56 Finite State achine for Control Implementation: PC Control logic Otpts PCCond IorD em em IR emtoreg PCSorce ALUOp ALUSrcB ALUSrcA Reg RegDst Inpts NS3 NS2 NS NS Op5 Op4 Op3 Op2 Op Op S3 S2 S S register opcode field State register 56

57 PLA Implementation Op5 If I picked a horizontal or vertical line cold yo eplain it? Op code D Q D Q Op4 Op3 Op2 Op Op S3 S2 S S PC PCCond IorD e mre a d e m IR e mtore g PCSorce PCSorce ALUOp ALUOp ALUSrcB ALUSrcB ALUSrcA Reg RegDst NS3 NS2 NS NS 57

58 RO Implementation RO = " Only emory" vales of memory locations are fied ahead of time A RO can be sed to implement a trth table if the address is m-bits, we can address 2 m entries in the RO. or otpts are the bits of that the address points to. m n m n m is the "height", and n is the "width" 58

59 RO Implementation How many inpts are there? 6 bits for opcode, 4 bits for state = address lines (i.e., 2 = 24 different addresses) How many otpts are there? 6 path-control otpts, 4 state bits = 2 otpts RO is 2 2 = 2K bits (and a rather nsal size) Rather wastefl, since for lots of the entries, the otpts are the same i.e., opcode is often ignored 59

60 RO vs PLA Break p the table into two parts 4 state bits tell yo the 6 otpts, bits of RO bits tell yo the 4 net state bits, 2 4 bits of RO Total: 4.3K bits of RO PLA is mch smaller Can share prodct terms Only need entries that prodce an active otpt Can take into accont don't cares Size: (#inpts #prodct-terms) + (#otpts #prodct-terms) For this eample = (7)+(27) = 5 PLA cells PLA cells sally abot the size of a RO cell (slightly bigger) 6

61 Another Implementation Style Comple instrctions The "net state" is often crrent state + Control nit PLA or RO Inpt Otpts PC PCCond IorD em em IR B emtoreg PCSorce ALUOp ALUSrcB ALUSrcA Reg RegDst AddrCtl State Adder Address select logic Op[5 ] register opcode field 6

62 icroprogramming Control is the hard part of processor design Datapath is fairly reglar and well-organized emory is highly reglar Control is irreglar and global icroprogramming: A Particlar Strategy for Implementing the Control Unit of a processor by "programming" at the level of register transfer operations icroarchitectre: Logical strctre and fnctional capabilities of the hardware as seen by the microprogrammer Historical Note: IB 36 Series first to distingish between architectre & organization Same instrction set across wide range of implementations, each with different cost/performance 62

63 acroinstrction Verss icroinstrction ain emory eection nit ADD SUB AND... DATA User program pls Data this can change! one of these is mapped into one of these at RTL level CPU control memory AND microseqence e.g., Fetch Fetch Operand(s) Calclate Save Answer(s) 63

64 Controller Design seqencer control path control microinstrction micro-pc seqencer The state diagrams that arise define the controller for an instrction set processor are highly strctred Use this strctre to constrct a simple microseqencer Control redces to programming this very simple device microprogramming 64

65 icroprogramming Implementation of the Control Control nit icrocode memory Inp t Otpts PC PCCond Io rd emrea d em IR W rite B emtoreg PCSorce ALUOp ALUS rcb ALUS rca Reg RegDst Ad drc tl Da ta pa th icroprogra m conte r Adder Address select logic Op[5 ] Ins tr c tio n re g is te r opcode field 65

66 icroprogramming microinstrction: low level control instrction which defines a set of path control signal. A specification methodology appropriate if hndreds of opcodes, modes, cycles, etc. signals specified symbolically sing microinstrctions Label ALU control SRC SRC2 Register control emory PC control Seqencing Fetch Add PC 4 PC ALU Seq Add PC Etshft Dispatch em Add A Etend Dispatch 2 LW2 ALU Seq DR Fetch SW2 ALU Fetch Rformat Fnc code A B Seq ALU Fetch BEQ Sbt A B ALUOt-cond Fetch JUP Jmp address Fetch 66

67 Field name Vale Signals active Comment Add ALUOp = Case the ALU to add. ALU control Sbt ALUOp = Case the ALU to sbtract; this implements the compare for branches. Fnc code ALUOp = Use the instrction's fnction code to determine ALU control. SRC PC ALUSrcA = Use the PC as the first ALU inpt. A ALUSrcA = Register A is the first ALU inpt. B ALUSrcB = Register B is the second ALU inpt. SRC2 4 ALUSrcB = Use 4 as the second ALU inpt. Etend ALUSrcB = Use otpt of the sign etension nit as the second ALU inpt. Etshft ALUSrcB = Use the otpt of the shift-by-two nit as the second ALU inpt. two registers sing the rs and rt fields of the IR as the register nmbers and ptting the into registers A and B. ALU Reg, a register sing the rd field of the IR as the register nmber and Register RegDst =, the contents of the ALUOt as the. control emtoreg = DR Reg, a register sing the rt field of the IR as the register nmber and RegDst =, the contents of the DR as the. emtoreg = PC em, memory sing the PC as address; write reslt into IR (and lord = the DR). emory ALU em, memory sing the ALUOt as address; write reslt into DR. lord = ALU em, memory sing the ALUOt as address, contents of B as the lord =. ALU PCSorce = the otpt of the ALU into the PC. PC PC write control ALUOt-cond PCSorce =, If the Zero otpt of the ALU is active, write the PC with the contents PCCond of the register ALUOt. jmp address PCSorce =, the PC with the jmp address from the instrction. PC Seq AddrCtl = Choose the net microinstrction seqentially. Seqencing Fetch AddrCtl = Go to the first microinstrction to begin a new instrction. Dispatch AddrCtl = Dispatch sing the RO. Dispatch 2 AddrCtl = Dispatch sing the RO 2.

68 Details Dispatch RO Dispatch RO 2 Op Opcode name Vale Op Opcode name Vale R-format lw jmp sw beq lw sw Adder PLA or RO State 3 2 AddrCtl Dispatch RO 2 Dispatch RO Address select logic State nmber Address-control action Vale of AddrCtl Use incremented state 3 Use dispatch RO 2 Use dispatch RO Use incremented state 3 4 Replace state nmber by 5 Replace state nmber by 6 Use incremented state 3 7 Replace state nmber by 8 Replace state nmber by 9 Replace state nmber by register opcode field 68

69 aimally vs. inimally Encoded No encoding: bit for each path operation faster, reqires more memory (logic) sed for Va 78 an astonishing 4K of memory! Lots of encoding: send the microinstrctions throgh logic to get control signals ses less memory, slower Historical contet of CISC: Too mch logic to pt on a single chip with everything else Use a RO (or even RA) to hold the microcode It s easy to add new instrctions 69

70 Designing a icroinstrction Set. Start with list of control signals 2. Grop signals together that make sense (vs. random): called fields 3. Places fields in some logical order e.g., ALU operation & ALU operands first and microinstrction seqencing last 4. Create a symbolic legend for the microinstrction format, showing name of field vales and how they set the control signals Use compters to design compters 5. To minimize the width, encode operations that will never be sed at the same time 7

71 Possible Design Paths of Control Initial Representation Finite State Diagram icroprogram Seqencing Control Eplicit Net State icroprogram conter Fnction + Dispatch ROs Logic Representation Logic Eqations Trth Tables Implementation PLA RO Techniqe hardwired control microprogrammed control 7

72 icroprogramming Pros and Cons Ease of design Fleibility Easy to adapt to changes in organization, timing, technology Can make changes late in design cycle, or even in the field Can implement very powerfl instrction sets (jst more control memory) Generality Can implement mltiple instrction sets on same machine. Can tailor instrction set to application. Compatibility any organizations, same instrction set Costly to implement Slow 72

73 icrocode: Trade-offs Distinction between specification and implementation is blrred Specification Advantages: Easy to design and write Design architectre and microcode in parallel Implementation (off-chip RO) Advantages Easy to change since vales are in memory Can emlate other architectres Can make se of internal registers Implementation Disadvantages, SLOWER now that: Control is implemented on same chip as processor RO is no longer faster than RA No need to go back and make changes 73

74 Historical Perspective In the 6s and 7s microprogramming was very important for implementing machines This led to more sophisticated ISAs and the VAX In the 8s RISC processors based on pipelining became poplar Pipelining the microinstrctions is also possible! Implementations of IA-32 architectre since 486 hardwired control for simpler instrctions (few cycles, FS control implemented sing PLA or random logic) microcoded control for more comple instrctions (large nmbers of cycles, central control store) The IA-64 architectre ses a RISC-style ISA and can be implemented withot a large central control store 74

75 Pentim 4 Pipelining is important (last IA-32 withot it was 8386 in 985) Control Control I/O interface cache Enhanced floating point and mltimedia Control Data cache Integer path Secondary cache and memory interface Chapter 7 Chapter 6 Advanced pipelining hyperthreading spport Control 75

76 Control Pentim 4 Control I/O interface cache Enhanced floating point and mltimedia Control Data cache Integer path Secondary cache and memory interface Advanced pipelining hyperthreading spport Control Somewhere in all that control we mst handle comple instrctions Processor eectes simple microinstrctions, 7 bits wide (hardwired) 2 control lines for integer path (4 for floating point) If an instrction reqires more than 4 microinstrctions to implement, control from microcode RO (8 microinstrctions) Its complicated! 76

77 Smmary If we nderstand the instrctions, we can bild a simple processor! If instrctions take different amonts of time, mlti-cycle is better Datapath implemented sing: Combinational logic for arithmetic logic nit State holding elements for registers and memory Control implemented sing: Combinational logic for single-cycle implementation Finite state machine for mlti-cycle implementation 77