TES Detectors (and SQUID Muxes) at NIST
|
|
- Valentine Woods
- 6 years ago
- Views:
Transcription
1 TES Detectors (and SQUID Muxes) at NIST Gene Hilton Kent Irwin William Duncan National Institute of Standards and Technology Boulder, Colorado December 13, 2006
2 Quantum Sensors Project Jim Beall Randy Doriese William Duncan Lisa Ferreira Gene Hilton Rob Horansky Kent Irwin Ben Mates Nathan Miller Galen O Neil Carl Reintsema Dan Schmidt Joel Ullom Leila Vale Yizi Xu Barry Zink Some of us...
3 Outline SCUBA-2 Overview Multiplexers Detectors Array Integration Readout Electronics Results Yield NIST sub-mm Imagers for CCAT Overview Multiplexer improvement Detector simplification Array Integration Testing Costs
4 SCUBA-2 Overview Implanted Absorber Detector Brick Detector Frame SQUID Multiplexer Wafer Bump Bonds Silicon Nitride Support Membrane SCUBA Imagers are fabricated using two separate wafer-scale chips - Detector and Multiplexer Each wafer sub-arrays consists of array pixels (1280 total) on a mm pitch Four sub-arrays are tiled to make a focal plane Two focal planes, 450 µm and 850µm
5 SCUBA-2 Multiplexer Standard NIST SQUID process Nb/AlO x /Nb junction ECR-PECVD low-temperature SiO 2 3 wiring levels, 10 lithography levels 0.8 µm minimum feature size
6 SCUBA-2 Multiplexer Standard NIST SQUID process Nb/AlO x /Nb junction ECR-PECVD low-temperature SiO 2 3 wiring levels, 10 lithography levels 0.8 µm minimum feature size... with some differences Wafer-scale pattern (made on a stepper) - 60 reticles! Two additional layers (SiO 2 and Mo) for bump-bond compatibility In-process testing
7 SCUBA-2 Detectors Brick Wafer Absorber ion implantation Oxidation Fusion Bonding Detector Substrate Wafer TES Detector Fabrication Patterning for brick formation Handle Wafer Grind/polish to desired brick thickness Grow silicon nitride membrane Reaqcuire alignment marks Bilayer formation and patterning (Mo/Cu) Additional normal metal (Cu) Passivation (SiO2) Shielding/bump interface (Mo) Mechanical Electrical Scottish Microelectronics Centre
8 SCUBA-2 Array Integration TES Detector Wafer Flatness determination Bump formation (In) Imager Hybrid Final Micromachining Focal Plane Integration SQUID Multiplexer Wafer Selection of wafer pairs Cold-welding hybridization Blanket-etch handle removal Bosch etch brick and frame formation Laser dicing Thermal mount on hairbrush Wirebond Cryogenic and optical test Flatness determination Bump formation (In)
9 SCUBA-2 Array Integration TES Detector Wafer Flatness determination Bump formation (In) Imager Hybrid Final Micromachining Focal Plane Integration SQUID Multiplexer Wafer Selection of wafer pairs Cold-welding hybridization Blanket-etch handle removal Bosch etch brick and frame formation Laser dicing Thermal mount on hairbrush Wirebond Cryogenic and optical test Flatness determination Bump formation (In) Sub-array Niobium Flex Series-array SQUID preamps
10 Readout Electronics UBC readout electronics - next talk
11 Two Detector Subarrays Are Now Cold Carl and Kent in Edinburgh November 30, 2006
12 Key Results Prototype Arrays Basic mux and detector functionality Measured detector/mux interactions - detector design changed and tested Measured mux crosstalk issues - multiplexer design changed and tested Measured NEP and optical response - well within requirements
13 Key Results Prototype Arrays Basic mux and detector functionality Measured detector/mux interactions - detector design changed and tested Measured mux crosstalk issues - multiplexer design changed and tested Measured NEP and optical response - well within requirements Science-Grade Arrays Two currently cold at the ATC in Edinburgh Working TESs and heaters on both arrays Optical response Further software development is key next step
14 Yield Multiplexer wafers - obtain 50% usable parts after cryogenic testing. First cryogenic testing 1 year ago. Detectors wafers - obtain 40% for starting stock (mechanical wafer bonding) Detector wafers - TESs and deep etch high but unknown Hybridization - 100% so far
15 M.07.0X I c max µa M I c max µa M.07.02
16 M.09.0X I c max µa M I c max µa M.09.01
17 New sub-mm Imagers Less risk, less flexibility 1K pixel/subarray mm pixel pitch 130 mk Less setup cost Earlier initial production Other wavelengths possible with minimal development More flexibility, more risk 4K pixel/subarray 0.5 mm pixel pitch More pixels per output channel Simpler magnetic shielding Other operating temperatures? Less production cost (per pixel, per sub-array?)
18 Multiplexer improvement Second-order gradiometric SQUIDS Much less magnetic shielding required ( 100 reduction in effective area) Improved SQUID noise (2 - helps muxing or reduces unit cell) Improved dynamic range (4 )
19 Multiplexer improvement Second-order gradiometric SQUIDS Much less magnetic shielding required ( 100 reduction in effective area) Improved SQUID noise (2 - helps muxing or reduces unit cell) Improved dynamic range (4 ) The new designs will allow us to shrink the multiplexer unit cell to 0.5 mm and allow pixel 4 increase in pixel count. We believe new designs can achieve significant yield enhancement over older SCUBA-2 designs.
20 Detector Improvements Since original SCUBA-2 start, NIST now has all tools necessary to replicate SCUBA-2 detector mechanical wafers (STS Deep Etch, Wafer Bonder) Simplification Can fabricate on thin flat wafers ( 100 µm) Use temporary carrier wafers (wax mounted) as necessary. Some implications for passband at shorter wavelengths Other methods (SOI, polymer bonding,... ) under study Bump Bonding Now have potential two sources for Indium bump bonding, Raytheon and NASA GSFC Goddard has experience bonding fragile parts - microshutters for NGST Higher Operating temperature -lower G with membrane perforation Other possibilities Different geometries (HCP, match to spectrometer,... ) Multi-color sensitivity
21 Relieved (Low G) X-ray Pixels
22 Testing SCUBA-2 has taught us the importance of fast turn-around on testing. We have invested in a very large dilution refrigerator to enable large-scale testing of imager components.
23 Testing SCUBA-2 has taught us the importance of fast turn-around on testing. We have invested in a very large dilution refrigerator to enable large-scale testing of imager components.
24 Cost
25 Cost
26
27 Outline 1 Overview 2 SCUBA-2 Overview Multiplexers Detectors Array Integration Readout Electronics SCUBA-2 Results SCUBA-2 Yield 3 NIST sub-mm Imagers for CCAT Overview Multiplexer improvement Detector Improvements Imager Testing Cost
Magnetically actuated microshutter arrays
Magnetically actuated microshutter arrays D. B. Mott *1, S.Aslam 1,2, K. A. Blumenstock 1, R. K. Fettig 1,2, D. Franz 1,2, A. S. Kutyrev 1,2, M. J. Li 1, C. J. Monroy 1,2, S. H. Moseley 1, D. S. Schwinger
More informationMicraGEM-Si A flexible process platform for complex MEMS devices
MicraGEM-Si A flexible process platform for complex MEMS devices By Dean Spicer, Jared Crawford, Collin Twanow, and Nick Wakefield Introduction MicraGEM-Si is a process platform for MEMS prototyping and
More informationHeterogeneous Integration and the Photonics Packaging Roadmap
Heterogeneous Integration and the Photonics Packaging Roadmap Presented by W. R. Bottoms Packaging Photonics for Speed & Bandwidth The Functions Of A Package Protect the contents from damage Mechanical
More informationPhoton-to-Photon CMOS Imager: Opto-Electronic 3D Integration
Photon-to-Photon CMOS Imager: Opto-Electronic 3D Integration Outline Key technologies for future CMOS imagers Bottlenecks for high speed imaging Our proposal Take home message Oct 12, 2017 Photon-to-Photon
More informationGLAST. Prototype Tracker Tower Construction Status
Prototype Tracker Tower Construction Status June 22, 1999 R.P. Johnson Santa Cruz Institute for Particle Physics University of California at Santa Cruz 1 1 11 2 3 5 4 Prototype Tracker Tower Configuration
More informationFABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag
FABRICATION OF CMOS INTEGRATED CIRCUITS Dr. Mohammed M. Farag Outline Overview of CMOS Fabrication Processes The CMOS Fabrication Process Flow Design Rules EE 432 VLSI Modeling and Design 2 CMOS Fabrication
More informationUpdate: Lambda project
Update: Lambda project Sabine Lange Detector Group DESY meeting, May 29-31, 2012 s1 Lambda project About Lambda: 2 x 6 3 chips (~28 x 85mm) high frame rate (8 read out lines, 2kHz readout) 10 gigabit Ethernet
More informationMonolithic 3D Integration using Standard Fab & Standard Transistors. Zvi Or-Bach CEO MonolithIC 3D Inc.
Monolithic 3D Integration using Standard Fab & Standard Transistors Zvi Or-Bach CEO MonolithIC 3D Inc. 3D Integration Through Silicon Via ( TSV ), Monolithic Increase integration Reduce interconnect total
More informationExpected feedback from 3D for SLHC Introduction. LHC 14 TeV pp collider at CERN start summer 2008
Introduction LHC 14 TeV pp collider at CERN start summer 2008 Gradual increase of luminosity up to L = 10 34 cm -2 s -1 in 2008-2011 SLHC - major increase of luminosity up to L = 10 35 cm -2 s -1 in 2016-2017
More informationPackaging for parallel optical interconnects with on-chip optical access
Packaging for parallel optical interconnects with on-chip optical access I. INTRODUCTION Parallel optical interconnects requires the integration of lasers and detectors directly on the CMOS chip. In the
More information3D SYSTEM INTEGRATION TECHNOLOGY CHOICES AND CHALLENGE ERIC BEYNE, ANTONIO LA MANNA
3D SYSTEM INTEGRATION TECHNOLOGY CHOICES AND CHALLENGE ERIC BEYNE, ANTONIO LA MANNA OUTLINE 3D Application Drivers and Roadmap 3D Stacked-IC Technology 3D System-on-Chip: Fine grain partitioning Conclusion
More informationEmbedded Power Dies for System-in-Package (SiP)
Embedded Power Dies for System-in-Package (SiP) D. Manessis, L. Boettcher, S. Karaszkiewicz, R.Patzelt, D. Schuetze, A. Podlasky, A. Ostmann Fraunhofer Institute for Reliability and Microintegration (IZM),
More informationCLEAN ROOM TECHNOLOGY
CLEAN ROOM TECHNOLOGY Justin Mathew Applied Electronics and Instrumentation College Of Engineering, Trivandrum April 28, 2015 Justin Mathew (CET) Clean Room Technology April 28, 2015 1 / 18 Overview 1
More informationThin n-in-p planar pixel modules for the ATLAS upgrade at HL-LHC
Thin n-in-p planar pixel modules for the ATLAS upgrade at HL-LHC A. Macchiolo, J. Beyer, A. La Rosa, R. Nisius, N. Savic Max-Planck-Institut für Physik, Munich 8 th International Workshop on Semiconductor
More information3D INTEGRATION, A SMART WAY TO ENHANCE PERFORMANCE. Leti Devices Workshop December 3, 2017
3D INTEGRATION, A SMART WAY TO ENHANCE PERFORMANCE OVERAL GOAL OF THIS TALK Hybrid bonding 3D sequential 3D VLSI technologies (3D VIA Pitch
More informationStacked Silicon Interconnect Technology (SSIT)
Stacked Silicon Interconnect Technology (SSIT) Suresh Ramalingam Xilinx Inc. MEPTEC, January 12, 2011 Agenda Background and Motivation Stacked Silicon Interconnect Technology Summary Background and Motivation
More informationMicroshutters Arrays for the JWST Near Infrared Spectrograph
Microshutters Arrays for the JWST Near Infrared Spectrograph S. H. Moseley *,a, R. Arendt a,b, R. A. Boucarut a, M. Jhabvala a, T. King a, G. Kletetschka a,c, A. S. Kutyrev a,b, M. Li a, S. Meyer a, D.
More informationBurn-in & Test Socket Workshop
Burn-in & Test Socket Workshop IEEE March 4-7, 2001 Hilton Mesa Pavilion Hotel Mesa, Arizona IEEE COMPUTER SOCIETY Sponsored By The IEEE Computer Society Test Technology Technical Council COPYRIGHT NOTICE
More informationFrom 3D Toolbox to 3D Integration: Examples of Successful 3D Applicative Demonstrators N.Sillon. CEA. All rights reserved
From 3D Toolbox to 3D Integration: Examples of Successful 3D Applicative Demonstrators N.Sillon Agenda Introduction 2,5D: Silicon Interposer 3DIC: Wide I/O Memory-On-Logic 3D Packaging: X-Ray sensor Conclusion
More informationBringing 3D Integration to Packaging Mainstream
Bringing 3D Integration to Packaging Mainstream Enabling a Microelectronic World MEPTEC Nov 2012 Choon Lee Technology HQ, Amkor Highlighted TSV in Packaging TSMC reveals plan for 3DIC design based on silicon
More informationProduction and Quality Assurance of Detector Modules for the LHCb Silicon Tracker
Production and Quality Assurance of Detector Modules for the LHCb Silicon Tracker Olaf Steinkamp for Dmytro Volyanskyy Physik-Institut der Universität Zürich 10th ICATPP Conference on Astroparticle, Particle,
More informationAdditional Slides for Lecture 17. EE 271 Lecture 17
Additional Slides for Lecture 17 Advantages/Disadvantages of Wire Bonding Pros Cost: cheapest packages use wire bonding Allows ready access to front side of die for probing Cons Relatively high inductance
More informationAT&S Company. Presentation. 3D Component Packaging. in Organic Substrate. Embedded Component. Mark Beesley IPC Apex 2012, San Diego.
3D Component Packaging AT&S Company in Organic Substrate Presentation Embedded Component Mark Beesley IPC Apex 2012, San Diego www.ats.net Austria Technologie & Systemtechnik Aktiengesellschaft Fabriksgasse13
More informationSMAFTI Package Technology Features Wide-Band and Large-Capacity Memory
SMAFTI Package Technology Features Wide-Band and Large-Capacity Memory KURITA Yoichiro, SOEJIMA Koji, KAWANO Masaya Abstract and NEC Corporation have jointly developed an ultra-compact system-in-package
More informationProduct Specifications
Product Specifications The ksa RateRat Pro is a turnkey, real-time, in-situ optical reflectance probe designed for deposition monitoring of semi-absorbent thin films. The RateRat Pro measures deposition
More informationSILICON PHOTONICS WAVEGUIDE AND ITS FIBER INTERCONNECT TECHNOLOGY. Jeong Hwan Song
SILICON PHOTONICS WAVEGUIDE AND ITS FIBER INTERCONNECT TECHNOLOGY Jeong Hwan Song CONTENTS Introduction of light waveguides Principals Types / materials Si photonics Interface design between optical fiber
More informationEUV Lithography and Overlay Control
YMS Magazine DECEMBER 2017 EUV Lithography and Overlay Control Efi Megged, Mark Wylie and Cathy Perry-Sullivan L A-Tencor Corporation One of the key parameters in IC fabrication is overlay the accuracy
More informationA 10kfps 32x32 Integrated Test Platform for Electrical Characterization of Imagers
A 10kfps 32x32 Integrated Test Platform for Imagers Intro Arch Pixel CMOS Results Conclusions 1/19 A 10kfps 32x32 Integrated Test Platform for Electrical Characterization of Imagers J.M. Margarit 1, L.
More informationMONOLITHIC NEAR INFRARED IMAGE SENSORS ENABLED BY QUANTUM DOT PHOTODETECTOR
MONOLITHIC NEAR INFRARED IMAGE SENSORS ENABLED BY QUANTUM DOT PHOTODETECTOR PAWEŁ E. MALINOWSKI, E. GEORGITZIKIS, J. MAES, M. MAMUN, O. ENZING, F. FRAZZICA, J.VAN OLMEN, P. DE MOOR, P. HEREMANS, Z. HENS,
More informationGLAST Silicon Microstrip Tracker Status
R.P. Johnson Santa Cruz Institute for Particle Physics University of California at Santa Cruz Mechanical Design Detector Procurement Work list for the Prototype Tracker Construction. ASIC Development Hybrids
More informationThe Cornerstone Project:
The Cornerstone Project: UK Silicon Photonics Fabrication Capability based on DUV Photolithography Dr Stevan Stanković University of Southampton Outline Introduction What is CORNERSTONE? What is offered?
More informationMEMS SENSOR FOR MEMS METROLOGY
MEMS SENSOR FOR MEMS METROLOGY IAB Presentation Byungki Kim, H Ali Razavi, F. Levent Degertekin, Thomas R. Kurfess 9/24/24 OUTLINE INTRODUCTION Motivation Contact/Noncontact measurement Optical interferometer
More informationEmbedded UTCP interposers for miniature smart sensors
Embedded UTCP interposers for miniature smart sensors T. Sterken 1,2, M. Op de Beeck 2, Tom Torfs 2, F. Vermeiren 1,2, C. Van Hoof 2, J. Vanfleteren 1,2 1 CMST (affiliated with Ugent and IMEC), Technologiepark
More information3D technology for Advanced Medical Devices Applications
3D technology for Advanced Medical Devices Applications By, Dr Pascal Couderc,Jerome Noiray, Dr Christian Val, Dr Nadia Boulay IMAPS MEDICAL WORKSHOP DECEMBER 4 & 5,2012 P.COUDERC 3D technology for Advanced
More informationPackage (1C) Young Won Lim 3/20/13
Copyright (c) 2011-2013 Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published
More informationPackage (1C) Young Won Lim 3/13/13
Copyright (c) 2011-2013 Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published
More informationPhotonics Integration in Si P Platform May 27 th Fiber to the Chip
Photonics Integration in Si P Platform May 27 th 2014 Fiber to the Chip Overview Introduction & Goal of Silicon Photonics Silicon Photonics Technology Wafer Level Optical Test Integration with Electronics
More informationThe Phase-2 ATLAS ITk Pixel Upgrade
The Phase-2 ATLAS ITk Pixel Upgrade T. Flick (University of Wuppertal) - on behalf of the ATLAS collaboration 14th Topical Seminar on Innovative Particle and Radiation Detectors () 03.-06. October 2016
More informationCMOS TECHNOLOGY- Chapter 2 in the Text
CMOS TECHOLOGY- Chapter 2 in the Text CMOS Technology- Chapter 2 We will describe a modern CMOS process flow. In the simplest CMOS technologies, we need to realize simply MOS and MOS transistors for circuits
More informationLITHOGRAPHY CHALLENGES FOR LEADING EDGE 3D PACKAGING APPLICATIONS
LITHOGRAPHY CHALLENGES FOR LEADING EDGE 3D PACKAGING APPLICATIONS Warren W. Flack, Manish Ranjan, Gareth Kenyon, Robert Hsieh Ultratech, Inc. 3050 Zanker Road, San Jose, CA 95134 USA mranjan@ultratech.com
More informationXinetics Deformable Mirror Technology 10 April 2003
Xinetics Deformable Mirror Technology 10 April 2003 Facility Vision & Roadmap Integrated Operations & Future Expansion 2 nd Floor Engr, Admin, & Special Mfg 60,000-sqft: COMPLETE 1 st Floor Manufacturing
More informationMinimizes reflection losses from UV - IR; Optional AR coatings & wedge windows are available.
Now Powered by LightField PyLoN:100 1340 x 100 The PyLoN :100 is a controllerless, cryogenically-cooled CCD camera designed for quantitative scientific spectroscopy applications demanding the highest possible
More informationDetector R&D at the LCFI Collaboration
LCFI Overview Detector R&D at the LCFI Collaboration (Bristol U, Oxford U, Lancaster U, Liverpool U, RAL) Konstantin Stefanov on behalf of the LCFI collaboration LCWS2005, Stanford, 18-22 March 2005 Introduction
More informationChip/Package/Board Design Flow
Chip/Package/Board Design Flow EM Simulation Advances in ADS 2011.10 1 EM Simulation Advances in ADS2011.10 Agilent EEsof Chip/Package/Board Design Flow 2 RF Chip/Package/Board Design Industry Trends Increasing
More informationFST s status on EUV Pellicle & Inspection System Development
FST s status on EUV Pellicle & Inspection System Development OCT.04, 2015 EUV Pellicle TWG @ Imec, nl. Donwon Park FST (Korea) http://www.fstc.co.kr FST Business Segments Division Pellicle TCU (Temperature
More informationWe are IntechOpen, the first native scientific publisher of Open Access books. International authors and editors. Our authors are among the TOP 1%
We are IntechOpen, the first native scientific publisher of Open Access books 3,350 108,000 1.7 M Open access books available International authors and editors Downloads Our authors are among the 151 Countries
More informationAUTOFOCUS SENSORS & MICROSCOPY AUTOMATION IR LASER SCANNING CONFOCAL MICROSCOPE IRLC DEEP SEE. Now See Deeper than ever before
AUTOFOCUS SENSORS & MICROSCOPY AUTOMATION IR LASER SCANNING CONFOCAL MICROSCOPE IRLC DEEP SEE Now See Deeper than ever before Review and inspection of non visible subsurface defects Non visible and subsurface
More informationGeneral Purpose, Low Noise NPN Silicon Bipolar Transistor. Technical Data AT AT-41533
General Purpose, Low Noise NPN Silicon Bipolar Transistor Technical Data AT-411 AT-433 Features General Purpose NPN Bipolar Transistor 9 MHz Performance: AT-411: 1 db NF,. db G A AT-433: 1 db NF, 14. db
More informationGETTING MORE FROM EVERY MEMBER OF THE LLS FAMILY
LLS RETROFIT Adding Process Capabilities Increasing Process Reliability Increasing System Throughput Extending System Lifetime Implementing Custom Solutions GETTING MORE FROM EVERY MEMBER OF THE LLS FAMILY
More informationApplications for Mapper technology Bert Jan Kampherbeek
Applications for Mapper technology Bert Jan Kampherbeek Co-founder & CEO Today s agenda Mapper technology Principles of operation Development status and performance Specification summary Mapper applications
More informationPIC design across platforms. Ronald Broeke Bright Photonics
PIC design across platforms Ronald Broeke Bright Photonics OUTLINE Introduction PIC applications & designs MPW Materials & platforms Design modules PICs in Phoxtrot Design House for Photonics ICs Custom
More informationAT-41511, AT General Purpose, Low Noise NPN Silicon Bipolar Transistors. Data Sheet. Description. Features. Pin Connections and Package Marking
AT-4111, AT-4133 General Purpose, Low Noise NPN Silicon Bipolar Transistors Data Sheet Description Avago s AT-4111 and AT-4133 are general purpose NPN bipolar transistors that offer excellent high frequency
More informationHigh Speed Optical Link Based on Integrated Silicon Photonics
High Speed Optical Link Based on Integrated Silicon Photonics Dr. Haisheng Rong Photonics Research Lab Intel Corporation www.intel.com/go/sp PKU, Summer School July 04, 2012 Agenda Motivation Electronic
More informationCARBON NANOTUBE FLAT PLATE BLACKBODY CALIBRATOR. John C. Fleming
CARBON NANOTUBE FLAT PLATE BLACKBODY CALIBRATOR John C. Fleming Ball Aerospace, jfleming@ball.com Sandra Collins, Beth Kelsic, Nathan Schwartz, David Osterman, Bevan Staple Ball Aerospace, scollins@ball.com
More informationHPS128-LT-S Hybrid pyroelectric linear array with 128 responsive elements and integrated CMOS multiplexer
HPS128-LT-S Hybrid pyroelectric linear array with 128 responsive elements and integrated CMOS multiplexer Description The pyroelectric linear array 128-LT is a hybrid detector with 128 responsive elements
More informationRalf K. Heilmann CAT-GS: Critical-Angle Transmission Grating Spectrometer January 27,
Ralf K. Heilmann CAT-GS: Critical-Angle Transmission Grating Spectrometer January 27, 2009 1 Overview of CAT-GS Mission requirements: Effective area > 1000 cm 2 (0.3 1 kev) Spectral resolution E/ΔE > 3000
More informationMulti-Die Packaging How Ready Are We?
Multi-Die Packaging How Ready Are We? Rich Rice ASE Group April 23 rd, 2015 Agenda ASE Brief Integration Drivers Multi-Chip Packaging 2.5D / 3D / SiP / SiM Design / Co-Design Challenges: an OSAT Perspective
More informationEECS 598: Integrating Emerging Technologies with Computer Architecture. Lecture 10: Three-Dimensional (3D) Integration
1 EECS 598: Integrating Emerging Technologies with Computer Architecture Lecture 10: Three-Dimensional (3D) Integration Instructor: Ron Dreslinski Winter 2016 University of Michigan 1 1 1 Announcements
More informationInspection of imprint templates Sematech Lithography Workshop May, 2008
Inspection of imprint templates Sematech Lithography Workshop May, 2008 Mark McCord, Tony DiBiase, Bo Magyulan Ian McMackin*, Joe Perez*, Doug Resnick* * Outline Electron beam inspection of templates Optical
More informationOptical Topography Measurement of Patterned Wafers
Optical Topography Measurement of Patterned Wafers Xavier Colonna de Lega and Peter de Groot Zygo Corporation, Laurel Brook Road, Middlefield CT 6455, USA xcolonna@zygo.com Abstract. We model the measurement
More information3D systems-on-chip. A clever partitioning of circuits to improve area, cost, power and performance. The 3D technology landscape
Edition April 2017 Semiconductor technology & processing 3D systems-on-chip A clever partitioning of circuits to improve area, cost, power and performance. In recent years, the technology of 3D integration
More information3D technology evolution to smart interposer and high density 3D ICs
3D technology evolution to smart interposer and high density 3D ICs Patrick Leduc, Jean Charbonnier, Nicolas Sillon, Séverine Chéramy, Yann Lamy, Gilles Simon CEA-Leti, Minatec Campus Why 3D integration?
More informationNIRvana: 640ST. Applications: Nanotube fluorescence, emission, absorption, non-destructive testing and singlet oxygen detection
Powered by LightField The NIRvana: 64ST from Princeton Instruments is the world s first scientific grade, deep-cooled, large format InGaAs camera for low-light scientific SWIR imaging and spectroscopy
More information반도체공정 - 김원정. Lattice constant (Å)
반도체물리 - 반도체공정 - 김원정 Semiconductors Lattice constant (Å) 1 PN junction Transistor 2 Integrated circuit Integrated circuit originally referred to a miniaturized electronic circuit consisting of semiconductor
More informationProgress of the Development of High Performance Removable Storage at InPhase Technologies for Application to Archival Storage
Progress of the Development of High Performance Removable Storage at InPhase Technologies for Application to Archival Storage William L. Wilson Ph.D, Chief Scientist, Founder InPhase Technologies Longmont,
More informationOpen access to photonic integration technologies
Open access to photonic integration technologies Academic and Industrial examples of photonic integrated circuits Katarzyna Ławniczuk k.lawniczuk@tue.nl What is photonic integration technology? multiple
More informationEndcap Modules for the ATLAS SemiConductor Tracker
Endcap Modules for the ATLAS SemiConductor Tracker RD3, Firenze, September 29 th, 23 Richard Nisius (MPI Munich) nisius@mppmu.mpg.de (For the ATLAS-SCT Collaboration) The plan of this presentation Introduction
More information2D nano PrintArray Product Data Sheet
NSCRIPTOR Product Data Sheet Dip Pen Nanolithography (DPN ) is the process of writing nanoscale patterns of molecular "ink" onto a sample substrate via a coated SPM tip. NanoInk s NSCRIPTOR DPN System
More informationSamsung K9GAG08U0M-PCB0 16 Gbit Multi-Level Cell (MLC) 51 nm Process Technology NAND Flash Memory
Samsung K9GAG08U0M-PCB0 16 Gbit Multi-Level Cell (MLC) 51 nm Process Technology NAND Flash Memory Structural Analysis with Additional Layout Feature Analysis For comments, questions, or more information
More information3D & Advanced Packaging
Tuesday, October 03, 2017 Company Overview March 12, 2015 3D & ADVANCED PACKAGING IS NOW WITHIN REACH WHAT IS NEXT LEVEL INTEGRATION? Next Level Integration blends high density packaging with advanced
More informationedram to the Rescue Why edram 1/3 Area 1/5 Power SER 2-3 Fit/Mbit vs 2k-5k for SRAM Smaller is faster What s Next?
edram to the Rescue Why edram 1/3 Area 1/5 Power SER 2-3 Fit/Mbit vs 2k-5k for SRAM Smaller is faster What s Next? 1 Integrating DRAM and Logic Integrate with Logic without impacting logic Performance,
More informationEasy integration into complex experimental setup
NIRvana: 64ST The NIRvana: 64ST from Princeton Instruments is the world s first scientific grade, deep-cooled, large format InGaAs camera for low-light scientific SWIR imaging and spectroscopy applications.
More informationTechSearch International, Inc.
Silicon Interposers: Ghost of the Past or a New Opportunity? Linda C. Matthew TechSearch International, Inc. www.techsearchinc.com Outline History of Silicon Carriers Thin film on silicon examples Multichip
More informationPRODUCTION OF ULTRA-FLAT SEMICONDUCTOR WAFER SUBSTRATES USING ADVANCED OPTICAL LENS POLISHING TECHNOLOGY
PRODUCTION OF ULTRA-FLAT SEMICONDUCTOR WAFER SUBSTRATES USING ADVANCED OPTICAL LENS POLISHING TECHNOLOGY / Slide 1 IQBAL (IZZY) BANSAL ASML HOLDING (NV) iqbalbansal@asml.com JANUARY 10, 2009
More informationSharp NC µm Pixel CCD Image Sensor
Sharp NC9610 1.75 µm Pixel CCD Image Sensor Imager Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology,
More informationPackaging of Selected Advanced Logic in 2x and 1x nodes. 1 I TechInsights
Packaging of Selected Advanced Logic in 2x and 1x nodes 1 I TechInsights Logic: LOGIC: Packaging of Selected Advanced Devices in 2x and 1x nodes Xilinx-Kintex 7XC 7 XC7K325T TSMC 28 nm HPL HKMG planar
More information9 rue Alfred Kastler - BP Nantes Cedex 3 - France Phone : +33 (0) website :
9 rue Alfred Kastler - BP 10748-44307 Nantes Cedex 3 - France Phone : +33 (0) 240 180 916 - email : info@systemplus.fr - website : www.systemplus.fr October 2011 - Version 1 Written by: Romain FRAUX DISCLAIMER
More informationWafer Level Packaging The Promise Evolves Dr. Thomas Di Stefano Centipede Systems, Inc. IWLPC 2008
Wafer Level Packaging The Promise Evolves Dr. Thomas Di Stefano Centipede Systems, Inc. IWLPC 2008 / DEVICE 1.E+03 1.E+02 1.E+01 1.E+00 1.E-01 1.E-02 1.E-03 1.E-04 1.E-05 1.E-06 1.E-07 Productivity Gains
More informationLow Current, High Performance NPN Silicon Bipolar Transistor. Technical Data AT AT-32033
Low Current, High Performance NPN Silicon Bipolar Transistor Technical Data AT-311 AT-333 Features High Performance Bipolar Transistor Optimized for Low Current, Low Voltage Operation 9 MHz Performance:
More informationOUTSTANDING PROPERTIES OF THE ESPROS CMOS/CCD TECHNOLOGY AND CONSEQUENCES FOR IMAGE SENSORS
OUTSTANDING PROPERTIES OF THE ESPROS CMOS/CCD TECHNOLOGY AND CONSEQUENCES FOR IMAGE SENSORS OECD CONFERENCE CENTER, PARIS, FRANCE / 8 10 FEBRUARY 2012 Martin Popp, Enrico Marchesi, Beat De Coi, Markus
More informationAdvancing high performance heterogeneous integration through die stacking
Advancing high performance heterogeneous integration through die stacking Suresh Ramalingam Senior Director, Advanced Packaging European 3D TSV Summit Jan 22 23, 2013 The First Wave of 3D ICs Perfecting
More informationNew capabilities of diffuser calibration lab at GSFC NASA to support remote sensing instrumentation
New capabilities of diffuser calibration lab at GSFC NASA to support remote sensing instrumentation Jinan Zeng1, Jim Butler2, and Jack Xiong2 1Fibertek Incorporation, 13605 Dulles Technology Dr., Herndon,
More informationNokia N90 (Toshiba ET8EA3-AS) 2.0 Megapixel CMOS Image Sensor Process Review
November 21, 2005 Nokia N90 (Toshiba ET8EA3-AS) 2.0 Megapixel CMOS Image Sensor Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning
More informationMLI INTRODUCTION GUIDE. copyright reserved 2012 MLI
MLI INTRODUCTION GUIDE Table of Contents MLI, the Company Introduction of MLI Why MLI MLI Test Equipments Pellicle Introduction Pellicle Film Transmission Pellicle Mounting Tool MLI Quality System 3 4
More informationAST3 Cameras, a Status Update
AST3 Cameras, a Status Update Astronomy & Astrophysics in Antarctica Aug. 18-21 Xi'an, China Richard Bredthauer, Greg Bredthauer, Kasey Boggs Semiconductor Technology Associates, Inc. 27122 Paseo Espada,
More informationIntroduction to Integrated Photonic Devices
Introduction to Integrated Photonic Devices Class: Integrated Photonic Devices Time: Wed. 1:10pm ~ 3:00pm. Fri. 10:10am ~ 11:00am Classroom: 資電 106 Lecturer: Prof. 李明昌 (Ming-Chang Lee) Block Diagram of
More informationPackaging and Integration Technologies for Silicon Photonics. Dr. Peter O Brien, Tyndall National Institute, Ireland.
Packaging and Integration Technologies for Silicon Photonics Dr. Peter O Brien, Tyndall National Institute, Ireland. Opportunities for Silicon Photonics Stress Sensors Active Optical Cable 300 mm Silicon
More informationBulk MEMS Layout 2017 Dr. Lynn Fuller, Casey Gonta, Patsy Cadareanu Webpage:
ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Bulk MEMS Layout 2017 Dr. Lynn Fuller, Casey Gonta, Patsy Cadareanu Webpage: http://people.rit.edu/lffeee 82 Lomb Memorial Drive Rochester,
More informationUltra-thin Capacitors for Enabling Miniaturized IoT Applications
Ultra-thin Capacitors for Enabling Miniaturized IoT Applications Fraunhofer Demo Day, Oct 8 th, 2015 Konrad Seidel, Fraunhofer IPMS-CNT 10/15/2015 1 CONTENT Why we need thin passive devices? Integration
More informationPost-Process Process CMOS Front End Engineering With Focused Ion Beams
Post-Process Process CMOS Front End Engineering With Focused Ion Beams A. Lugstein 1, W. Brezna 1, B. Goebel 2, L. Palmetshofer 3, and E. Bertagnolli 1 1) Vienna University of Technology, Floragasse 7,
More informationDoug Schramm a, Dale Bowles a, Martin Mastovich b, Paul C. Knutrud b, Anastasia Tyurina b ABSTRACT 1. INTRODUCTION
Algorithm Implementation and Techniques for Providing More Reliable Overlay Measurements and Better Tracking of the Shallow Trench Isolation (STI) Process Doug Schramm a, Dale Bowles a, Martin Mastovich
More information21 rue La Nouë Bras de Fer Nantes - France Phone : +33 (0) website :
21 rue La Nouë Bras de Fer - 44200 Nantes - France Phone : +33 (0) 240 180 916 - email : info@systemplus.fr - website : www.systemplus.fr August 2012- Version 1 Written by: Maher SAHMIMI DISCLAIMER : System
More informationPLANAR LIGHTWAVE CIRCUITS FOR USE IN ADVANCED OPTICAL INSTRUMENTATION
PLANAR LIGHTWAVE CIRCUITS FOR USE IN ADVANCED OPTICAL INSTRUMENTATION AN ENABLENCE ARTICLE WRITTEN BY DR. MATT PEARSON, VP TECHNOLOGY & ASHOK BALAKRISHNAN, DIRECTOR OF PRODUCT DEVELOPMENT PUBLISHED IN
More informationSWIR Vision Systems Acuros TM CQD TM SWIR Cameras. November 2018 SWIR VISION SYSTEM
SWIR Vision Systems Acuros TM CQD TM SWIR Cameras November 2018 SWIR VISION SYSTEM Introducing Quantum Dots for short-wave IR imaging! Acuros TM CQD TM films turn silicon ICs into infrared sensors Encapsulant
More information3D Detector Simulation with Synopsys TCAD
Journée de la simulation 17/6/2013 3D Detector Simulation with Synopsys TCAD V. Gkougkousis1,2, A. Lounis 1,2, N. Dinu 1, A. Bassalat 1,3 1. Laboratoire de L'accélérateur Linéaire 2. Université Paris-SUD
More informationTechnology and Manufacturing
Technology and Manufacturing Executive Vice President Field Trip 2006 - London, May 23rd Field Trip 2006 - London, May 23rd Technology Technology Development Centers and Main Programs CMOS Logic Platform
More informationElectronics Rapid advances in information technology has made possible the arrival of a full-scale ubiquitous information society where communication
Rapid advances in information technology has made possible the arrival of a full-scale ubiquitous information society where communication can be done freely anytime, anywhere, and with anyone. Hitachi
More informationSilicon. Where applications demand precise tolerances and optimum surface finish, discover the benefits of:
Silicon Where applications demand precise tolerances and optimum surface finish, discover the benefits of: Processing silicon by x-sectional polishing, delayering and planarisation Maximising repeatability
More informationTLS-Dicing for concentrator dies - a fast and clean technology. Hans-Ulrich Zühlke
TLS-Dicing for concentrator dies - a fast and clean technology Hans-Ulrich Zühlke TLS-Dicing with JENOPTIK-VOTAN Semi Contents Overview Jenoptik Principle of TLS-Technology TLS-Dicing the benefits at a
More informationThe Evolution of Thermal Imaging Cameras
170 Years of Continued Innovation The Evolution of Thermal Imaging Cameras The World s Finest Manufacturers of Temperature, Pressure & Humidity, Test and Calibration Instruments t May, 2007 What is a Thermal
More information