Zilog ZDS 1/25 HARDWARE USER MANUAL \ PRELIMINARY

Transcription

1 Zlog ZDS 1/25 HARDWARE USER MANUAL \ PRELIMINARY

2 , Revson 1 31 October 1978 Copyrght 1978 by Zlog, Inc. All rghts reserved. No part of ths publcaton may be reproduced, stored n any retreval system, or transmtted, n any form or by any means, electronc, mechancal, photocopyng, recordng or otherwse, wthout the pror wrtten permsson of Zlog. Zlog assumes no responsblty for the use of any crcutry other than crcutry emboded n a Zlog product. No other crcut patent lcenses are mpled.

3 ZDS 1/25 HARDWARE USER MANUAL PRELIMINARY

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5 TABLE OF CONTENTS SECTION PAGE 1.0 INTRODUCTION General Informaton Related Documents General Descrpton Operatng Modes INSTALLATION Unpackng Pre-Power Checks Console Connecton Power-Up Sequence MAJOR UNITS General Informaton Mcrocomputer System Central Processor Module (CPU) Dynamc Memory Module (DMM) Floppy Dsc Controller Module (FDC) Optonal I/O Modules Emulaton Subsystem Breakpont Module (BKPT) Real Tme Storage Module (RTSM) User Interface Module (UIM) Montor Module (MTM) PRINCIPLES OF OPERATION General Informaton Central Processor Module Z80 Mcroprocessor (Sheet 1) Reset Logc (Sheet 1) Clock Generator (Sheet 1) Control Buffer (Sheet 1) Data Buffer (Sheet 1) Address Buffer and Decoder (Sheets 1, 2 and 4) Z80-CTC (Counter Tmer Crcut) CTC Pn Descrpton CTC Programmng USART Operaton USART Sgnal Descrpton CTC Utlzaton USART Operaton USART Programmng 4-18

6 4.3 Dynamc Memory Module Control Logc (Sheet 1) Data Buffers (Sheet 2) Row Address Select (Sheet 1) Address Multplex (Sheet 2) Dynamc Memory Array (Sheet 4) Floppy Dsc Controller Module Dskette Format Data Format Recordng Format Floppy Dsc Controller Interfaces Floppy Controller - Detaled Operaton Data Bus Latches (Sheet 3) Data Converter (Sheet 2) Read Data Buffer (Sheet 2) CRC Logc (Sheet 7) Data Encoder (Sheet 3) Data Separator (Sheet 1) Read/Wrte Control (Sheet 4) System Control Interface (Sheet 3) Wat Generator (Sheet 5) Control Regster (Sheet 6) Control Interface (Sheet 6) Status Multplex (Sheet 2) Breakpont Module Control Logc Address Argument Regster (Sheet 2) Address Comparators (Sheet 2) Data Argument Regster (Sheet 1) Data Argument Compare Logc (Sheet 1) Data Mask Regster (Sheet 5) Data Mask Compare Logc (Sheet 5) Control Argument Regster (Sheet 3) Control Compare Logc (Sheet 3) Break/Sync Generator (Sheet 4) Realtme Storage Module Storage Array (Sheet 1 and 2) Address Latches (Sheet 1) Data Latches (Sheet 2) Control Decode (Sheet 3) Data Bus Drvers (Sheet 3) Storage Control Logc (Sheets 2, 3 and 4) 4-59

7 4.7 Mapper/ICE Module Address Decoder Memory Mapper (Sheet 2) Address Bus Drvers (Sheet 2) Output Control Bus (Sheet 1 and Input Control Bus (Sheet 1) Data Bus Buffers (Sheet 2) Clock Synchronzaton Logc (Sheet 1) External Memory External Clock 4.8 Montor Module Panel Interface (Sheet 1) Instructon Decoder (Sheet 3) Mode Change Logc (Sheet 1) NO-OP Generator (Sheet 3) Mode Select Logc (Sheet 2) System Status Buffer (Sheet 1) Port Address Decoder (Sheet 2) User Data Bus Control (Sheet 3) Console Interface Recevers/ Drvers (Sheet 4) 3) APPENDICES Appendx A CPU Schematcs (4 sheets) A-l Appendx B Appendx C Appendx D AppendxE Appendx F Appendx G Appendx H Appendx I Appendx J 64K Memory Module Schematcs (3 sheets) Floppy Dsk Controller Schematcs (7 sheets) Montor Schematcs (3 sheets) User Interface/Mapper (3 sheets) Breakpont Schematcs (5 sheets) Real Tme Storage Module Schematcs (4 sheets) PCB Locatons for ZDS-1/25 Backplane Defnton, ZDS-1/25 Pnout Charts B-l C-l D-l E-l F-l G-l H-l 1-1 J-l

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9 1.0 INTRODUCTION 1.1 General Informaton Ths manual descrbes the nstallaton and hardware operaton of the ZDS-1/25 Development Systems. It s dvded nto sectons to enable the user to quckly locate nformaton pertnent to the product's nstallaton, operaton and use. The sectons and ther contents are shown below. SECTION I - INTRODUCTION SECTION II - INSTALLATION SECTION III - MAJOR UNITS SECTION IV - PRINCIPLES OF OPERATION Descrbes the organzaton of the manual, related documents and functonal descrpton. Descrbes the hardware nstallaton and checkout of the system. Descrbes the functonal purpose and operaton of the varous sub asssembles n the unt Descrbes the detaled operaton of the unt as a system. 1". 2 Related Documents The followng lst of documents wll provde detaled nformaton to supplement ths manual. RIO Operatng System-User's Manual RIO Text Edtor-User's Manual RIO Assembler and Lnker-User's Manual ZDS-1/25, ZDS-1/40 PROM User's Manual Z80-CIB Hardware User's Manual Z80-ZDSP Hardware User's Manual Z80-PPB Hardware User's Manual Z80-PPB/16 Hardware User's Manual 1-1

10 1.3 General Descrpton The ZDS-1/25 Development System s a mcrocomputer system desgned to support all hardware and softwre development actvtes for the Z80-CPU. The system ncludes a sngle cabnet whch contans dual sngle-densty hard-sectored floppy dsk unts, emulaton nterface, real-tme storage module, breakpont module, memory module, console nterface module, montor module, DC power supples, nternal cablng and sngle card slot for opton expanson. Specfc features of the ZDS-1/25 Development System nclude: Z80-CPU wth 4k bytes dedcated statc RAM/ROM. RS-232 or current loop nterface supportng transmsson rates from baud. 60k bytes of dynamc RAM. Programmable hardware breakpont module. Programable real-tme event storage module. In-crcut emulaton nterface to user's prototype system. Memory mappng n blocks of 256 bytes. Dual sngle-densty hard-sectored floppy dsk drves and controller. Full operatng system software: -ROM-based debug software -Relocatable Macro Assenbler and Lnker -Text Edtor -Dsc Fle Management System Optonal nterfaces: -Auxlary Seral/Parallel Input/Output Board -Prnter Interface/Prom Programmer Interface -EPROM/Bpolar PROM Programmers -Parallel Interface Board 1-2

11 Optonal Perpherals character CRT termnal wth upper/lower case keyboard -120 character/second Matrx Prnter, bdrectonal wth forms length selector. Optonal Software: -Basc Interpreter, ncludng both bnary and BCD math. -FORTRAN IV based on ANSI 1966 standard. -PLZ programmng languages (Compler, Interpreter and hgh level assembler) 1.4 OPERATING MODES Because the Z80-CPU s shared by both the system and the user's prototype durng emulaton, two dstnct modes of operaton are provded for the user. These modes of operaton are clearly ndcated by the MONITOR and USER swtch/ndcators on the front of the system. MONITOR MODE: Ths s the normal operatng mode of the system when not usng the emulaton logc. In ths mode all system resources are allocated to the development system and the emulaton logc s dsabled. Whle runnng n ths mode the breakpont module s dsabled, and loadng of the breakpont module and the realtme storage parameters s enabled. The user memory n the prototype system may be accessed by the development system n part or as a whole dependng on the memory mapper confguraton USER MODE: Ths mode s used when runnng n-crcut emulaton and may be establshed n one to two fashons: (1) by pressng the USER button, or (2) by executng a Go command from the Debug envronment. In ths mode the Z80-CPU s dedcated to the emulaton logc and s used to execute user's program n a real tme mode. In order to accomplsh ths, certan system functons and emulaton functons must occur. These functons are lsted below: 1-3

12 Breakpont logc s enabled to compare address, data and control busses for equvalence. Breakpont parameters may not be loaded. Real Tme Storage Module s allowed to trace bus events. Real Tme Storage Module parameter loadng s dsabled. Enable data strobe for Real Tme Storage Modules. Enables Z80-CPU to see nterrupt, non-maskable nterrupt, wat, bus request and reset nputs from the user's system. Allows user's system to utlze blocks of or the entre development system memory, save FOOOH-FFFFH. Wrte protects the IK statc RAM scratch pad. 1-4

13 2.0 INSTALLATION 2.1 Unpackng Each ZDS-1/25 Development System s shpped n a padded shppng contaner for protecton. Upon recevng the system, place contaner n uprght poston, open contaner, remove top secton of packng materal, and vsually nspect the unt for damage. WARNING The approxmate weght of the unt s 65 Ibs; exercse cauton when removng unt from shppng contaner. Remove the unt from the bottom of the shppng contaner. Insure power cable and emulaton cable w/termnator are ncluded n the contaner. Remove foam pads from floppy dsk unts, and nspect openngs for foregn objects. Remove the two top cover retanng screws (reference Fg 2-3) from the rear of the unt, and remove the top-cover by movng t towards the rear and upward. Inspect the nsde of the unt for foregn objects, loose mechancal components, and to nsure all DC power supply connectons are secure. Check all pluggable components to be sure that they are securely seated on the PC boards. Check all PC boards to be sure that they are nstalled n ther correct slots (reference Fgure 2-1 for locatons). Check all I/O cable connectons to be sure that they are secure on the motherboard and the rear of the unt (reference Fgure 2-2) Replace top-cover and secure wth two screws, prevously removed. 2.2 PRE-POWER CHECKS The performance of the system can be affected by nose and/or transents enterng the system on the prmary power nput. Therefore, one of the followng nose solaton technques should be used. 2-1

14 DC DISCS OPTION J07 METOQRY J0G CPU J24 FICPfV DISC I^QNfTCR FIGURE 2 ~/ PC. BOARD UDCflT \OVS FLDPPV D»SC CABLE CDNSCUE AUXJL1ARV SERIPL PbQT PfU^vx 3-0*7 JMTERFACE RXOtfL C^>6L, n n n n n n n n n n JI3 JI4 JIS J16 J17 J18 J2Q J2! J2S" ^>

15 a. Power-lne sheldng may be utlzed, enclosng the nput power lnes n rgd condut or metallc sheldng, whch s connected to earth ground. b. Lne flters may be utlzed to reduce the ampltude of transents on the lne. GROUNDING The proper groundng of the system s extremely mportant, especally when connectng the emulaton cable to the user's prototype system. Inadequate groundng often causes ntermttent problems whch may be dffcult to solate. Also, nadequate groundng between the prototye and the development system may result n damage to the emulaton nterface and/or user's prototype. All zlog machne power cords contan an nsulated equpment ground wre (green, or green wth yellow strpe), whch s ndentcal n sze and nsulaton to the grounded and ungrounded supply conductors. Ths conductor connects the machne frame ground to a protectve ground on the nput power plug. WARNING An nsulated groundng conductor dentcal n sze and nsulaton to the grounded and ungrounded branch-crcut supply conductors, except that t s green or green wth one or more yellow strpes, s to be nstalled as part of the branchcrcut that supples the unt. Ths conductor must be connected at the servce equpment. Condut must not be used as the only groundng medum. PRIMARY INPUT POWER Pror to connectng the power cable between the nput power source and the system, the source must be checked for proper polarty, voltage and groundng. Cycles (+/- 1%:) Phase: 60HZ Sngle 50HZ Sngle Voltage (+/- 10%) Current: 110VAC 100/230 VAC Klovolt Amperes: 2-3

16 2.3 CONSOLE CONNECTION A sngle 25-pn female connector s provded at the rear of the unt for connectng a console drver (reference Fgure 2-3). The console devce may be any keyboard prnter or CRT dsplay devce employng an RS-232 or 20 ma. current loop nterface. Baud rates for the console may be from CAUTION The termnal connector on the rear of the system s shpped wth pns 5,6 and 8 wred hgh. Accordng to standard RS- 232 specfcatons, these pns are desgnated: Pn 5-Clear to Send Pn 6-Data Set Ready Pn 8-Carrer Detect These pns serve as TTY.RETURN lnes whch are pulled up to +12v through 200 ohms. The only pns used by the RS-232 nterface are: Pn 2-RS232 Data In Pn 3-RS232 Data Out Pn 7-RS232 Return Pns used by the current loops (teletype) Pn 10-TTY Data In Pn 16-TTY Data Out Pns 5,6,7,24-TTY IN Return Pn 17-TTY Out Return nterface are: After nsurng that correct pn connectons exst n the cable from the termnal, the cable may be connected to the termnal connector on the rear of the unt. 2.4 POWER UP SEQUENCE Apply power to termnal console devce and apply power to the ZDS-1/25 by actvatng the swtch on the rear of the unt. The MON ndcator should be llumnated and the fan should energze. 2-4

17 PUHCH pftpertap6 REAPER PRINTER USEP INTERFACE C*6l >* C P8> USER. INTERFACS. 32- CLOCX SYNC POWER POOLER cw -^ -> «, "" J- y.. '\ -, Zt)5-l /2S

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19 3.0 MAJOR UNITS 3.1 General Informaton The ZDS-1/25 contans the basc hardware of a mcrocomputer system, plus an emulaton subsystem used for real-tme hardware and software debuggng (reference Fgure 3-1). The varous modules that comprse the system wll be descrbed functonally, concentratng on ther nter-relatonshp and the role they perform n the overall system. For detaled operaton of each module, reference Secton 4.0 Prncples of Operaton. 3.2 Mcrocomputer System The modules that compose the mcrocomputer system are the Central Processor Module, Dynamc Memory Module, Floppy Dsk Controller Module, and the Optonal I/O Modules(s). These are descrbed n the followng text wth the excepton of the I/O Modules whch are descrbed n seperate manuals (reference Secton 1 for manual ttle and number) Central Processor Module (CPU) The Central Processor Module provdes the major control for the system usng the Z80-CPU. Resdent on the CPU module s the 3K Montor PROMs whch serve to control all debug and emulaton actvty along wth smple I/O drvers for the console and floppy dsk nterface. A IK byte statc RAM memory s provded to be used as a "scratch pad" for the 3K montor. All Z80-CPU sgnals are buffered on the board provdng nterface to the nternal address, data and control busses. Decodng of address sgnals provdes page and card selecct sgnals used by on board PROM/RAM and the off-board Dynamc Memory Module. The page and card selecton forces the 3K Montor and IK statc RAM to appear at address FOOO-FFFFH whle the system s n MONITOR mode. Ths feature allows the user to create and debug programs whch are located at any address from 0000-EFFFH. The CPU Card also provdes the system wth a USART to enable asynchronous nterface wth the system console devce. Baud rate synchronzaton wth the console devce s automatc and rates from Baud are supported. Lke the Floppy Dsk Controller Module, the actual ntellgence for ths module resdes n the 3K PROM Montor. Also provded s a fourchannel counter-tmer crcut, Z80-CTC, whch s used partally by the system and may be also controlled by the user. 3-1

20 3.2.2 Dynamc Memory Module (DMM) A sngle Dymanc Memory Module s provded n the system; t contans a maxmum of 60K bytes of storage when 16Kxl Dynamc RAM components are employed. All refresh tmng sgnals are generated on board and are trggered by the refresh sgnal from the CPU module. Jumpers on the board allow use of ether 16K or 4K memory components by controllng selected address lnes receved from the CPU module Floppy Dsk Controller Module (FDC) The Floppy Dsk Controller Module provdes an nterface between the system and two sngle-densty, sngle-sded, hard-sectored floppy dsk unts. Actual ntellgence, whch s requred by the controller, s contaned n the 3K Montor PROM's located on the CPU module. The controller serves as a temporary data buffer, nterface to the dsks, data modulator, data separator and CRC generator and checker Optonal I/O Modules Optonal card slots (J8 and J9) are provded for I/O expanson. Any one of the ZDS-1 Seres opton boards may be nstalled n one of these slots wthout modfcatons to the motherboard wrng. For detals regardng these optons reference the approprate manual lsted n Secton EMULATION SUBSYSTEM A group of modules comprse a specalzed subsystem wthn the ZDS-1/25. Its purpose s to montor and control the nterface between the ZDS-1/25 and the user's prototype whle performng n-crcut emulaton. Ths subsystem s composed of the followng modules descrbed n subsequent subparagraphs below. Breakpont Module Real Tme Storage Module User Interface Module Montor Module Breakpont Module (BKPT) The Breakpont Module provdes the user wth a means to termnate executon of a program when specfed condtons of the address, data or control bus occur. Ths feature s 3-2

21 most useful when debuggng programs or hardware that run n real-tme. The breakpont allows real-tme executon of a program untl the selected event occurs, at whch tme one of two events may occur: frst, the user may wsh to stop program executon or break on the event so that CPU regsters, memory or the real-tme storage module may be examned; second, the user may wsh to generate a sync pulse on the occurrance of the event to trgger external test equpment to montor the event n hs own hardware. Ether of these can be accomplshed easly by enterng the desred parameter from the system console. The Breakpont Module s loaded (wth the parameters entered va the system console) by the 3K Montor PROM. These parameters, called "arguments," may be any one or a combnaton of the followng: CONTROL ARGUMENTS: - Ml Op Code Fetch - MR Memory Read - MW Memory Wrte - PR Port (I/O) Read - PW Port (I/O) Wrte ADDRESS ARGUMENTS - A Memory Address - P Port (I/O) Address DATA ARGUMENT - D Data Byte - M Data Mask Real Tme Storage Module (RTSM) The Real Tme Storage Module provdes a means for the system to store selected bus transactons whle executng a program. Ths feature allows the system to trace address, data and control bus lnes n real tme executon of the user's program to provde a hstory of the most current 256 selected events. The user may dsplay the contents of the hstory on the system console to analyze the executon of the program under test. Control of the RTSM s provded by the emulaton subsystem, (whle executng the user's program) to enable real-tme storage of bus actvty. Parameter loadng and dsplay of the hstory s controlled by the 3K PROM Montor on the CPU module. The user may select any one or a combnaton of the trace parameters to trace: 3-3

22 Memory Reads Memory Wrtes Port (I/O) Reads Port (I/O) Wrtes All Read Operatons All Wrte Operatons All Port Operatons All Memory Operatons All Operatons ' User Interface Module (UIM or Mapper/ICE) The User Interface Module provdes the electrcal nterface between the emulaton subsystem and the user's prototype system so that n-crcut emulaton may occur. Connecton between the ZDS-1/25 and the user's prototype s acheved by a three-foot cable and termnaton block. The M/ICE contans recevers, drvers and nterface controls, as well as a memory mapper. Memory mappng allows the user's prototype system to borrow blocks of development system memory, each block beng composed of 256 bytes. Typcally, ths feature s used when the user s developng software that wll eventually resde n PROM on the prototype. By means of the mapper, the user may borrow blocks of memory from the development system memory as though t were resdent n hs prototype wthout any degradaton n system speed. The mapper s loaded to the confguraton desred by the" user by executng a dsk resdent program called "MAPPER." Once the map s loaded, the user may enable the map or dsable the map usng one of the methods shown below. Control of bus access s provded by Swtch One (SI) on the rear of the unt. TO ENABLE MAPPER LOGIC: Place MEM select swtch (SI) to map EXT ( sw down) and ssue a port wrte to EEH wth data bt Dl low. TO DISABLE MAPPER LOGIC (use one of the followng) : Place MEM select swtch (SI) to nternal MEM ( sw up) Executon of Port Wrte to I/O Port EEH wth data bt Dl hgh Operator depresses the WAIT button (System Reset) Also provded on the M/ICE s clock selecton logc, whch selects the clock source for the Z80-CPU whle runnng emulatons,.e., nternal (2.5 MHZ) or external (varable). Clock selecton s controlled by S2 on the rear of the unt; UP for nternal, drvng clock, DOWN for external clock. 3-4

23 3.3.4 Montor Module (MON.25) Although the montor module provdes several dskrete functons for the system, ts prmary purpose s to provde varous strobes and controls used by the emulaton subsystem. The dskrete functons provded by the montor are as follows: Console Electrcal Interface - provdes recever and drver crcuts whch allow use of standard RS-232 or current loop devce as the system console. The method of nterface determnes whch recevers and drvers are employed. Operator Panel Interface - provdes debounce crcutry for the MON, USER, WAIT, SI and S2 swtches; provdes lamp drvers for MON, WAIT, HALT and USER ndcators; provdes swtch synchronzaton logc between modes and system logc functons to prevent undesrable dsrupton of system tmng System I/O Port Decode - provdes decodng logc for Z80-CPU address bts AO-A7 to select system address ports of FO-FFH and to prevent user's prototype from addressng the system I/O ports EO-FFH. The remander of the logc on the montor s used to generate control sgnals used by the emulaton subsystem to sample data, address and control busses, or to provde control of the nterface to the user's prototype and synchronze the emulaton subsystem to the user suppled clock f external clock s selected. 3-5

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25 4.0 PRINCIPLES OF OPERATION 4.1 GENERAL INFORMATION The followng dscusson descrbes the detaled operaton of each p.c. board used n the ZDS-1/25 Development System. A block dagram of each board s provded, showng the varous functonal unts on the board, whch are then related to a specfc logc Sheet number for further crcut clarfcaton. 4.2 CENTRAL PROCESSOR MODULE The processor card contans a Z80-CPU, Z80 CTC and USART for console nterface, plus 3K of PROM and IK of statc RAM for controllng the debug envronment. System PHI s derved from a MHZ oscllator s provded to the floppy dsk controller for synchronous data separaton. The CPU bus s fully buffered to support stand alone operaton wth full memory and I/O complments. The relatonshp of these elements s represented n Fgure Z80 Mcroprocessor (Sheet 1) system The Z80-CPU serves as the control for the system. It s shared by both the system (MONITOR MODE) and the emulaton subsystem (USER MODE). The Z80-CPU does not dfferentate between executng programs n USER or MONITOR MODES as a consequence the surroundng logc of the mcrocomputer system and emulaton subsystem must make the dstncton. The processor operates n a normal fashon fetchng and executng nstructons from storage ether PROM or RAM as descrbed n the Z80-CPU Techncal Manual Reset Logc (Sheet 1) The Z80-CPU may be reset by one of several condtons, reset operaton wll result n the followng: N Ths Program Counter wll be reset (OOOOH) Interrupt Enable flp-flop wll be reset, dsablng all maskable nterrupts. Interrupt Page Address Regster (I) wll be cleared. Memory Refresh Regster (R) wll be cleared. Interrupt Mode 0 wll be establshed. Address and data bus go to a hgh mpedance state whle RESET s actve (logc 0). Also, all control output sgnals go to ther nactve state. < 4-1

26 I 4 k- w 4 1 H I vva 4-2

27 Reset logc crcutry s trggered by one of the followng events: RESET SW (Reset Swtch) occurs when the operator depresses the momentary swtch (WAIT) on the front panel of the unt. Debounce crcutry s provded (logc Sheet 1) va C3 and R2 on the CPU board. RESTART s generated from the mode change logc on the monter module and s the result of one of the followng events: BREAK sgnal from the Breakpont Module, ndcatng a comparson between the argument regsters and the bus actvty. Swtchng between MONITOR and USER modes, ether by operator pressng MON or USER buttons, or a software generated mode change from the 3K PROM Debug frmware. SYS RESET does not drectly reset the Z80-CPU, but nstead generates the RESTART sgnal prevously descrbed. The SYS RESET sgnal may be generated by (1) power-on clear sgnal, (2) software reset commands, or (3) mode change from MONITOR to USER or vsa versa. Two outputs are generated by the reset logc; one s appled drectly to the Z80-CPU as a reset whle the second output, POWER ON CLR, s appled to the User Interface Module, Montor Module and the Opton card slot as a reset CLOCK GENERATOR (Sheet 1) The Z80 CPU bus buffers are shown on Sheet One of the schematcs. System PHI s generated by hybrd oscllator A29. Counter A22 produces the 2.46 MHz system clock as well as half PHI for baud rate tmng. The dscrete crcut oscllator s controlled by a MHz crystal and s used by the floppy controller's synchronous data separator. Data bus buffer A31 nterfaces the CPU to the system bus (backplane) and drves toward the CPU durng Ml or Read cycles. Buffers A26 and A23 drve the system address bus. A32 drves outbound control sgnals such as Ml, IORQ, RD, etc., whle A27 receves user provded nputs, e.g., INT, NMI, RESET, etc. In actualty, system PHI s provded by the User Interface Module, whch determnes the approprate development system clock. Zlog clock drver A25 provdes a MOS compatble clock source for the LSI devces. 4-3

28 4.2.4 CONTROL BUFFER (Sheet 2) Sheet 2 of the schematcs detal the PROM/RAM mplementaton and the bus control logc for both A31 and A16 bus buffers. Chp selects for A17-A19 and A13, A14 occur when PROM addresses are decoded by Sheet 3 logc. These decoded addresses, along wth I/O and nterrupt requests from perpherals A20 and A21 (Sheet 4) cause bus drver A16 to drve the system data bus toward the CPU. Automatc baud rate tmng s acqured through trstate drver A28 and data bt DO, through Port FFH. The Development System 3K Montor s ntended to provde the basc debuggng commands, basc Input/Output drver frmware and bootstrap porton of a floppy dsk-based operatng system. The operaton of ths frmware s descrbed n the ZDS-1/25, 1/40 PROM MANUAL DATA BUFFER (Sheet 3) Sheet 3 depcts the address decodng assgnments for the followng: PROM Frmware FOOO-FFFF HEX Dynamc Memory 0-EFFF HEX System Ports FO-FF HEX Adder A34 translates montor mode addresses from 00 to FOOO placng memory select decoder A33 n the user address space (RAM at zero). Gates A7 and All generate the page 15 address enable whch allows montor mode PROM accesses. System I/O ports are decoded by the logc of A2 and A ADDRESS BUFFER AND DECODER (Sheets 1, 2, and 4) Sheet 4 contans the perpherals found on the CPU2 card. The console nterface s mplemented by way of USART A21, and CTC provdes nterrupt capablty for the floppy dsk nterface and the USART status lnes. Jumper El and E2 allow recever nterrupts from the USART. Flop flop A8 provdes a square-wave baud-rate clock source to the USART. 4-4

29 - odo </>*/>*/) co I A V N V tn I ^03 I 5 2 a a o a a: a UJ -<r a OC UJ f ft s ^ scj cvj CT3 UL (H

30 4.2.7 Z80-CTC (Counter Tmer Crcut) CTC Pn Descrpton DO-D7 Z80-CPU Data Bus (b-drectonal, tr-state). Ths bus s used to transfer all data and command words between the Z80-CPU and the Z80-CTC. There are 8 bts on ths bus, of whch DO s the least sgnfcant. CS1-CSO Channel Select (nput, actve hgh) These pns form a 2-bt bnary address code for selectng one of the four ndependent CTC channels for an I/O wrte or read. (See truth table below.) CS1 CSO ChO 0 0 Ch 0 1 Ch2 1 0 Ch3 1 1 CE- Chp Enable (nput, actve low) A low level on ths pn enables the CTC to accept control words, nterrupt vectors, or tme constant data words from the Z80 data bus durng an I/O wrte cycle, or to transmt the contents of the down counter to the CPU durng an I/O ready cycle. In most applcatons, ths sgnal s decoded from the 8 least sgnfcant bts of the address bus for any of the four I/O port addresses that are mapped to the four counter/tmer channels. Clock (ph) System Clock (nput) Ths sngle-phase clock s used by the CTC to synchronze certan sgnals nternally. 4-6

31 Machne Cycle One Sgnal from CPU (nput, actve low) When Ml- s actve and the RD- sgnal s actve, the CPU s fetchng an nstructon from memory. When Ml- s actve and the IORQ- sgnal s actve, the CPU s acknowledgng an nterrupt, alertng the CTC to place an nterrupt vector on the Z80 data bus f t has dasy chan prorty and one of ts channels has requested an nterrupt. M- IORQ- Input/Output Request from CPU (nput, actve low) The IORQ- sgnal s used n conjuncton wth the CE- and RDsgnals to transfer data and channel control words between the Z80-CPU and the CTC. Durng a CTC wrte cycle, IORQ- and CE- must be true and RD- false. The CTC does not receve a specfc wrte sgnal, nstead generatng ts own nternally from the nverse of a vald RD- sgnal. In a CTC read cycle, IORQ-, CE-, and RD- must be actve to place the contents of the down counter on the Z80 data bus. If IORQ- and Ml- are both true, the CPU s acknowledgng an nterrupt request, and the hghest-prorty nterruptng channel wll place ts nterrupt vector on the Z80 data bus. RD- Read Cycle Status from the CPU (nput, actve low) The RD- sgnal s used n conjuncton wth the IORQ- and CEsgnals to transfer data and channel control words between the Z80-CPU and the CTC. Durng a CTC wrte cycle, IORQ- and CE- must be true and RD- false. The CTC does not receve a specfc wrte sgnal, nstead generatng ts own nternally from the nverse of a vald RD- sgnal. In a CTC read cycle, IORQ-, CE-, and RD- must be actve to place the contents of the down counter on the Z80 data bus. IEI Interrupt Enable In (nput, actve hgh) Ths sgnal s used to help form a system-wde nterrupt dasy chan wh^h establshes prortes when more than cne perpheral devce n the system has nterruptng capablty. A hgh level on ths pn ndcates that no other nterruptng devces of hgher prorty n the dasy chan are beng 4-7

32 servced by the Z80-CPU. IEO Interrupt Enable Out (output, actve hgh) The IEO sgnal, n conjuncton wth IEI, s used to form a system-wde nterrupt prorty dasy chan. IEO s hgh only f IEI s hgh and the CPU s not servcng an nterrupt from any CTC channel. Thus, ths sgnal blocks lower prorty devces from nterruptng whle a hgher prorty nterruptng devce s beng servced by the CPU. Interrupt Request (output, open dran, actve low) Ths sgnal goes true when any CTC channel whch has been programmed to enable nterrupts has a zero-count condton n ts down counter. INT- RESET- Reset (nput, actve low) Ths sgnal stops all channels from countng and resets channel nterrupt enable bts n all control regsters, thereby dsablng CTC-generated nterrupts. The ZC/TO and INT- outputs go to ther nactve states, IEO reflects IEI, and the CTC's data bus output drvers go to the hgh mpedance state. CLK/TRG3-CLK/TRGO External Clock/Tmer Trgger (nput, user-selectable actve hgh or low) There are four CLK/TRG pns, correspondng to the four ndependent CTC channels. In the counter mode, every actve edge on ths pn decrements the down counter. In the tmer mode, an actve edge on ths pn ntates the tmng functon. The user may select the actve edge to be ether rsng or fallng. ZC/T02-C/TOO Zero Count/Tmeout (output, actve hgh) There are three ZC/TO pns, correspondng to CTC channels 2 4-8

33 through 0. (Due to package pn lmtatons, channel 3 has no ZC/TO pn.) In ether counter mode or tmer mode, when the down counter decrements to zero, an actve hgh gong pulse appears at ths pn CTC Programmng Before a Z80-CTC channel can begn countng or tmng operatons, a channel control word and a tme constant data word must be wrtten to t by the CPU. These words wll be stored n the channel control regster and the tme constant regster of that channel. In addton, f any of the four channels have been programmed wth bt 7 of ther channel control words to enable nterrupts, an nterrupt vector must be wrtten to the approprate regster n the CTC. Due to automatc features n the nterrupt control logc, one pre-programmed nterrupt vector suffces for all four channels. Loadng the Channel Control Regster To load a channel control word, the CPU performs a normal I/O wrte sequence to the port address correspondng to the CTC channel. Two CTC nput pns, namely CSO and CS1, are used to form a 2-bt bnary address to select one of four channels wthn the devce. In many system archtectures, these two nput pns are connected to address bus lnes AO and Al, respectvely, so that the four channels n a CTC devce wll occupy contguous I/O port addresses. A word wrtten to a CTC channel wll be nterpreted as a channel control word, and loaded nto the channel control regster, wth bt 0 beng a logc 1. The other seven bts of ths word select operatng modes and condtons as ndcated n the dagram below. Followng the dagram, the meanng of each bt wll be dscussed n detal. D7 D6 D5 D4 D3 D2 Dl DO Interrupt Enable Mode Range* Slope Trgger* Load Tme Constant Reset 1 * Used n tmer mode only Bt 7=1 The channel s enabled to generate an nterrupt request sequence every tme the down counter reaches a zero-count 4-9

34 condton. To set ths bt to 1 n any of the four channel control regsters necesstates that an nterrupt vector also be wrtten to the CTC before operaton begns. Channel nterrupts may be programmed n ether counter mode or tmer mode. If an updated channel control word s wrtten to a channel already n operaton wth bt 7 set, the nterrupt enable selecton wll not be retroactve to a precedng zero-count condton. Bt 7=0 Channel nterrupts dsabled. Bt 6=1 Counter mode selected. The down counter s decremented by each trggerng edge of the external clock (CLK/TRG) nput. The prescaler s not used. Bt 6=0 Tmer mode selected. The prescaler s clocked by the system clock, and the output of the prescaler n turn, clocks the down counter. The output of the down counter (the channel's ZC/TO output) s a unform pulse tran of perods gven by the product t * P * TC where t s the perod of system clock, P s the prescaler factor of 16 or 256, and TC s the tme constant data word. Bt 5=1 (Defned for tmer mode only.) Prescaler factor s 256. Bt 5=0 (Defned for tmer mode only.) Prescaler factor s 16. Bt 4=1 Tmer mode - postve edge trgger starts tmer operaton. Counter mode - postve edge decrements the down counter. Bt 4=0 Tmer mode - negatve edge trgger starts tmer operaton. Counter mode - negatve edge decrements the down counter. 4-10

35 Bt 3=1 Tmer mode only - external trgger s vald for startng tmer operaton after rsng edge of T of the machne cycle followng the one that loads the tme constant. The prescaler s decremented two clock cycles later f the setup tme s met, otherwse, three clock cycles. Bt 3=0 Tmer mode only - tmer begns operaton on the rsng edge of T of the machne cycle followng the one that loads the tme constant. Bt 2=1 The tme constant data word for the tme constant regster wll be the next word wrtten to ths channel. If an updated channel control word and tme constant data word are wrtten to a channel whle t s already n operaton, the down counter wll contnue decrementng to zero before the new tme constant s loaded nto t. Bt 2=0 No tme constant data word for the tme constant regster should be expected to follow. To program bt 2 to ths state mples that ths channel control word s ntended to update the status of a channel already n operaton, snce a channel wll not operate wthout a correctly programmed data word n the tme constant regster, and a set bt 2 n ths channel control word provdes the only way of wrtng to the tme constant regster. Bt 1=1 Reset channel. Channel stops countng or tmng. Ths s not a stored condton. Upon wrtng nto ths bt, a reset pulse dscontnues current channel operaton, however, none of the bts n the channel control regster are changed. If both bt 2=1 and bt 1=1, the channel wll resume operaton upon loadng a tme constant. Bt 1=0 Channel contnues current operaton. A channel may not begn operaton n ether tmer mode or counter mode unless a tme constant data word s wrtten nto 4-11

36 the tme constant regster by the CPU. Ths data word wll be expected on the next I/O wrte to ths channel followng the I/O wrte of the channel control word, provded bt 2 of the channel control word s set. The tme constant data word may be any nteger value n the range If all eght bts n ths word are zero, t s nterpreted as 256. If a tme constant data word s loaded to a channel already n operaton, the down counter wll contnue decrementng to zero before the new tme constant s loaded from the tme constant regster to the down counter. Tme Constant Regster D7 D6 D5 D4 D3 D2 Dl DO TC7 TC6 TC5 TC4 TC3 TC2 TC2 TCO MSB LSB The Z80-CTC has been desgned to operate wth the Z80-CPU programmed for mode 2 nterrupt response. Under the requrements of ths mode, when a CTC channel requests an nterrupt and s acknowledged, a 16-bt ponter must be formed to obtan a correspondng nterrupt servce routne startng address from a table n memory. The upper 8 bts of ths ponter are provded by the CPU's I regster, and the lower 8 bts of the ponter are provded by the CTC n the form of an nterrupt vector unque to the partcular channel that requested the nterrupt. MODE 2 INTERRUPT OPERATION INTERRUPT SERVICE ROUTINE STARTING ADDRESS TABLE LOW ORDER HIGH ORDER Desred startng address ponted to by: I REG CONTENTS 7 BITS FROM PERIPHERAL 0 The hgh order 5 bts of ths nterrupt vector must be wrtten to the CTC n advance as part of the ntal programmng sequence. To do so, the CPU must wrte to the I/O port addresses correspondng to the CTC channel 0, just as t would f a channel control word were beng wrtten to that channel, except that bt 3 of the word beng wrtten must contan a 0. (As explaned above n Secton 3.1, f bt 0 of a word wrtten to a channel were set to 2, the word would be nterpreted as a channel control word, so a 0 n bt 4-12

37 0 sgnals the CTC to load the ncomng word nto the nterrupt vector regster.) Bts 1 and 2, however, are not used when loadng ths vector. At the tme when the nterruptng channel must place the nterrupt vector on the Z80 data bus, the nterrupt control logc of the CTC automatcally supples a bnary code n bts 1 and 2 dentfyng whch of the four CTC channels s to be servced Channel 2 - Baud Rate Generaton Ths channel may be operated n ether counter or tmer mode and s trggered or clocked by the output of A4-pn 9. Once the counter decrements to zero, the ZC2 output goes actve (hgh) to clock the second stage of A4 whose output provdes the transmt and receve clocks to the USART. Channel 3 - USART Transmt Interrupt Generator Ths channel allows the USART to have nterrupt capablty wth the system. Ths channel wll generate an nterrupt upon recevng a TxRDY sgnal from the USART USART Operaton USART Sgnal Descrpton Data Bus (DO-D7) Ths tree-state, 8-bt bus s used for nformaton exchange between the USART and the host processor. Data, controk, andd stat6us bytes are exchanged upon executon of nput and output nstructons from the Z80. Reset (RST) The USART wll assume an dle sstate when a hgh level s appled to the reset nput. When the reset s returned low, the USART wll reman n the dle state untl t receves a new mode control nstructon. Clock (CLK) Ths nput s used for nternal tmng wthn the USART. It does not control the transmt or rec3eve rate. However, t should be at least 30 tmes the reeceve or transmt rate n the synchronous mode and 4.5 tmes the receve or trasnmt rates n the asynchronous mode. The CLK frequency s also restrcted by both an upper and a lower bound. 4-13

38 INTERRUPT VECTOR REGISTER D7 D6 D5 D4 4 D3 vs '/y/y/y/ D2 Dl DO '/M V7 V6 V5 V t \. SupplecTby User 0 ^ 0 Channel 0 (hghest prorty) 0 1 Channel Channel Channel 3 (lowest prorty) CTC Utlzaton <// Automatcally nserted ///! bv Z80-CTC All four channels of the Z80-CTC are used by the system for varous tmng functons. The channels used and ther purpose are shown below: Channel 0 - Sector Counter Ths channel s operated n counter mode and s used as a Sector Counter for the Floppy Dsk Controller. Interrupts are used wth ths channel to flag software as to when the approprate number of sector pulses have been receved from the dsk so that the heads may be loaded. Ths counter s ncremented by the sgnal, INDX, from the Flopppy Dsk Controller Module. Channel 1 - Bt Measurement Ths channel s operated n tmer mode and s trggered by the RCUR OUT sgnal from the Seral Latches on the CPU module. The output of the channel (ZC1) becomes RCV CLK whch s routed to the CPU module to clock the RCVR OUT sgnal nto the Seral Latches. Control/Data (C/D) Durng a read operaton, f ths nput s at a hgh level, the status by e wll be read, and f t s at a lew level/ the receve data wll be read by the processor. When a wrte operaton s beng performed, ths nput wll ndcate to the USART that the bus nformaton beng wrtten s a command f 4-14

39 C/D s hgh and data f C/D s low. C/D- RD- WR- CS X Read (RD-) X X USART DATA >DATA BUS DATA BUS >USART DATA USART STATUS >DATA BUS DATA BUS >USART COMMAND DATA BUS >3-STATE Ths actve low nput enables data or status to be transferred from the USART to the Z80. Wrte (WR-) Ths actve transferred low nput enables to the USART from data or control to be the Z80. Chp Select (CS-) Ths actve low nput enables the processor to access the USART for an I/O operaton. When CS- s hgh, the data bus output s n the hgh mpedance state. Data Set Ready (DSR-) Ths s a general-purpose nput sgnal and forms part of the status byte that may be read by the processor. DSR- s generally used as a response to DTR by the modem to ndcate that t s ready. The sgnal acts only as a flag and does not control any nternal logc. Data Termnal Ready (DTR-) Ths output sgnal reflects the condton of bt 1 n the command byte from the Z80. The DTR sgnal s commonly used for data termnal ready or rate select n modem control. Clear to Send (CTS-) Ths s a general-purpose nput sgnal used to enable the USART to transmt data f the TxEN bt n the command byte s a one. CTS- s generally used as a response to RTS- by a modem to ndcate that transmsson may begn. Desgners not usng CTS- n ther systems should remember to te t low so that USART data transmsson wll not be dsabled. 4-15

40 Request to Send (RTS-) Ths output sgnal reflects the condton of bt 5 n the command byte from the Z80. The RTS- sgnal s commonly used to ntate a data transmsson by requestng the modem to prepare to send. Transmt Data (TxD) Data from the data bus s converted to a seral format wth approprate sync, start/stop, and party nformaton nserted nto the data stream. Ths bt stream s then transmtted to the TxD output. Transmtter Ready (TR) The TR output sgnal goes hgh when data n the transmt data buffer has been shfted nto the transmtter secton allowng the transmt data buffer to accept the next byte from the processor. TR wll be reset when nformaton s wrtten nto the transmt data buffer. Loadng the command regster also resets TR. TR wll be avalable on ths output pn only when the USART s enabled to transmt (CTS-=0, TxEN=l). However, the TxRDY bt n the status buffer wll always be set when the transmt data buffer s empty regardless of the state of TxEN and CTS-. TR can be tested by checkng bt 0 of the status regster for pollng operaton or the TR sgnal can be used to generate an nterrupt. On the SCON, CTC2 s used to receve the actve hgh TR sgnal from the USART to decrement a counter from 1 to 0, and consequently, provde a Z80 mode 2 nterrupt vector. Transmtter Clock (TxC-) The transmtter clock controls the seral character transmsson rate. In the asynchronous mode, the TxC- frequency s a multple of the actual baud rate. Bts 0 and 1 of the mode nstructon select the multple to be Ix, 16x, or 64x the baud rate. In the synchronous mode, the TxC- frequency s automatcally selected to equal the actual baud rate. Note that for both synchronous and asynchronous modes, seral data s shfted out of the USART by the fallng edge of TxC-. Receve Data (RxD) Composte seral data s receved at ths nput and converted 4-16

41 to a parallel format; sync, start/stop, and party are checked, and then the assembled byte s prepared for bufferng to the Z80. For communcatons requrng less than 8 bts per character, the extra bts are set to logcal "zero" Recever Ready (RR) The RR output sgnal ndcates to the processor that data has been shfted nto the recever buffer from the recever secton and may be read. The sgnal s actve hgh and wll be reset when the buffer s read by the processor. RR can be actvated only f the recever enable (RxE) has been set n the command regster, even though the recever may be runnng. If the processor does not read the recever buffer before the next character s shfted from the recever secton, then an overrun error wll be ndcated n the status buffer. RR can be tested by checkng bt 1 of the status regster for pollng operaton or the RR sgnal can be used to generate an nterrupt. On the SCON, CT1 may be used to receve the actve hgh RR sgnal from the USART to decrement a counter from 1 to 0, and consequently, provde a Z80 mode 2 nterrupt vector. Recever Clock (RxC-) The recever clock s the rate at whch the ncomng character s receved. In the asynchronous mode, the RxC frequency may be 1, 16, or 64 tmes the actual baud rate, but n the synchronous mode, the RxC- frequency must equal the baud rate. Bts 0 and 1 n the mode nstructon select asynchronous at Ix, 16x, or 64x or synchronous operaton at Ix the baud rate. Unlke TxC-, data s sampled by the USART on the rsng edge of RxC-. Snce the USART wll frequently be handlng both the recepton and transmsson for a gven lnk, the receve and transmt baud rates wll be the same. RxC- and TxC- then requre the same frequency and may be ted together and connected to a sngle clock source or baud rate generator. Sync Detect (SYNC) Ths sgnal s used only n the synchronous mode. It can be an nput or output dependng on the USART mode nstructon, programmng the operaton for external or nternal synchronzaton, respectvely. In the nternal sync mode, the SYNC "output" wll go to a logcal one when the USART has 4-17

42 dentfed the sync character n the recever data stream. If the USART s programmed for "b-sync" operaton, the sync output wll not go to a logcal one untl the second consecutve sync character has been dentfed. In both cases, the sync output transton from low to hgh wll occur n the mddle of the last bt of the respectve sync character. Sync and bt 6 (sync) n the status regster are reset when the status buffer s read or when a devce RST occurs. In the external sync mode, a postve edge on the sync "nput" wll cause the USART to start assemblng a data byte on the next fallng edge of RxC-. The sync sgnal should reman hgh for at least one RxC- perod USART Operaton A set of control words must be sent to the USART to defne the desred mode and communcatons format. The control words wll specfy the baud rate factor (Ix, 16x, 64x), character length (5 to 8), number of stop bts (1, 3/2, 2), asynchronous or synchronous mode, syndet (nternal or external), party, etc. After recevng the control words, the USART s ready to communcate. TxRDY s rased to sgnal the processor that the USART s ready to receve a character for transmsson. When the processor wrtes a character to the USART, TxRDY s automatcally reset. Concurrently, the USART may receve seral data; and after recevng an entre character, the RxRDY output s rased to ndcate a completed character s ready for the processor. The processor fetch wll automatcally reset RxRDY. NOTE: The 8251 and 9551 USARTs may provde faulty data from the recever buffer for the frst read after power-on. A dummy read s recommended. The USART cannot transmt untl the TxEN (Transmtter Enable) bt has been set by a command nstructon and untl the CTS- (Clear to Send) nput s a "zero" USART Programmng The USART must be loaded wth a group of two to four control words provded by the processor before data recepton and transmsson can begn. A reset (nternal or external) must mmedately proceed the control words whch are used to program the complete operatonal descrpton of the 4-18

43 communcatons nterface. If an external reset s not avalable, three successve zeros followed by a reset command nstructon can be used to ntalze the USART. TxD s held n the "markng" state after reset, watng for a new command nstructon. There are two control word formats: 1. Mode Instructon 2. Command Instructon Mode Instructon Ths control word specfes the general characterstcs of the nterface regardng the synchronous or asynchronous mode, baud rate factor, character length, party, and number of stop bts. Once the mode nstructon has been receved, sync characters or command nstructons may be nserted dependng on the mode nstructon content. Command Instructon Ths control word drects the actual operaton of the format selected n the mode nstructon. Functonal control of transmt and receve, error reset, reset, and modem sgnals are accommodated n the command nstructon. 4-19

44 ASYNCHRONOUS OPERATION., f MODE CONTROL C/D C/D = 0 COMMAND DATA (INITIALIZING (SEQUENCE SYNCHRONOUS OPERATION MODE CONTROL C/D = 1 C/D = 0 SYNC #1 SYNC #2 (OPTIONAL) COMMAND DATA INITIALIZING SEQUENCE FIGURE 4-13: Control Word Sequence for Intalzaton 4-20

45 Only a sngle address s set asde for mode control bytes, command bytes, and sync character bytes. For ths to be possble, logc nternal to the chp drects control nformaton to ts proper destnaton based on the sequence n whch t s receved. Followng a reset, the frst control code output s nterpreted as a mode control. If the mode control specfes synchronous operaton, then the next one or two bytes (as determned by the mode byte) output as control codes wll be nterpreted as sync characters. For ether asynchronous or synchronous operaton, the next byte output as a control code s nterpreted as a command. All subsequent bytes output as control codes are nterpreted as commands. There are two ways n whch control logc may return to antcpatng a mode control nput; followng an external reset sgnal or followng an nternal reset command. Mode Control Codes The USART nterprets mode control codes as llustrated n Fgures 4-14 and Control code bts 0 and 1 determne whether synchronous or asynchronous operaton s specfed. A non-zero value n bts 0 and 1 specfes asynchronous operaton and defnes the relatonshp between the data transfer baud rate and recever or transmtter clock rate. Asynchronous seral data may be receved or transmtted on every clock pulse, on every 16th clock pulse, or on every 64th clock pulse. A zero n both bts 0 and 1 defnes the mode of operaton as synchronous. For synchronous and asynchronous modes, control determne the number of data bts whch wll be each data character. bts 2 and present n For synchronous and asynchronous modes, bts 4 and 5 determne whether there wll be a party bt n each character, and f so, whether odd or even party wll be adopted. Thus, n synchronous mode, a character wll consst of fve, sx, seven, or eght data bts, plus an optonal party bt. In asynchronous mode, the data unt wll consst of fve, sx, seven, or eght data bts, an optonal party bt, a preceedng start bt, plus 1, 1 1/2, or 2 tralng stop bts. Interpretaton of subsequent bts dffers for synchronous or asynchronous modes. Control code bts 6 and 7 n asynchronous mode determne how many stop bts wll tral each data unt. 1 1/2 stop bts can only be specfed wth a 16x or 64x baud rate factor. In these two cases, the half stop bt wll be equvalent to 8 or 32 clock pulses, respectvely. 4-21

46 In synchronous mode, control bts 6 and 7 determne how character synchronzaton wll be acheved. When syndet s an output, nternal synchronzaton s specfed; one or two sync characters, as specfed by control bt 7, must be detected at the head of a data stream n order to establsh synchronzaton * V- v ' ' ^r^ v ' uu nn UU Synchronous Mode 5 bts/character 6 bts/character 7 bts/character 8 bts/character v- n 1 Party Dsable Party Enable ^, " U 1 Odd Party Even Party V 1 Syn Syn Detect Detect Output Input V H 1 2 Syn Characters 1 Syn Characters Fgure Synchronous Mode Control Codes Mode Instructon Defnton The USART can operate n ether asynchronous or synchronous communcaton modes. Understandng how the mode nstructon controls the functonal operaton of the USART s easest when the devce s consdered to be two separate components, one asynchronous and the other synchronous, whch share the same support crcuts and package. Although the format defnton can be changed at wll or "on the fly", the two modes wll be explaned separately for clarty. 4-22

47 Async Mode (IX baud rate) 10 - Async Mode (16x baud rate) 11 - Async Mode (64x baud rate) 00-5 bts/character 01-6 bts/character 10-7 bts/character 11-8 bts/character Party Dsable 1 - Party Enable Odd Party 1 - Even Party 00 - Invald 01-1 Stop Bt /2 Stop Bts 11-2 Stop Bts Fgure Asynchronous Mode Control Code Asynchronous Mode When a data character s wrtten nto the USART, t automatcally adds a start bt (low level or "space") and the number of stop bts (hgh level or "mark") specfed by the mode nstructon. If party has been enabled, an odd or even party bt s nserted just before the stop bt(s), as specfed by the mode nstructon. Then, f CTS- and TxEN are actve, the character s transmtted as a seral data stream at the TxD output. Data s shfted out by the fallng edge of TxC- at TxC-, TxC/16- or TxC-/64, as defned by the mode nstructon. If no data characters have been loaded nto the USART, or f all avalable characters have been transmtted, the TxD output remans "hgh" (markng) n preparaton for sendng the start bt of the next character provded by the processor. TxD may be forced to send a break (contnuously low) by settng the correct bt n the command nstructon. 4-23

48 The RxD nput lne s normally held "hgh" (markng) by the transmttng devce. A fallng edge at RxD sgnals the possble begnnng of a start bt and a new character. The start bt s checked by testng for a "low" at ts nomnal center and the bt assemblng counter starts countng. The bt counter locates the approxmate center of the data, party (f specfed), and stop bts. The party error flag (PE) s set, f a party error occurs. Input bts are sampled at the RxD pn wth the rsng edge of RxC-. If a hgh s not detected for the stop bt, whch normally sgnals the end of an nput character, a framng error (FE) wll be set. After a vald stop bt, the nput character s loaded nto the parallel data bus buffer of the USART and the RxRDY sgnal s rased to ndcate to the processor that a character s ready to be fetched. If the processor has faled to fetch the prevous character, the new character replaces the old and the overrun flag (OE) s set. All the error flags can be reset by settng a bt n the command nstructon. Error flag condtons wll not stop subsequent USART operaton. 4-24

49 TRANSMIT/RECEIVE FORMAT ASYNCHRONOUS MODE y 5 ~. Sr- TxD Markng Start Data Bts Party Stop Bt Bt Bts Lf * TRANSMITTER OUTPUT I ^ * ( RxD Start Data Bts Party Stop Bt Bt Bts I / c I RECEIVER INPUT CPU BYTE (5-8 Bts/Char) 5 5 Data Character f j ASSEMBLED SERIAL DATA OUTPUT (TxD) Start Data Character Party Stop Bt Bt Bts j.* -5 5~" TRANSMISSION FORMAT e * Start Bt SERIAL DATA INPUT (RxD) c c Data Character Par ty Bts CPU BYTE (5-8 bts/char)* Stop Bts Data Character / f * If character length s defned as 5, 6, or 7 bts, the unused bts are set to "zero" RECEIVE FORMAT 4-25

50 Synchronous Transmsson As n asynchronous transmsson, the TxD output remans "hgh" (markng) untl the UPD8251 receves the frst character from the processor whch s usually a sync character. After a command nstructon has set TxEN and after clear to send (CTS-) goes low, the frst character s serally transmtted. Data s shfted out on the fallng edge of TxC- and the same rate as TxC-. Once transmsson has started, synchonronus mode format requres that the seral data stream at TxD contnue at the TxC- rate or sync wll be lost. If a data character s not provded by the processor before the UPD8251 transmtter buffer becomes empty, the sync character(s) loaded drectly followng the mode nstructon wll be automatcally nserted n the TxD data stream. The sync character(s) are nserted to fll the lne and mantan synchronzaton untl new data characters are avalable for transmsson. If the USART becomes empty, and must send the sync character (s), the TxEMPTY output s rased to sgnal the processor that the transmtter buffer s empty and sync characters are beng transmtted. TxEMPTY s automatcally reset by the next character from the processor. Synchronous Receve In synchronous receve, character synchronzaton can be ether external or nternal. If the nternal sync mode has been selected, and the enable hunt (EH) bt has been set by a command nstructon, the recever goes nto the hunt mode. Incomng data on the RxD nput s sampled on the rsng edge of RxC-, and the recever buffer s compared wth the frst sync character after each bt has been loaded untl a match s found. If two sync characters have been programmed, the next receved character s also compared. When the sync character(s) programmed have been detected, the USART leaves the hunt mode and s n character synchronzaton. At ths tme, the syndet (output) s set hgh. Syndet s automatcally reset by a status read. If external sync has been specfed n the mode nstructon, a "one" appled to the syndet (nput) for at least one RxCcycle wll synchronze the USART. Party and overrun errors are treated the same n the synchronous as n the asynchronous mode. Framng errors do not apply n the synchronous format. 4-26

51 The processor may command the recever to enter the hunt mode wth a command nstructon whch sets enable hunt (EH) f synchronzaton s lost. TRANSMIT/RECEIVER FORMAT SYNCHRONOUS MODE CPU BYTES (5-8 C f bts/char) Data Characters 3 5 Assembled Seral Data Output (TxD) Sync Char 1 Sync Char 2 TRANSMIT FORMAT Data Characters Sync Char 1 Seral Data Input Sync Char 2 (RxD) Data Characters CPU BYTES (5-8 bts/char) Data Characters RECEIVE FORMAT Command Words Command words are used to ntate specfc functons wthn the USART, such as, "reset all error flags" or "start searchng for sync". Consequently, command words may be ssued by the mcroprocessor to the USART at any tme durng the executon of a program n whch specfc functons are to be ntated wthn the communcaton crcut. A reset operaton (nternal va CMD IR or external va the reset nput) wll cause the USART to nterpret the next "control wrte", whch must mmedately follow the reset, as a mode nstructon. Followng the mode nstructon, a command word, of the format shown n Fgure 4-16, s ssued 4-27

52 -1 to the USART. 0 TXEN 1 0 Enable Transmt Dsable Transmt DTR RxE 1 - Enable Data TRM RDY 1 - Enable RxRDY 0 - Dsable RxRDY SBRK 1 - TxD forced low (break) 0 - Normal Operaton ER RTS IR EH 1 - Reset all error flags 1 - Enable REQ TO SEND 1 - Forces nternal reset 1 - Enter hunt mode Fgure USART Control Command Bt 0 of the command word s the transmt enable bt (TxEN). Data transmsson from the USART cannot take place unless TxEN s set n the command regster. Fgure 5 defnes the way n whch TxEN, TxE, and TxRDY combne to control transmtter operatons. Bt 1 s the data termnal ready (DTR) bt. When the DTR command bt s set, the DTR- output connecton s actve (low). DTR s used to advse a modem that the data termnal s prepared to accept or transmt data. Bt 2 s the recever enable command bt (RxE). RxE s used to enable the RxRDY output sgnal. RxE prevents the RxRDY sgnal from beng generated to notfy the processor that a complete character s framed n the receve character buffer It does not nhbt the assembly of data characters at the nput, however. Consequently, f communcaton crcuts are actve, characters wll be assembled by the recever and 4-28

53 transferred to the recever character buffer. If RxE s dsabled, the overrun error (OE) wll probably be set; to nsure proper operaton, the overrun error s usually reset wth the same command that enables RxE. Table 4-2. Transmtter Secton Operaton TxEN TxE TxRDY Transmt output regster and transmt character buffer empty. TxD contnues to mark f USART s n the asynchronous mode. TxD wll send sync pattern f USART s n the synchronous mode. Data can be entered nto buffer Transmt output regster s shftng a character. Transmt character buffer s avalable to receve a new byte from the processor Transmt regster has fnshed sendng. A new character s watng for transmsson. Ths s a transent condton Transmt regster s currently sendng and an addtonal character s stored n the transmt character buffer for transmsson. 0 X X Transmtter s dsabled. Bt 3 s the send break command bt (SBRK). When SBRK s set, the transmtter ouput (TxD) s nterrupted and a contnuous bnary "0" level (spacng), s appled to the TxD output sgnal. The break wll contnue untl a subsequent command word s sent to the USART to remove SBRK. Bt 4 s the error reset bt (ER). When a command word s 4-29

54 transmtted wth the ER bt set, all three error flags n the status regster are reset. Error reset occurs when the command word s loaded nto the USART. No latch s provded n the command regster to save the ER command bt. Bt 5, the request to send command bt (RTS), sets a latch to reflect the RTS sgnal level. The output of ths latch s created ndependently of other sgnals n the USART. As a result, data transfers may be made by the mcroprocessor to the transmt regster, and data may be actvely transmtted to the communcaton lne through TxD regardless of the status of RTS. Bt 6, the nternal reset (IR), causes the USART to return to the dle mode. All functons wthn the USART cease, and no new operaton can be resumed untl the crcut s rentalzed. If the operatng mode s to be altered durng the executon of a mcroprocessor program, the USART must frst be reset. Ether the external reset connecton can be actvated, or the nternal reset command can be sent to the USART. Internal reset s a momentary functon performed only when the command s used. Bt 7 s the enter hunt command bt (EH). The enter hunt mode command- s only effectve for the USART when t s operatng n the synchronous mode. EH causes the recever to stop assemblng characters at the RxD nput and start searchng for the prescrbed sync pattern. Once the "enter hunt" mode has been ntated, the search for the sync pattern wll contnue ndefntely untl EH s reset when a subsequent command word s sent, when the IR command s sent to the USART, or when sync characters are recognzed. Status Read Format It s frequently necessary for the processor to examne the "status" of an actve nterface devce to determne f errors have occurred or to notce other condtons whch requre a response from the processor. The USART has features whch allow the processor to "read" the devce status at any tme. A data fetch s ssued by the processor whle holdng the C/D- nput "hgh" to obtan devce status nformaton. Many of the bts n the status regster are copes of external pns. Ths dual status arrangement allows the USART to be used n both polled and nterrupt drven envronments. 4-30

55 0 TxRDY (Transmtter Ready) RxRDY (Receve Ready) TxE (Transmt Reg. Empty) PE (Party Error) DE (Recever Overrun) FE (Char. Framng Error) SYNDET (Sync Detected) DSR (Data Set Ready) TxRDY sgnals the processor that the transmt character buffer s empty and that the USART can accept a new character for transmsson. RxRDY sgnals the processor that a completed character s holdng n the receve character buffer regster for transfer to the processor TxE sgnals the processor empty. that the transmt regster s PE s the party error sgnal ndcatng to the CPU that the character stored n the receve character buffer was receved wth an ncorrect number of bnary "1" bts. The PE flag s cleared by settng the ER bt n a subsequent command nstructon. PE beng set does not nhbt USART operaton. OE s the recever overrun error. OE s set whenever a byte stored n the recever character regster s overwrtten wth a new byte before beng transferred to the processor. The OE flag s cleared by settng the ER bt n a subsequent command nstructon. OE beng set does not nhbt USART operaton. FE s the character framng error whch ndcates that the asynchronous mode byte stored n the recever character buffer was receved wth an ncorrect character bt format (stop bt), as specfed by the current mode. The FE flag s cleared by settng the ER bt n a subsequent command nstructon. FE beng set does not nhbt USART operaton. 4-31

56 4.3 DYNAMIC MEMORY MODULE A Dynamc Memory Module s provded for the Development System for storage of user programs and the operatng system. The module utlzes 16K Dynamc RAM components to provde a maxmum storage capacty of 60K bytes. Memory addressng s controlled by a combnaton of the Address Bus (AO-A15) bts and Page and Card Select sgnals from the Central Processor Module, prevously descrbed. The relatonshps are llustrated n Fgure Control Logc (Sheet 1) The Control Logc receves Memory Request (MRQ), Memory Read (MRD), Wrte (WR), Memory Inhbt and Refresh (RFSH) sgnals from the Central Processor Module and converts them to tmng sequences for memory access. Memory access s trggered by MRQ (actve low). s ntated the followng events must occur: Once an access For refresh cycles MRQ (low) and RFSH (low) force all Row Address Selects (RASO-RAS3) to ther actve low state and generates CONTROL (low) and ICAS (low) for the refresh cycle. The data buffers are swtched to prevent gatng of any data onto the system data bus. For memory read or wrte cycles MRQ (actve low) trggers the access and enables the RAS address to be gated to the memory array (CONTROL gong low) followed by the delayed RAS sgnal ICAS (actve low), whch enables gatng of the CAS address to the memory array. The MEMORY INHIBIT sgnal s provded by the Central Processor Module when accessng the on-board 3K PROM or IK statc RAM to dsable the data buffers of the Dynamc Memory Module from placng data onto the system data bus Data Buffers (Sheet 2) A par of 4-bt bdrectonal bus drvers (A3 and A6) serve to nterface the Dynamc RAM Array to the system data bus. These are always enabled (pn 1 grounded) and are solely controlled by OUTPUT ENABLE (actve low). The OUTPUT ENABLE sgnal orgnates from the control logc (Sheet 1) and selects whether data s to be receved from or placed onto the system data bus. For memory wrte (MRQ and WR low) operatons, the buffers receve data from the system data bus, ths s also true for refresh operatons (MRQ and MRD low) and data from the selected address s gated onto the system data bus. 4-32

57 4.3.3 Row Address Select (Sheet 1) The Row Address Select logc s composed of a mulplexer (All) and two addtonal stages of gatng to dfferentate between normal memory access and refresh accesses. Durng refresh operatons (MRQ and RFSH low) all RAS sgnals (RASO-RAS3) are forced to ther actve low state. Normal memory accesses nvolve generaton of selected RAS sgnals by gatng the outputs of multplexer All wth Memory Request (MRQ) actve low. The jumpers for RAS address selecton are shown below. FOR 16K COMPONENTS (60K): L-M, N Address Multplex (Sheet 2) The Address Multplex functon (A7 and A8) provdes control of the Z80-CPU addresses, whch are gated to the Dynamc Memory Array durng the RAS and CAS cycles of each memory access. Enables to the multplexers are grounded, thereby constantly provdng an enable for ether the A or B nputs to be gated to the memory array. When n the dle state (CONTROL sgnal hgh), the B-nputs AO-A4, A12 and A13 are gated to the array. Durng a RAS cycle (Control actve low), the A-nputs are gated as long as t s not a refresh (RFSH low) cycle. The jumperng for the proper address selecton s shown below. FOR 16K COMPONENTS (60K): B-C, E-F, H-I Dynamc Memory Array (Sheet 4) The Dynamc Memory Array s composed of 32, 16K X 1 bt Dynamc Random Access Memory components. These are arranged n four rows, each contanng 16,384 bytes of storage. Ths scheme allows a basc confguraton of 60K. 4.4 FLOPPY DISC CONTROLLER MODULE The Floppy Dsc Controller Module provdes an nterface between the Development System and two sngle-densty, snglesded, hard-sectored floppy dsk drves, e.g., Shugart Model 801 Dsc Drve. Interface and tmng functons are provded by the controller, but the ntellgence for the controller s mbedded n the 3K PROM Debug frmware. A block dagram of the controller s provded n Fgure 4-9, whch may be used as a reference. 4-33

58 INDEX CB G1IOW1M6 OF DISC) SECTOR HOLES'* ; ( 23 DATA BYTES/TRACK) TH,ACToPl. 0/sc R 4-3^

59 4.4.1 Dskette Format In order to understand the operatons of dsk unts, the reader should know how data s stored on the surface of the dskettes. Each hard sectored dskette contans 32 holes or sector marks whch dentfy the begnnng of each sector on the dskette. The begnnng of the dskette tself contans a sngle hole called an "ndex mark," whch serves as a reference pont for all succeedng sector marks, (see Fgure 4-3). The ndex and sector marks serve to synchronze the controller rotatonal movement of the dskette, but a means must be provded to locate data stored at varous parts on the surface of the dskette from the center to the outer lmts. Data s stored n concentrc locatons called "tracks" begnnng from the outer-most edge (Track 00) to the nner-most edge (Track 76). Movement from one track to the next s controlled by a stepper motor wthn the dsk drve whch controls the read/wrte head postonng. A pulse appled to the drve causes the head to be moved one track poston. The drecton of movement (nware/outward) must also be provded to the drve by the controller Data Format The format of the data wrtten on a selected track between a sector mark and the next sector mark s controlled by the drver program contaned n the 3K PROM Debug frmware. The basc format for the data wrtten n each sector s llustrated below. / / / / / PREAMBLI / / / / DATA BLOCK LINK PPC \* \\ / MB LEV - SHADED AREAS ARE ESTABLISHED BY THE FIRMWARE AND CONTROLLER PREAMBLE - 16 bytes of all zeroes; used to synchronze the controller for the followng data felds. 4-35

60 SECTOR ADDRESS - sngle byte havng the most sgnfcent bt equal to a "1" for a start bt, followed by two zeroes The last fve bts contan the sector address. 100 xxxxx SECTOR ADDRESS (0-1FH) TRACK ADDRESS - sngle byte contanng the track address n the least sgnfcant seven bts AD-A6. 0 xxxxxxx TRACK ADDRESS (0-7FH) DATA BLOCK bytes of data stored by the user; may be n bnary or ASCII form. LINKAGE - provdes two ponters, each composed of two bytes, whch pont to the precedng and succeedng sector of data n the fle. The ponters are composed of the sector and track addresses prevously descrbed. CRC - the Cyclc Redundancy Check word (2 bytes) s the output of the CRC generator contaned n the controller. It s a check sum for the sector and track addresses, data block and lnkage words. POSTAMBLE - s composed of a seres of zeroes wrtten after the CRC word to provde a protecton gap after the vald data felds of the sector RECORDING FORMAT The format of the data recorded on the dskette s a total functon of the System resdent frmware. Data s recorded on the dskette usng frequency modulaton as the recordng mode;.e., each data bt recorded on the dskette has an assocated clock bt recorded wth t. Ths s referred to as FM. Data wrtten on and read back from the dskette takes the form as shown n Fgure 4-4. The bnary data pattern shown represents a 101. CLOCK BITS I DATA BITS Fgure 4-4 DATA PATTERN 4-36

61 a. BIT CELL - As shown n Fgure 4-5, the clock bts and data bts (f present) are nterleaved. By defnton, a bt cell s the perod between the leadng edge of one clock bt and the leadng edge of the next clock bt. CLOCK BITS DATA BIT (IF PRESENT) Fgure 4-5 DATA PATTERN BYTE - A Byte, when referrng to seral data (beng wrtten onto or read from the dsk drve) s defned as 8 consecutve bt cells. The most sgnfcant bt cell s defned as bt cell 0, and the least sgnfcant bt cell s defned as bt cell 7. When reference s made to a specfc data bt (.e., data bt 3), t s wth respect to the correspondng bt cell (bt cell 3). Durng a wrte operaton, bt cell 0 of each byte s transferred to the dsk drve frst and bt cell 7 s beng transferred last. Correspondngly, the most sgnfcant byte of data s transferred to the dsk frst, and the least sgnfcant byte s transferred last. When data s read back from the drve, bt cell 0 of each byte wll be transferred frst and bt cell 7 last. As wth readng, the most sgnfcant byte wll be transferred frst from the drve to the user. 4-37

62 Fgure 4-6 llustrates the relatonshp of the bts wthn a byte, and Fgure 4-7 llustrates the relatonshp of the bytes for read and wrte data Floppy Dsk Controller Interfaces As prevously descrbed the Floppy Dsk Controller serves to nterface the Development System to dual floppy dsk drves. Ths operaton s represented n block form by Fgure 4-8. The controller must provde two nterfaces: (1) for nterface to the Development System, and (2) for the dsk unts. Each of these nterfaces wll be brefly descrbed n the followng text. DEVELOPMENT SYSTEM INTERFACE: Interface to the Development System s farly smple. The three system busses (address, data and control) are employed by the controller n a smplfed form. Data Bus - nterfaces are eght bts (DO-D7) of the system data bus to the controller for command, status, and data exchange. Address Bus - does not drectly nterface to the controller. Because the controller s an I/O devce and does not posses DMA (drect memory access) capabltes, t may be selected by decodng the lower Address Bus lnes (AO-A7) of the Z80-CPU durng I/O Request operatons. Ths decodng s performed by the MONITOR Module and results n the followng select sgnals whch are appled to the controller. DISK CONT A (Port F9H) used for loadng command nformaton nto the controller. DISK CONT B (Port FAH) also used for loadng command nformaton nto the controller and retrevng status. DISK DATA (Port F8) s used to transfer data to or from the on-board data buffer. Control Bus - a mnmal number of control sgnals are requred because the controller only utlzes the I/O controls of the Z80-CPU. The IORQ sgnal along wth RD for I/O read operatons 4-38

63 Fgure 4-6 llustrates the relatonshp of the bts wthn a byte, and Fgure 4-7 llustrates the relatonshp of the bytes for read and wrte data. C D C D C C D C C D C n n / BIT CELLO MSB BIT CELL 1 BIT CELL: BIT CELL 3 BIT CELL 4 BIT CELLS BIT CELL 6 BIT CELL: LSB BIT CELLO BINARY REPRESENTATION OF DATA BITS CLOCK BITS HEXADECIMAL REPRESENTATION OF- DATA BITS CLOCK BITS Fgure 4.5 BITS WITHIN A BYTE I BYTE 0 BYTE } > \ <> { 10 1 II : BYTE! BIT CELL 0 OF BYTE 9 IS FIRST DATA TO BE SENT TO THE DRIVE WHEN WRITING AND FROM THE DRIVE WHEN READING DATA BYTES BIT CELL 7 OF BYTE 17 IS LAST DATA TO BE SENT TO THE DRIVE WHEN WRITING AND FROM THE DRIVE WHEN READING Fgure Q f _J DATA BYTE RELATIONSHIPS 4-39

64 d»05 n U 1 a a au. TT* 3 Z ^ s,h a V V V U n a: 5 a a (D (0 a 4 tmrm < 03 o <r> a a

65 or WR for I/O wrte operatons s used to control data movement between the system data bus and the controller. The PHI clock from the Central Processor Module s used by the controller for all tmng. Also provded s the SYS RESET sgnal from the CPM. Two outputs are provded from the controller to the system: (1) WAIT s used to synchronze data transfer from the controller to the Z80-CPU; (2) INDX provdes ndex and sector mark recognton whch s used to clock the CTC located on the SCON Module. FLOPPY DISC DRIVE INTERFACE: Many sgnals are provded for the floppy dsk nterface n order to faclate the nterface of many types of floppy dsk drves. However, when utlzng the Shugart SA801 Dsc Drves a mnmum number of sgnals may be employed due to the flexablty of the dsk unts. SELO/SEL1 (SELECT) - sgnals are used by the drve(s) to determne when t has been selected for an operaton by the controller. Under normal operaton, the Drve Select lne wll load the R/W head, apply power to the stepper motor, enable the nput lnes, actvate the output lnes, and lght the ACTIVITY LED on the front of the drve. LOAD HEAD 0/1 - sgnals are not used by the nterface, but are optonally provded to enable the controller to control the loadng of the R/W heads n the drve(s). STEP OUT/STEP IN - sgnals are also not used by the nterface, but are provded as ndependent controls to allow two sgnals for stepper motor control. The drves presently employ the use of the STEP sgnal and DIRECTION sgnal for ths functon. STEP - sgnal (actve hgh) n conjuncton wth the DIRECTION sgnal beng hgh causes the head to move one track away from the center of the dsk. DIRECTION - sgnal (when hgh) selects movement away from the center of the dsk; conversely, when low, selects movement toward the center of the dsk. CURRENT - provdes an ndependent sgnal for applyng DC power to the Stepper Motor of the dsk drve(s). Ths s not used by the SA801 Dsc Drves. WRITE GATE - provdes a common control to the dsk drves to wrte data onto the dsk surface. When dsabled (logc hgh) the heads are enabled for read operatons. WRITE 1 - provdes an optonal sgnal whch may be used to generate the WRITE GATE functon for drve 1 whle WRITE GATE tself would perform the functon for drve

66 WR DATA - ths nterface lne provdes the data to be wrtten on the dsk and s enabled by the WRITE GATE lne beng actve (low). Each transton from a logcal one level to a logcal zero level wll cause the current through the Read/Wrte head to be reversed, thereby wrtng a data bt. RDY (Ready) - ths sgnal ndcates that a dsk has been nserted, the door closed, and the two ndex holes sensed. DOOR OPEN 1 - provdes an optonal status bt to ndcate that the drve has gone from a READY state to a non-ready state (door open). TRK 00/01 - provdes a sgnal from the drve(s) whch ndcates that the drve's R/W head s postoned at track zero (outermost track) and the access crcutry s drvng current through phase one of the stepper motor. Only TRKOO s requred by both SA801 Dsc Drves and the controller, due to the drve selecton technque employed. WRT PROT 0/1 - provdes a status ndcatng the dskette nserted nto the drve has a wrte-protecton tab nstalled. Only a sngle lne s requred, and s shared by both SA801 Dsc Drves. INDXO/1 - ths sgnal provdes an ndcaton of the begnnng of the track once every revoluton of the dskette ( ms). Only INDXO s used, and t s shared by both drves. READ DATA - ths lne provdes raw read data (data and clock) as t s read by the R/W head. Optonally, t can contan only the read data f the drve contans data/clock separaton logc. READ CLK - provdes the read clocks after they have been nternally separated from the data/clock stream by the drve's nternal data separaton logc Floppy Controller - Detaled Operaton The detaled operaton of the Floppy Dsc Controller Module wll be provded usng Fgure 4-9 as a reference. Ths llustraton functonally llustrates the controller and provdes specfc references to logc Sheet numbers for the Floppy Dsc Controller. 4-42

67 < r» r >» X X \ t w \X J 1 ^? > / «^ DlfCCOKTROL ^ DISC STATUS 1 A <T a 1» 1 co 1 r I SEPARATOR 1 r ^ ^M* 1 n <. x" *s> 1 STATUS ( MULTIPLEX * \ to O cr CJ 0^M t C-«) I t k r ^ ^, /- <! r! a I 4 11 A r ^ 1 JI c1 (X 5 CJ r ^ ^ j I \ a. 3 S 1^ p» ' L * <5 * </) 'A " ***s Ul S ~ (1 ^ <5 ^ I rr Q ^U, ll 1 <r t y Q c_ 4 r a u. \ UJ\ X 1 ^ 3k ^ r CSJ ^Ml^l^ t j\ V " r I t. \ 5 } t f a UJ t a u Ifl, 0 LL H -r Q U d m a Iu U (0 (f } u 3 t < J ^X"s c0 3 0 k 1" ^ *x, S T 1 f»- 1 &» t I 3 1 r G5 ft a ^ t I INTERFACE A ' J2. CO ā ^a " < t 1 r : ^- N s r > k t / \ Sk K^ 4-43

68 Data Bus Latches (Sheet 3) All data s destned for the controller (I/O Ports F8, F9 or FA) must pass through the Data Bus Latches (A30 and A33). When any of the three I/O Port Addresses assgned to the controller are selected durng an I/O (Port) Wrte operaton (IOWR actve low), the contents of the system data bus s latched by the Data Bus Latches. The outputs of the latches are routed to the Data Converter (A23 and A24) on Sheet 2, as well as to the Control Regsters (A22, A25 and A26) on Sheet Data Converter (Sheet 2) The Data Converter (A23 and A24) provdes both parallel-toseral data converson durng wrte operatons, and seralto-parallel data converson durng read operatons. Durng Wrte operatons the converter s parallel loaded wth the contents of the Data Bus Latches (Sheet 3) as a result of TX LOAD (actve hgh) and the leadng edge of the SHIFT CLK (actve low). When the TX LOAD sgnal goes false (logc 0) the converter functons as a shft regster, performng a shft rght operaton wth each occurrance of the SHIFT CLK. The seral data output (TxK), most sgnfcant bt of the converter s routed to the CRC Logc for exposure to the CRC generator. Durng Read operatons the output of the Data Separator (Sheet 1) RxDATA s appled to the seral data nput of the Data Converter. The occurrance of each SHIFT CLK wll serally shft the RxData nto the converter. Once eght bts have been loaded nto the converter the contents of the converter are quckly transferred to the Read Data Buffer (Sheet 2) so that the next eght bts may be clocked n wthout dsrupton of the seral data stream Read Data Buffer (Sheet 2) The Read Data Buffer (A31 and A32) provdes a temporary storage for data durng read operatons from the dsk. Ths temporary storage s requred to prevent dsrupton of the seral data stream beng shfted nto the Data Converter. Once eght bts have been assembled by the converter they are transferred n parallel to the Read Data Buffer by the RxBUFF LOAD sgnal (actve low) so that the seral data tmng nto the converter s not dsrupted. The 3K PROM frmware wll transfer the data from the Read Data Buffer by executng an I/O Port Read from Port F8H whch 4-44

69 results n the generaton of READ CHAR (actve low). Ths acton enables the outputs of the Read Data Buffer to go actve, transferrng the contents to the system data bus (DO-D7) CRC Logc (Sheet 7) The CRC Logc provdes the CRC Generaton and Check functon for data beng serally wrtten or read from the dsk. It also performs a data multplex functon n determnng what type of data s to be gated to the Data Encoder durng wrte operatons. An F9401 CRC Generator/Checker (AZ) provdes the generaton and checkng of the seral data stream. Durng wrte operatons, ndcated by WRITE ENABLE (hgh) and WR MODE+ (hgh), the output of the Data Converter (TxD) s gated to the generator va A15 and s clocked nto the CRC Generator/Checker by the SHIFT CLK (low). The generator performs a dvson on the ncomng data stream usng a CRC-16 polynomal. When data s beng entered, the CRC Enable flp-flop A10 (Sheet 7) s reset causng the CWE (check Word Enable) nput to the generator to be dsabled. Once the data has been completely transferred (128 bytes) the 3K PROM frmware wll set the CRC Enable flp-flop actvatng the CWE nput to the generator. Ths condton wll enable the 16-bt cyclc redundency check character to be appended to the data stream to the dsk. Durng read operatons, the RCV DATA sgnal from the Data Converter (Sheet 2) s gated to the generator by RX MODE+ (hgh). The data s once agan shfted nto the generator by the SHIFT CLK (low) sgnal, but the generator only functons as a montor to sample the data stream. Once the last bt of the ncomng data stream has been receved, ths would logcally be the last bt of the 16-bt CRC receved, the CRC ERR (actve low) may be sampled to see f an error has occurred. Ths sgnal wll reman n a fxed state untl another SHIFT CLK s appled or untl the generator s reset by RX MODE + or WR MODE + gong false (low). 4-45

70 Data Encoder (Sheet 3) The Wrte Data Encoder (A4, A18, A19, A12, A20 and A27) serves to ntegrate the wrte clock wth the data beng transferred to the dsk drve, to mantan the double frequency recordng format (reference Fgure 4-4). The 80 clock from the Central Processor module s dvded by eght to yeld A (2.047 MHZ) whch s appled to the Data Encoder whch performs a dvde by 2, 4 and 8 converson. The dvde by eght output (TX CLK) occurs at a 256KHZ rate and s appled to the Read/ Wrte Control logc (Sheet 4) to control data movement wthn the controller. The output WR DATA nterfaces drectly to the dsk drve(s) as a composte clock and data sgnal Data Separator (Sheet 1) The Data Separator shown on logc Sheet 1 serves to nterface the READ DATA and RD CLK sgnals from the dsk drve(s) to the controller. Ths board s desgned to accomodate nterface to drves whch have no nternal data separaton logc or to those whch do. For the Model SA801 Dsc Drves the latter s the case so the READ DATA and RD CLK sgnals are present from the dsk nterface. Four jumpers are provded on the board (A-D) to select nternal or external data separaton. The poston of each jumper for nternal or external data separaton s shown below. A B C D INTERNAL EXTERNAL The logc s enabled to functon only n read operatons, RX MODE + (actve hgh) and results n the generaton of RX DATA whch goes to the Data Converter (Sheet 2) and the Read/Wrte Control (Sheet 4). Also generated s RX CLK (actve hgh) whch s routed to the Read/Wrte Control logc to control data movement durng read operatons Read/Wrte Control (Sheet 4) The logc shown on Sheet 4 serves to control the data transfer between the controller and the drve, the data movement wthn the controller and to synchronze the whole process wth data transfers to or from the system data bus. WRITE OPERATIONS: The wrte operaton s ntated by settng the WRITE latch n the Control Regster (Sheet 6). Ths results n two sgnals: WR MODE (actve low) and WR-MODE + (actve hgh), whch are appled to the Read/Wrte Control logc on Sheet 4. The WR MODE + removes the reset from the Wrte Enable 4-46

71 generator (A6) and the WR MODE (low) prevents read clocks (RX CLK) from trggerng the Shft Clock generator (A5 and A9). The WR MODE + enables the Shft Clock generator to functon wth each occurrance of the TX CLK. The WR MODE (actve low) removes the set nput from the Start Bt Detecton logc (A10 and All) and allows the bt counter (All) to ncrement wth each TX CLK. Once eght bts have been wrtten the TX BUFF UNLOAD (actve low) sgnal s nverted by A8 to provde TX LOAD (hgh) to enable the parallel loadng of the Data Bus Latch outputs (Sheet 3) nto the Data Converter (Sheet 2) so that the next character may be serally shfted to the dsk. READ OPERATIONS: The read operaton s ntated when WR MODE (actve low) sgnal s false (hgh) enablng the RX CLK to trgger SHIFT CLK. The SHIFT CLK cannot ncrement the Bt Counter (All) untl the Start Bt Detect Flp-flop s set, sgnfyng the frst bt receved of the sector address. By mplementng ths feature, only the actual data felds of the record beng read wll be transferred to the Z80-CPU and CRC Checkng wll not commence untl the actual data s present. Once the data begns, the Bt Counter advances untl eght bts have been serally shfted nto the Data Converter (Sheet 2) as ndcated by RX BUFF LOAD (actve low). The RX BUFF LOAD (low) enables the outputs of the Data Converter (Sheet 2) where t may be transferred to the Z80-CPU by executng a Port Read to Port F8H. Data must be removed from the buffer pror to the recepton of the next data character or t wll be over wr tten System Control Interface (Sheet 3) The nterface between the system and the controller s shown on logc Sheet 3 and Sheet 5. The Z80-CPU I/O Control sgnals, IORQ, RD and WR are decoded on Sheet 5 to form IORD and IOWR whch are used on Sheet 3. The dsk controller s assgned three I/O Port Addresses (F8, F9 and FA) each of whch has a specal purpose. A decode port address results n the generaton of the followng gatng sgnals used to control data movement to or from the system data bus. WR CONT 1 - Wrte to port FA - enables loadng of Control Regster B WR CHAR - Wrte to port F8 - enables loadng of Data Bus Latches READ CHAR - Read to port FA - enables readng of Read Data Buffer READ STATUS - Read to port FA - enables readng of the Status Multplex WR CONT 2 - Wrte to port F9 - enables loadng of Control Regster A 4-47

72 Wat Generator (Sheet 5) The Wat Generator s provded to help synchronze the data transfer between the system data bus and the controller. Durng Wrte operatons t functons usng TX BUFF UNLOAD and WR CHAR sgnals to prevent the Z80-CPU from transferrng a character nto the Data Bus Latches (Sheet 3) untl the exstng data beng held n the latches s transferred to the Data Converter (Sheet 2). Durng Read operatons t functons usng RX BUFF LOAD and READ CHAR sgnals to prevent the transfer of data from the Read Buffer (Sheet 2) untl t has been loaded from the outputs of the Data Converter (Sheet 2) Control Regster (Sheet 6) The Control Regster s actually composed of three 4-bt regsters (A22, A25 and A26) whch are confgured to form an eght bt regster (A22 and A25) and a four bt regster (A26). The ntent s to provde an eght bt regster to control those sgnals whch are accessed or changed most frequently and a 4-bt regster whch s seldom accessed. These regsters shall be referenced as Control Regster A (8-bts) and Control Regster B (4-bts). The varous bts of the regsters and ther respectve I/O Port Addresses are shown n Fgure Control Interface (Sheet 6) The Control sgnal nterface to the dsk drves s shown on logc Sheet 6. The nterface crcutry (A27, A34 and A35) decodes the outputs of the Control Regsters and nverts the sgnals to drve the dsk drve nterface. Many sgnals are presented to the nterface whch are not used by the Model SA801 Dsc Drve, reference paragraph Status Multplex (Sheet 6) The Status Multplex conssts of a 2-nput 4-bt multplexer (A37) and a bus drver (A28). Eght sgnals are provded nto the multplexer of whch four may be sampled at any one tme. The selecton of whch four bts are examned s determned by the SEL 1 (bt 6) sgnal from Control Regster B. The outputs of the multplexer are routed to A28 along wth CRC ERR (actve low) from the CRC Checker (Sheet 7). Gatng of the status onto the system data bus s controlled by the READ STATUS (low) sgnal from the System Control Interface (Sheet 5). The status bts are shown n Fgure Lke the Control Interface sgnals there are many status sgnals some of whch are not used, reference paragraph

73 STATUS FRQIVN PORT FAB a) 7 MOT USED CRC ERROR CACTWE LOW) INDX (2 (ACTIVS LOW) WRITE PROTECT 0 (ACTIVE L&V*) TRACK CSQS (ACTIVE READV SEL1-1 CDRWE O NOT USED CRC ERROR (ACT\\)E PROTSCT (TACTWE U)Vj() TRACK c3 1 CACTNE 4-l\ r RESISTER A (PQRT A a L NOT USED CRC ENABLE READ LOAD HEAD STEP OUT- STEP IN CURRENT (STEPPER MOTOR) WRITE CDNTPQL REGISTER Q (PORT I a NOT USED MOTOR a NOT USED SELECT 1 SELECT 0 DISC. CQKTTROL 4-49

74 4.5 Breakpont Module Ths module functons as a part of the Emulaton Subsystem and provdes the user wth the capablty to suspend the real-tme executon of a program when selected address, data and control bus events occur. A block dagram, Fgure 4-18, s provded as a reference contanng specfc references to logc Sheet numbers Control Logc The control logc, although not shown on the block dagram, performs an mportant part n the Breakpont Module. A majorty of the control logc s shown on Sheet 4. Ths logc s responsble for controllng the loadng of address, data, data mask and control bus arguments nto the respectve regsters. Loadng of the varous arguments must be performed n strct sequence by ssung I/O (Port) wrte commands to Port FBH. The sequence may be termnated early by ssung an I/O (Port) read to Port FBH whch wll reset the Sequence Control Regster (A7). The Sequence Control Regster (A7) and assocated decoder (A14) serve to generate data strobe sgnals for loadng of the selected argument regsters. These strobes are actve for the duraton of the IOWRB pulse generated on logc Sheet 3. 1st Wrte - LOAD MODE (Control Argument) 2nd Wrte - LOAD DATA (Data Argument) 3rd Wrte - LOAD ADDR LOWER (Lower Half of Address Argument) 4th Wrte - LOAD ADDR UPPER (Upper Half of Address Argument) 5th Wrte - LOAD DATA MASK (Data Mask Argument) 4-50

75 s 3 LU 1 Gfl UJ <3 lu <n UJ a 2 n 0. o a a < a -J UJ o ^ ^r> 6 <Q u. gs & t SJ TT <r m 4-51

76 Generaton of the frst wrte (LOAD MODE actve low) causes the control bus argument to be loaded (Sheet 3) and also loads the Break Condton Regster (A12) on Sheet 4. The bt confguraton of the data bus, for loadng these regsters s shown below. D7 \. D6 D5 D4 D3 D2 Dl DO V CONTROL 1 ] ARGUMENT DO - PORT READ Dl - PORT WRITE D2 - MEMORY READ D3 - MEMORY WRITE D4 - OPCODE FETCH BREAK CONDITION D5 - SYNC/BREAK (LOW) D6 - DATA COMPARE D7 - ADDRESS COMPARE 4-52

77 4.5.2 Address Argument Regster (Sheet 2) The address Argument Regster s composed of four quadruple D-type flp-flops confgured to form two eght bt regsters havng separate clock nputs. Elements A19 and A20 comprse the lower Address Argument Regster and A17 and A18 form the Upper Address Argument Regster. Data bus nformaton s transferred nto the lower Address Argument Regster when the thrd Port Wrte s ssued to Port FBH whle the Upper Address Argument Regster s loaded wth the fourth Port Wrte. The outputs of the argument regsters feed the B-nputs of the Address Comparators also shown on the Sheet Address Comparators (Sheet 2) Address comparson s acheved usng four 4-bt magntude comparators whch contnuously compare the contents of the Upper and Lower Address Argument Regsters wth the Z80-CPU's Address Bus (AO-A15). When an equvalence occurs the A=B output of the comparator wll be an actve hgh and dependng on the state of EN ADDR LSB, the output of A25 or A27 wll be gated to flp-flop A3 (ADDR EQ). If the selected Control Bus Argument s true (CONTROL EQ actve hgh) flp-flop A3 wll set ndcatng that an address comparson has occurred. Ths sgnal s routed to the Break Condton Selecton logc (Sheet 4) Data Argument Regster (Sheet 1) The data argument s loaded nto A22 and A23 durng the second I/O (Port) Wrte to PORT FBH by the clock sgnal LOAD DATA beng actve low. Outputs of the Data Argument Regster are routed to the Data Comparson logc shown on logc Sheet 1. Once data s loaded nto the Data Argument Regster t cannot be cleared, nstead another wrte operaton must be performed wth the data bus set to zero n order to affect a regster clear Data Argument Compare Logc (Sheet 1) Contents of the Data Argument Regster are compared wth the Z80-CPU data bus (DO-D7) usng two quad-nput exclusve-or gates (A15 and A16). Equvalence of selected data bts result n DO EQU - D7 EQU beng generated. These sgnals are routed to the Data Mask Compare logc for another comparson wth the 4-53

78 mask, f any, before the DATA EQ flp-flop (A10) may be set. The settng of the DATA EQ flp-flop s contngent on two events, (1) the gatng of the DATA BITS EQ sgnal from the Data Mask Compare logc and (2) the generaton of the DATA STROBE sgnal from the Montor Module. Ths s to nsure the Real Tme Storage Module captures data bus actvty before the break actually occurs. The CONTROL EQ sgnal nto the second stage of A10 nsures the proper control argument accompanes the condton when the data bus s equvalent to the Data Argument Regster Data Mask Regster (Sheet 5) The Data Mask Regster provdes the user wth a means to montor the data bus for a selected bt or group of bts. Components Al and A2 from the 8-bt Data Mask Regster whch s loaded by the executon of the ffth Port Wrte to Port FBH. Lke the Data Argument Regster the Data Mask Regster cannot be reset. It must be reset by wrtng an all zeroes data byte nto t Data Mask Compare Logc (Sheet 5) Data mask comparson s mplemented usng two quad 2-nput postve NAND-buffers (A8 and A9) whose outputs are wre-or'ed to form DATA BITS EQ (actve low). The mask functon works as follows: Functon Example: User wants to test for bt 7 beng actve hgh from a specfc port address Data Argument Regster: Data Bus: 1 Q 1 1 Q Q 0 1 XOR Result: Data Mask Regster: NAND Result: 0^ Any Low Output = Data Bts 4-54

79 4.5.8 Control Argument Regster (Sheet 3) Control bus arguments are loaded nto A21 (Sheet 3) and A12 (Sheet 4) upon ssuance of the frst Port Wrte to Port FBH by the clock sgnal LOAD MODE beng actve low. As mentoned prevously n subparagraph both the control arguments and break condton are loaded smultaneously. Control bus condtons are: - IORD (DO) Port Read - IOWR (Dl) Port Wrte - MRD (D2) Memory Read - MWR (D3) Memory Wrte - Ml (Dr) Opcode Fetch Control Compare Logc (Sheet 3) The control bus argument bts are compared wth the actual Z80-CPU control bus by A28 and A5, the latter beng used for Ml or Opcode Fetch. Only one of the above fve condtons may be loaded nto the argument regster at any one tme. Detecton of equvalence between the bus and argument regster results n CONTROL EQ actve low and actve hgh beng generated Break/Sync Generator (Sheet 4 The logc provded by the Break/Sync Generator controls when a SYNC pulse and/or BREAK s to be generated. Whenever there s an equvalence between the argument regsters and the bus actvty a SYNC s generated, a Break may or may not be generated. The QA output of A12 (Break Condton Regster) determnes f only a SYNC or a SYNC and a BREAK wll occur. Whenever a SYNC occurs, the sgnal forces the BREAK STATUS latch (A6) set. The BREAK STATUS (actve hgh) sgnal may be examned by executng a Port Read to Port FEB. Ths latch may be reset by POWER ON CLR (low) or a Port Read to Port FBH. If a BREAK occurs the sgnal (actve low) s gated va A30-pn 13 to the Montor Module where t s used to trgger the Mode Change Logc thereby causng a transton from User Mode to Montor Mode termnatng the executon of the user's program. 4-55

80 4.6 Real Tme Storage Module ** % The Real Tme Storage Module provdes the functon of a programmable storage devce whch montors the Z80-CPU address, data and control buses whle runnng n USER or Montor Mode. Fgure 4-X provdes a block dagram whch wll be used as a reference from the followng text Storage Array (Sheets 1 and 2) Data storage for the selected bus events by eght 256 x 4 bt statc RAMs. These RAMs serve to store 16 address bts (AO-A15), 8 data bts (DO-D7), seven bts of control nformaton and a frst event stored marker bt to ndcate the begnnng of the most current trace actvty. The Storage Control logc provdes an address to all eght statc RAMs smultaneously so that t functons as a 256 x 32 bt memory. Although data s stored nto the memory array n quanttes of 32 bts (WR sgnal actve low) t s read from the array n eght bt felds. Ths s accomplshed by holdng the address lnes (RAO-RA7) n a fxed state and executng four Port Read operatons from Port Address FCH, reference subparagraph Address Latches (Sheet 1) Three quad D-type latches (All, A12 and A13) are provded to latch the Address Bus (AO-A15) of the Z80-CPU durng ether USER or MONITOR modes of operaton. The latches are clocked by DATA STB B (actve hgh) whch orgnates from the Montor Module. The latches provde a temporary storage for the Address Bus nformaton pror to wrtng t nto the Storage Array components A3, A4, A5 and A

81 5 (A a Ul xx% k. c* T I cd V X / u) 1s >- 01 a. ^^-«CNJ ro UJ v>». 4XV ^ * x^ CvJ s. \N ADDRESS UATC.HE5 + XV^ b r If) IJj a 1 Ax 1 "s k. CVJ K \/ < ^ \l j q; s v n a ^ /'V k. 4 f ^r (0 cu o I- LL fl CQ US Ul n (T SYSTEM AD 4 K. 1 A 1 fdl SVSTEfA COI\Kd >. 00 la a I \<f yl / s. X»^v ^ ^ ~>3 3DIA3O ^ S a I 4-57

82 4.6.3 Data Latches (Sheet 2) Two quad D-type latches (A18 and A23) are provded to latch the Data Bus (DO-D7) of the Z80-CPU durng USER or MONITOR modes of operaton. Lke the address latches they are clocked by DATA STB B (actve hgh) from the Montor Module. Outputs of the latches are routed to memory components Al and A8 of the Storage Array Control Decode (Sheet 3) The Control Decode logc provdes a method of compactng varous Z80-CPU control bus sgnals before storng them n the Storage Array. Logc s provded by A25 and A27 to AND selected control sgnals to result n a value whch better descrbes the bus event n progress. The source sgnals and resultant sgnals, whch are stored, are shown below. SOURCE MRQ, RD MRQ, WR IORQ, RD IORQ, WR IORQ, Ml RESULT MRD MWR IORD IOWR INT ACK MEMORY READ MEMORY WRITE I/O READ I/O WRITE Interrupt Acknowledge In addton to the aforementoned sgnals two others are also stored whch are BUSAK (A24-pn 3) and HALTA (logc Sheet 2). The state of the aforementoned fve sgnals are latched by a sngle.quad D-type latch (A26) whch s clocked by DATA STB B The BUSAK and HALTA sgnals are not latched because these are sgnals whch have a long duraton when actve and are thus not tme crtcal Data Bus Drvers (Sheet 3) Two bus drver elements (A16 and part of A17) nterface the output data lnes from the statc RAM storage Array to the system data bus. These drvers are only enabled n Montor Mode when an I/O Read s ssued to Port FCH (STOR SEL actve low). 4-58

83 4.6.6 Storage Control Logc (Sheets 2, 3 and 4) The Storage Control Logc provdes two functons: 1) controls loadng of the Storage Array, and 2) unloadng of the Storage Array for software. In order to determne what types of transactons are to be stored n the Storage Array the user loads the qualfer nto the Real Tme Storage Module by executng a Port Wrte to Port FCH whle n Montor Mode. Data bts DO-D3 contan the qualfer whch s strobed nto a quad D-type latch (A19) on logc Sheet 3. The outputs of ths latch are ANDed wth the decoded sgnals MRD f MWR, IORD and IOWR by A20 to generate a wrte strobe WR DATA (actve low) to the Storage Array when runnng n USER mode (emulaton). Latched address, data and control bus nformaton wll then be wrtten nto the Storage Array. Concurrently, the contents of the Address Generator (A9 and A10 on Sheet 4) for the Storage Array wll be ncremented pontng to the next sequental locaton n the array. To read the contents of the Storage Array the system must be n MONITOR Mode and Port Reads to I/O Port FCH must be executed. Snce 32 bts represent one bus event, four consecutve Port Reads must be executed, each transferrng 8 bts to the system data bus. The selecton of whch 8-bt feld s to be transferred s determned by a counter (A22) and assocated decoder (A15) as shown below. 8-Bt Port Read Count Feld Transferred 1 0 LSB. STORED ADDRESS BUS (AO-A7) 2 1 MSB. STORED ADDRESS BUS (A8-A15) 3 2 STORED DATA BUS (DO-D7) 4 3 STORED CONTROL BUS Once four consecutve Port Reads have been executed the counter reaches a full count, decoded as RD CONTROL (actve low) whch generates the READ sgnal (Sheet 3) on the next Port Read to decrement the Address Generator (A9 and A10) on logc Sheet 4. The effect s that the most recent event stored s the second one read, etc. The 3K Debug PROM wll contnue the readng of the data untl t encounters the frst event stored marker (Bt 7 of the stored control nformaton) or the approprate number of user specfed events entered from the system console. 4-59

84 4.7 Mapper/ICE Module The M/ICE provdes the crcutry used to nterface the Emulaton Subsystem logc to the user's prototype va a three (3) foot cable and termnator. Ths module depcted n block form by Fgure 4-20 whch wll be used as a reference for the followng subparagraphs. Essentally, the Mapper/User Hardware Interface conssts of an extenson of the Z80 System bus wth address, data and control fed to the user through trstate buffers allowng n-crcut emulaton Address Decoder (Sheet 2) The Z80 memory address space s normally assgned to exst nternal to the system, as are I/O ports for stand-alone operaton. When the user nterface cable s n place, the address space of the target hardware can be allocated between nternal, system RAM and ROM/RAM and I/O external to the ZDS-1/25. Memory mappng s mplemented as a swtch between nternal and external bus accesses Memory Mapper (Sheet 2) The system clock, orgnatng on the CPU card, s fed drectly to clock swtch logc on ths card, allowng the user to determne the source of system PHI. The external clock s montored for ntegrty and wll revert to system clock n the event of external clock falure. In order to preserve system ntegrty, montor mode operatons are conducted under system clock. 4-60

85 UJ y^o ^ u w 4-61

86 4.7.3 Address Bus Drvers (Sheet 2) Sheet 1 of the schematcs contans recever A02 for user-generated sgnals ncludng NMI, INT, WAIT, BUSRQ, and external clock f selected by rear panel swtch S2. Drver A12 supples BUSAK, HALT, FBI, and system IEO to the cable connector n the event the user wshes to dasychan the development hardware. Also, n the absence of an external clock source, system clock can be suppled wth 75 OHMs drve capablty by selectng nternal clock (S2 ON) Output Control Bus (Sheets 1 and 3) The logc of A23 and A24 comprse a synchronous clock dropout detector to nsure CPU clock ntegrty. The 9316/ drven by system PHI provdes a rpple carry pulse to set Ql every 16 clock perods. Meanwhle, the External clock beng montored s strobng a zero from D to Ql on every fallng edge. PHI dvded by four then passes Ql to XCON meanng external clock s on (actve low). Should external clock fal XCOF (external clock off) s latched low untl power on clear s asserted. Clock selecton s based on several nputs to the clock select logc. Power on clear or an external clock falure wll fcrce the selecton of nternal clock to the CPU. If S2 selects Extenal dlock, then the transston to user mode n the ZDS-1/25 wll be accompaned by the synchronous swtch to user clock. USCPU mode (n whch the user clock drves the CPU always) s selected by a Port Wrte to Port EE (PWEE) wth data bt 7 low. Ths mode s useful when external hardware must reman synchronous to the CPU clock n montor mode. (Jumper A to A to mplement.) A IK resstor provdes lne termnaton for the ncomng clock Input Control Bus (Sheet 1) Sheet 2 of the schematcs contans bus control logc and bufferng for the address and data busses. Drvers A3-A5 provde 16 address bts to the user (unless trstated by BUSAK+). Adder A6 provdes the montor mode offset that makes the system PROM actvty appear to take place between FOOO and FFFF HEX (page 15). In user mode ths offset s transparent to user addresses. PROM addresses from page 15 are decoded by bus control PROM A21. Control outputs TRANS- and RCV+ regulate montor mode 4-62

87 bus actvty (e.g., RETI) from confusng external perpheral devces. Lnkng the nternal and external dasychan would prevent smlar sde effects from RAM resdent system software. Another nput s user bus control. Orgnatng on the montor card UB.CONT requests bus transcevers A7 and A8 to drve the system bus. Ths s contngent upon external port or memory selecton va status Port EE Data Bus Buffers (Sheet 2) Sheet 3 of the schematcs show control bus buffer Al. The opton of dsablng UMRQ and UM1 s provded for memory nterfaces whose bus control logc cannot tolerate Ml or MREQ f memory f that address s mapped elsewhere. System IEO (IE*) s generated by A29 whch OR's the ndvdual leo's from the CPU and perpheral cards. It s the term IE* that should be lnked to user IEI to nsure proper user nterrupt handlng Clock Synchronzaton Logc (Sheet 1) Memory mappng s accomplshed wth bpolar statc RAM A13. The eght most sgnfcant address bts are used to delneate 256 sector wthn- the RAM. A logc one n any locaton represents a sector of nternal memory. Zero represents a request for memory outsde the ZDS-1/25. Ths nformaton s avalable to buffer A28 for nterrogaton va DO on the data bus, though t s ntended for the user memory enable output by way of A32 and A33. Mappng s enabled va data bt Dl of status Port EE. External memory can be selected n ts entrty by data bt D2 of Port EE. External ports are enabled by a zero to data bt 3 or Port EE External Memory A stuaton arses when mode zero nterrupts are occurrng n external memory. By vrtue of the fact that the CPU expects two addtonal memory read cycles n response to a call nstructon durng the mode 0 nterrupt acknowledge cycle, the call vectors returned must be ssued to the CPU durng these memory reads. It s therefore necessary to nsure that external memory s selected n such an event. Latch A36 s set by an external nterrupt acknowledge, and s subsequently cleared by the resultng wrtes, caused by the PC beng pushed 4-63

88 onto the the stack. Snce ths occurs for all modes of nterrupts, regardless of mode External Clock Data bt D4 represents the clock functon: external clock avalable. Note that ether S2=ON or an ext. elk. falure causes D4 = 1. Programmng the status port s done smply by selectng the functon wth actve low bts (see table above). Once programmed the functons wll reman selected untl POWER ON CLEAR s asserted. As a convenence, the opton of all external bus can be nvoked by a PWEE wth data bt 0 low. Ths causes Dl, D2, and D3 to be stored low n the status port, and all accesses are consdered external. 4-64

89 TABLE 1 I. FEATURE OVERVIEW Readable Clock Integrty Detector PREE-D4 Select Internal/External Select Internal/External Ports Memory PWEE-D3 PWEE-D2 Dsable/Enable Memory Map PWEE-D1 Readable Memory Swtch (SO) Readable Clock Status (SI) Readable Memory Map Mode 0 Interrupt Fx PREE-DO PREE-D4 PREF-DO Embedded System IEO (IE*) Avalable II. FUNCTIONS SWITCH FUNCTION STATES BIT PORT READ WRITE 50 ON Internal Bus = INT DO EE 1 X 51 ON Internal Clock Drve D4 EE F. X SO OFF Ext Bus Envronment Enable Mapper 0=ON Enable w/ext Ports DO Dl D1,D3 EE EE EE 0.c.4.E=EXT BUS.D.5 EXT Memory EXT w/ext Ports 0=EXT D2 D2,D3 EE EE.A.2.B.0 EXT Ports 0=EXT D3 EE.6.7 SI OFF EXT CLK Envronment D4 EE E. X CLK Integrty 0=OK D4 EE E. X 4-65

90 TABLE 2 The btmap mplemented n ths revson ( Rev. 4) of the Mapper/ICE s as follows: R F T P R T P 0000 OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OOAO OC OC OC OC OC OC OOBO OC OC OC OC OC OC OOCO OC OC OC OC OC OC OODO OC OC OC OC OC OC OOEO OC OC OC OC OC OC OOFO OC OC OC 05 OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC AO OC OC OC OC OC OC BO OC OC OC OC OC OC CO OC OC OC OC OC OC DO OC OC OC OC OC OC EO OC OC OC OC OC OC FO OC OC 05 05( OC 05 OC 05^

91 4.8 MONITOR MODULE The Montor Module provdes several dscrete functons for the system and plays a prmary role n the control of the Emulaton Subsystem. A block dagram s provded by Fgure 4-21 whch may be used as a reference Panel Interface (Sheet 1) The Panel Interface logc s shown on Sheet 1. It conssts of the MONITOR and USER, HALT and WAIT ndcators located on the front panel of the system. The outputs from the MONITOR and USER latches are routed to the System Status Buffer (A27) and to the Mode Select Logc on Sheet

92 r t a o a In a rn 2 3 t RESTART \\ V V J d^ 1 C U. J \\ 1 A It t k ^ OJ MMM L * & «ft* te- /) UJ j Q fej 3 cj s^1 UJ a r Q Of W 3 (0 j o en u a cq J j. 1 uj <y Sry g 1 H <- h UJ c^ a 2 t LU * ~~ ^ I O D - II SS (0 a CJ a, w In Ul en OJ I LL j 2 1 <_ *» ) 5 If > 2 M k «e» ^ H I \ t ^s u^ a < c ^N D 3 Q C * jx / / V \ CO ^ _j * c C a 2 5 If! I J 0 A f * X -68 ^S.IS tf 2 %

93 4.8.2 Instructon Decoder (Sheet 3) The Instructon Decoder serves to montor the system data bus to nsure that only a sngle Ml sgnal (MIS) s generated at the begnnng of each nstructon. Durng mult-byte nstructons Ml s generated for each byte accessed from memory. Ths stuaton s undesrable for emulaton control therefore the combnaton of A28, Al, A2, A3, A8, A9 and A16 provde the necessary logc to enable the generaton of Ml (MIS) for the frst opcode fetch of a double byte or trple byte nstructon. The resultant output (MIS actve low) s routed to the Mode Change Logc (Sheet 1) and the Mode Select Logc (Sheet 2) to nsure the transton from USER to MONITOR mode or vce versa occurs n a manner whch synchronzes t wth Z80-CPU nstructon fetch Mode Change Logc (Sheet 1) The Mode Change Logc provdes for the mode transton synchronzaton caused by operator depresson of the USER or MONITOR swtches, or a Breakpont (BREAK actve low). The detecton of the mode change s reflected mmedately by A14 pn 5, then synchronzed wth MIS (prevously descrbed) to generate FORCE NOP. Also generated, when the Z80-CPU reads the next nstructon from the data bus, n NOP (actve low) whch gates a NOP (OOH) onto the data bus to the Z80-CPU va A21 and part of A29 (Sheet 3). At ths same tme RESTART D (actve low) s also routed to the RTSM to prevent the wrtng of the NOP nto the RTSM. The CHANGE MODE CLR (actve low) generates SYS RESET (actve low) on Sheet 2 and SYS CLR, whch resets the Mode Change Logc (A14-1) NO-OP Generator (Sheet 3) The NO-OP Generator serves to place an all zeroes byte (NOP) onto the data bus nputs to the Z80-CPU when a mode change or breakpont occurs. The generator s merely a bus drver whose nputs are grounded and these are gated to the data bus when the NOP (actve low) sgnal s generated by the Mode Change Logc. 4-69

94 4.8.5 Mode Select Logc (Sheet 2) The Mode Select Logc s composed of two flp-flops (A18), a latch (A31) and assocated gatng logc (A10, A17). Ths serves to detect the depresson of the MON or USER Mode by the 3K PROM frmware. Detecton of one of the above condtons s reflected by the latch (A31) whch s then synchronzed by MIS to set A18-pn 5 followed by A18-pn 9 on the followng MIS. The result s the generaton of MONITOR (ether actve hgh or low) whch s routed wth ts nverse to the system Breakpont Module, CPU Module and Real Tme Storage Module System Status Buffer (Sheet 1) A status byte contanng system status s provded by a buffer A27 on logc Sheet 1. Ths may be read by executng a Port Read command from I/O Port FEH. The status byte defnton s shown below. 0 L Not Used Sense Swtch 2 Break Status Sense Swtch 2 Sense Swtch 1 Montor Swtch User Swtch Not Used Port Address Decoder (Sheet 2) The system I/O Port addresses are decoded (Sheet 2) by A30 and A32. Ths "centralzed" decode functon mnmzes the number of select lnes whch must be routed to the varous boards n the system. The port assgnments for the system are shown n Table

95 Table 4-3. System I/O Port Assgnments Port (HEX) FO Fl F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Devce Counter-Tmer Port Counter-Tmer Port Counter-Tmer Port Counter-Tmer Port USART Data Port USART Control Port Dsk Data Port Dsk Control Port B Dsk Control Port A Breakpont RTSM System Reset or User System Status Port Seral Latches Mode User Data Bus Control (Sheet 3) Logc Sheet 3 contans the user data bus control sgnal whch s appled to the User Interface Module to control the drecton of the bdrectonal data bus drvers for the data bus nterface between the user's prototype and the development system. When the UB CONT sgnal s actve low the data bus drvers are set to receve data from the user's prototype system, when hgh the drvers place data from the development system data bus onto the user's data bus n the prototype. The UB CONT sgnal may be generated shown below. n one of three cases USER MEMORY ACCESS (READ): Ths event s sgnaled by USER MEM ENABLE (actve low) from the memory mapper logc on the User Interface Module. The MREQ and RD sgnals further qualfy the logc (All and A5) to generate UB CONT (low). It s mportant to note that the USER MEM ENABLE (low) serves to dsable MRD (actve low) preventng system memory access. 4-71

96 USER I/O PORT READ: Whenever I/O Port Read (IORQ logcal zero) s executed from any devce other than Port addresses EO-FFH (DEV E+F logcal zero) the UB CONT sgnal wll be generated. Ths s also true for MONITOR mode but the MON DIS sgnal serves to dsable the bdrectonal bus drvers on the User Interface Module. INTERRUPT ACKNOWLEDGE CYCLE: When the Z80-CPU enters an nterrupt acknowledge cycle (IORQ and Ml actve) the nterruptng devce can place an eght bt vector onto the data bus. These two sgnals are qualfed by IE (from the lowest prorty system devce) to dstngush between user nterrupts and system nterrupts. The IE sgnal s derved from the IEO lne of the lowest prorty nterruptdrven devce, usually the Counter-Tmer Crcut on the SCON Module Console Interface Recevers/Drvers (Sheet 4) The actual recever and drver crcuts for both the 20 ma. TTY console nterface and the RS232C nterface are shown on logc Sheet 4. Ths crcutry provdes the transmt and receve sgnal nterface between the SCON Module and the console connector on the rear of the system. Other pertnent RS232C sgnals are provded drectly by the SCON snce they are not used for 20 ma. current loop. 4-72

97 APPENDIX A CPU SCHEMATICS

98

99 lp) I'M!?}! H -. f ^ <

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101

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103

104 I! 3 O J -' o UJ UJ 50 vj *3 /t> /N» «(» fj ~ flf~\jlf* ft n <n «o jr fl «o «. / ^ / >> / v / S / S >> X M O a. lo 0 a 0 U O a \ / M O 0 ft 0 0 I* A ^E a 1 r n X ^ 6 0 a!! ' l'j'll" < uh ) 5N o f f 11 5 ~T - 1 U H" * ft ^ <* j r ^ rs *" S 2 (T fs S r (a ^ f^ s <; U Z ^J r u O Q > O VJ ft *«o, 0«- ss A^ t- - «J a 5 ^ 3 A O j

105

106 [ '--, of 3? N Oft. I6I«T 51 s 58?» ll< f!>nn

107 APPENDIX B 64K MEMORY MODULE SCHEMATICS

108

109 $5-2 ffl-5. SI s auj f*^ t ^ so ll! uh! ' H * <* Q E? * w» -HI p»,h!, ft; tl! If P* ll! I* K E B 8 \ Xs / \ ^\ / S S S 5> H ho R IS a. 1 IU O 2 I. P ll \ / N / S v' N «- O T t «a IX K> ft H T T v( / N I 3 S X ^ N 3 k /V /\ f\ S ~ J ^* "" * *c ^ «* ** «^ ^ o - -. "> «O J : ' \ \ : *. S,N *

110 B.J > * V t [. c J J** M^ M " Jg f 1 j j 5 0! 0 1^ B 1^sd J ««t «rt* " ^ fj ^TW, ^ 1" 0 O 5 r*» UJS, -?'Ll t ^3!^ ' ^ 1 P } 1 '-t 5 1 II * -j*" ll -; ll 9 < s 1 t «> V > \ c k» «Q e 0a a o o o jrt a o a -. o s o a a Q a a 8 p» a r" 8» - ft kl «+ 1 «^ S j* f? < = f! 4 r- _ ^ ^ O ^o r (0 H- J 0 fl -j r S^ ""^ 10 *J g r S d H' «: c > : *y <t a r I r ( a^ «4 rf * r* 13 r 2 r 1? ; a ^ ^ 5 r «4I* 1 r t sul«ml -4 ^ 2 0 tf 4 fl r- j f! : n a 4 «<o ^ ^ 1 fl * (*1 ^ * J r- «c " * - 0 s! * ± fl _ ^?- * H '. 1 g Iu! 1 1! 9- Q fn? { -? g V / ^ ; (0 y ^! *o f \ r r ^ S \ <?» / ^\ ^ \ g / \ r4 I1,- s. "\ /\ A^ / > «: - _ v / o- P/ e ^ \ /^x / \ / ^ /. r- ^h a3 t?» «\ j; J I -, 41 *< j I k ^ ^. UrfX j H \ / N ^N / rfl I r pa \ " \ P 'O < \ / r < r c < f 3 ^ J ' "I * 5 S 7 1 " 1 j j 1 )] j!

111 r S 7 HH» A, 8» ' " s '? ** - 1 <j 2 &. N A 8 4 g 4 ^a A ^ 1 s«< j _ 4 ^ _. f 2 3. d tu 5 <0 «8 ^3 8 * OL 2 r 8 r* 1! * * I I E I!! ^9 r H. 1 ^ 11 I 1 I O 0 _* 3 u ^ s l cvj» ** ^ 1 t J ss f*?^ 0» 0" 1 rt j ~ I SQ ] \ h^!!hj «SH I 1 ± S J d lt J l * ^ (J J -1 + ~] D...J 2 M a * a) n 5 > n. J r 0!C 4- "1 1 tj * *J S 1 * (j Q!T * o ḟ ISl A Q n ^ ', T N_ O r ^ n >J Q! j n r~ Q S,J S I 3» S 4 «r 1 r - o * T r VI S 3» tf 7 I - t Q. - r f g ?,L * 1 F * ^M O - ' X * SL 4 H c. ' 2 pj * (J f\ s- -* 2 ^s 2 _ a f^ ± 5 ± ^ ] v3 <J v> d ^ «"~~ U r * I =1 I or Q ts or 0 cr S 9 «* n r 0 Q - LA r So p Iv PllX J 1 z \ * V 1 ^ ^ : -J 4 I J d 1 ll

112

113 APPENDIX C FLOPPY DISK CONTROLLER SCHEMATICS

114

115 t U] J J 0 x II a 5 j >-. L 0 N u 7 h4 Q -Jl SI f# III 5^5 «Zx A '^ n L-SO o a d u. \ I La- oo- ^u a " U 3. ^rrtl r,z 10> *Cr- S_ Q J4: u ' <* «nu. Q 2? 3' 1 Hf ^' o * * W M s-" U. - a U w ~» 1(11' -0 ^ ' u UV^V I'll < BJvJ,O ^» ' I I ' I»I s-ssjaafll ^y SI 8

116 J 0 - *j? o 2Q K s. m Q > VJ O 9 $ <:J *. «^ n *» C3 C3 o " xl 1. 4; '/I N ^ r- a? ^ 9Q Q '^4 P r? : ~ n j w S5 Q -^ rrt ^ ul 23 «^3 a u u H 31 II' v> * m t. I 1 N 32 r»» d m!-_ j! 0 \j a QJ 33 Q G S Q I 1 1 I 1 3l Q Q n fl,1 n ^ n c \J j ^ 0) T ] C n a S a < 3{ n >» ) ^) } (J a M? 0 w. U.I a H - T T H K W / U Q UJI n c ).. f j 1*1 INI jy S! t 1 0 ft* 1 J a. vj " <J ' ' ^ u Ifl O '^1"<^ W vj VJ 1 1. ^ <n. 1 Q Q N G Q Q S a 3 1,, js ' fo ' S^ - I I ll I I /^ fl >»I AO:

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118 (L 0 f!!j Tll,, s.» 5 1 1!

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122 V

123 APPENDIX D MONITOR SCHEMATICS

124

125

126 s: 1 4* 0 < Q 1r f \r " s 1! «? 3! ^ 4 & I C Q C? s- & I? J J! I ^ * J! _\ < I 5 L LOGIC DIAGRAM MOMITOR.2^ 2 &j*.& ;3 jiss!» 3 1 1! 3 3» z U M k 3 \! \ 4 \ rn t (\ c t a \ \ \ f l'r 1 M '! n a I] {.! : Ht Qo u? [~ f[ O(»[ u>[ g[ «v«r> 3 = «. g $s?s -L L ' OA vo a- r o M t f f f «J. 1 -»->-» T

127 1- < u a CM at 10 IN?

128

129 APPENDIX E USER INTERFACE/MAPPER SCHEMATICS

130

131 1- - (» > > - - t t a I '' r } t A ^ 5 x»» - c / t* «t rx \T v> zrf" > r f 1 >n ^ T, * A» r * - c r 5 ^3D n r- c-t * I* <. u ^ «>»> ^ W? H?^r* 51 s O a J r* * d u -<! 1^ / -J H 1 m a 3 / r ft g <o r-^o j ol a. HI c Y u o a ~> <-.j r IB a L8- J zit I.. x kaout OR 1 '" ' 1 Ct \! t\ 5 s C» \* f.^ A- l^r O T T «I'M 0- r"' r 1 \ 1 4 ( Q _j '? r 1 rt >* C y I 2 rf> 1 ^ n 5 2!g ^ / 5 / 1 V 1 r\. f «5 ^ N / r B I «0 1 e- 1 r- r S ^ ^ ^f 1 ' ' v uw-rrr C ^ r *3 ^r> ^ 5 Q l CslY * ~[_ -O7a<an x 1W I X «1 N _ fj rfl * h * n ^"' t< If r» < / t- r) ! K "^H v k ^ 2- J'«f^ > ^» 1 It «.r>p v. rj s- X l 1 A. 3 O j r 5 Q! / j T j! ^ «3 cf> f 41 tu \ f f L. 1 ^) ID * /\ AN / N y\ n rt 1 rj - * a rj ( 5 I C / t < y ^ 5 ^o r> at <..» 7<» r ^I s * * T ^a 01 I cjc IT 5 ^ (,4 r 1 f r v < o «O ^^ 1 H o "'- I" «o- 1 ^1-$ fc- VA a>? U1 ' f r* 5» ^^ < t>^ ~ r._c/ ^Sf «? -J IV 3 55 s ^ ou ^ & ^ s" -J / o oq =T rfl -s «^ Io -r» H!j u xt III HI' f f { r sr* ) k c* ** T«*«^ *!» t ^ t / ^5 E / 2 cr ^ >w *' 1 V y r - A <* H r* ct r J2o ^ >a ->^ r ^ ^ 1 sa ID a C > XV = ^ a O 5 «? o- _j, c* - H /^v ~js <^ /O\ -l a «:" w,_ " >< o- ~!^en o - =U r*7, o ^ «^ «# 0 = o j a T V I ~1 0 *» ^ S9] ^d s t* 3 v» >t a ^ 1 «J»- / f 1 ^«c< 'J> /! s * -^=4l 5K «^s m» n a" Q = a ju j u^ s Q r 1 f / c >.a e *3? s «? -T^ C A 1 (TO, *t /t^<0\ M«Q\ Ut^ j v "7 a - 2 n ^ POvtJtR cxj CLB - 9 Sj * * v» v«/n /fv 1 U1 s AL2-5J (?S - 4 v ^ n S? *> 0 ^ = j XV /%\ rf>«l -pj5j LP -*! jf 8l ^ IT- N9. 9 t Sl l <3 * S* «> f H ^ <0 A r<»»<* <? N A«# Y Y a 'T 1 -nnjd^n 4 LMS I ^BVHMWH 1 =1?^ ' = < j! 1 j 5!^ 5 3 «S 5! u, o? Q S O : o N? _J -^: * ~ H:!L r> * 1 -H t l! 'l. l!-.j a! :! 1 jl H. ^qtn r^ r"s 3^ S * I * a. S! 0. u. "»T USE«. luterfac S I : s- V s?i s r 1 o o 0 fv 8" fo! w O o N S n O rw rff.m III MI 1 ' f» ME ^ I. N n n (0

132 \ I ^Jl- ^ D ; s? * I l cg,c DtaeAh, 5 H 8! 31 o I :. l! HS ; l!n r? a I 3 I H ^ US K. WTE^fACE./MAPP&2 tut \»*w»o MU 1 *«* 0 DZ-OIO4-OZ 4 «o^ NONE 1 I"" 1 " "}a ' 1 -t*" h! $ <? :? f -» s - f <? ; 2 * a : 2 * s f & 2 * r> x < 3. u <o ^ B> ;s _» < j : 81 1 rf e 5 "" *< j 3 ** :^. s,.! St * 0 < > \ V* w? «h t ) - «I C 9 A CO <r S *(T I- ^ ft 3 r» a* (T I 1!! j» exj r -- c 3 Q c T ^. «' S a X < 1 ES <> cj t frv ^ c 1^3cSc < c<t VI v9 rr << a > (A H' <* t t l- ^ r' U> 1 J *! ~ y ^ - ^ g = -a d c ± <«r* UN - - Jten r J 1 *^ cr r O * = «c ± j t_ * ^ o / ^ - I- «I - n 9 = r- c * * u ^ = 2 13 as^s3 J» t S rt * (T 3 4 >/> J*~ ' r* Mr~ -' «0 o o e ' a - ~ r- ^ >n t\ _ c K «* f (0. 9 a! S rs J- r: ^ > ** «^ 1 1 ' * 17 * ^. <o - «-I * > aa * r~> C -4 w4 * 4 1* 9 : t 3= = fw * 1 r * 2 r; S- «* 1' M ' r* 4 / /t. \ \ r,! ]!' j. 4 /I 15.' * j * pj Q»^ I I! or\ f 1$ 3 ~* rj fv S" N / ' S / k. Jk J? c; 3 < «2 ^ T >* l ; ^ 4! c >n 4 ^» n & 0 e- or-.. / - : v / ^* s 0F- < 3 - h s I k ; J f V 3 r <r a e n -j 1 1 T 1,0 / s 1 5r» yy 5 ^. 5 w- r<^ I'll* " y = f^ 1 I -w 1 ORUVR- o. A BUTTON 1 J>^ 4 / (t tq ' 01. T t 1 0 t- -7 n 0 u o ). f - t ( a) >-( >M s- -s /\ N XV / v / S 1 _ c^ pc\ ^ - ^j h- 4 - v- ^1«? f> «? 3 T JJ A U S n <NJ ^ rf> w v(n r* U3 - ^r ««r * (- s ^ X s, xn X^ ^. J ; > s "1 J H! <v ^ r- *~ ^

133

134

135 APPENDIX F BREAKPOINT SCHEMATICS

136

137

138 9. t 2! I ^<C UJ MI! 5 2'l 2U uf 0 y. 2 o v/l Ml N «). ll ll. 0) [fs 1 r~ fl 0 cflq (G & "tln 00^Q 0 I f' u 0] $S ul 3ft S ^. <, t»

139 2. LU tt CO 5 =f s - o u rs s -. " III 25? - m»!;! «* l!!! o 11. o Io 1 s

140

141 ll " * e ;ls I s UJ tt CQ t Il UJ 8.2? H a >j o j \ js 0 w rn m 2 $s s r~ M?s <r n vu 9S p «j f) M r- «ll) Q U 33 0 VJ er N 4 0 ro g»t 0 ^ N. ^ «^ a * 4 r- m n <j - Q rt) ul < a u E UJ Ifl Q '1L j t [Q Q I d) Q Q, 0) Q j KJ ll t Q 0 UJ B / > KJ UJ B * Ul k, ^ CO Q I 00 ul Q J k c. L 9] r- 0 j ss ^ I- X JO, t-!r H T I I n <o <rt p

142

143 APPENDIX G REAL TIME STORAGE MODULE SCHEMATICS

144

145 K N AAAAAAA dd tfl ff: ooq CQ (fl CQ fjr I I r=f<!o!_ tf fflsstlvj o I I g dl 3 1 vfl le 0 < fj fl (2 u}j = rt N I 55 _j ffljuji * 1 I ' ll t I- fl n 1 Wl

146 (Tl I- 1^- >n n - "^«AAAAAAAA *-r 2 s 0 ft a> Q - N ^KJ _(SI ^ 355 <t< 0 30 I s " "3 ^ U ^? V 0 7 N I AA AAAAAAAA ftf 55 In AAAAAAAAAAAAAA A 35

147

148 s B 2 e H 1^5 H ^-1 'lt I* 3 ; :.-. NM/ A 1 n v3 111 n 1 V, m N *(^ -f ^ Q 5 u =v «ft to o Q a m 4 «la t- n t

149 APPENDIX H PCB LOCATIONS FOR THE ZDS-1/25 s..

150

151 PCB LOCATION FOR THE ZDS-1/25 REVISION CONNECTOR PRINTED CIRCUIT BOARDS J01 J02 JOS J04 JOS J06 JOT JOS J MAPPER-ICE MONITOR.25 FLOPPY CONTROLLER BREAKPOINT2 RTSM RTSM2 CPU2 6OK DYNAMIC RAM 6OK MEMORY.25 16K STATIC RAM (CARD 0) ZDSP CIB 16K STATIC RAM (CARD 1) ZDSP PPB PPB16 RXB 16K STATIC RAM (CARD 2) I/O CONNECTORS J13 J14 J15 J16 J17 J18 J19 J20 J21 J25 J26 FLOPPY DRIVE CABLE (50 PINS) CONSOLE CABLE AUXILIARY SERIAL CABLE USER INTERFACE CABLE #2 USER INTERFACE CABLE #1 SPARE (USER DEFINABLE) PROLOG PROM PROGRAMMER CABLE LINE PRINTER CABLE (ZDSP) FRONT PANEL CABLE POWER CABLE REMEX PUNCH-READER CABLE (50 PINS) H-l

152 PCB Locatons (cont.) REAR PANEL CONNECTORS J100 SYNC PULSE PLUG (BNC) J101 REMEX PUNCH J102 REMEX READER J103 LINE PRINTER (ZDSP) J104 PROLOG PROM PROGRAMMER J105 USER INTERFACE CABLE #1 J106 USER INTERFACE CABLE #2 J107 AUXILIARY SERIAL PORT J108 TERMINAL INTERRUPT DAISY CHAIN IE0.1 (IEO.1,2,3) IE0.2 IE0.3 J06 J01 JOS J09 CPU2 (CTC) MAPPER-ICE CIS, ZDSP.l ZDSP.2, PPB (PIO PIO, CTC) (PIO, CTC) H-2

153 APPENDIX I BACKPLANE DEFINITION FOR THE ZDS-1/25

154

155 BACKPLANE DEFINITION FOR THE ZDS-1/ REV SYSTEM=ZDS.l/25 GEOMETRY= (ZDS-1/25) SLOTS= J01 J02 J03 J04 JOS J06 J07 JOS J09 J13 J14 J15 J16 J17 J18 J19 J20 J21 J25 MICE.PIN MONITOR.25.PIN FLOPPY.PIN BKPT2.PIN RTSM2.PIN CPU2.PIN MEMORY.25.PIN ZDSP.l.PIN REMEX.PIN ZDSP.2.PIN PROM.PROG.DS.PIN FLOPPY.CABLE.PIN TTY.CABLE.PIN ZDSP.CABLE.PIN M.ICE.CABLE.2.PIN M.ICE.CABLE.1.PIN ZDSP.2.CABLE.PIN PROLOG.CABLE.PIN LP.CABLE.PIN FRONT.PANEL.CABLE.PIN POWER.CABLE.PIN STATIC.MEMORY.PIN CARD=0 STATIC.MEMORY.PIN CARD=1 GIB.PIN PIB.PIN STATIC.MEMORY.PIN CARD=2 1-1

156 Backplane Defnton (cont.) J26 REMEX.CABLE.PIN (REMEX.READER.CABLE.PIN) (REMEX.PUNCH.CABLE.PIN) 1-2

157 BACKPLANE DEFINITION FOR THE ZDS-1/ REV SYSTEM=ZDS.l/25 GEOMETRY=ZDS.1.GEO NETS= +05V V V.1 +12V.2 +12V.3-05V.1-05V.2 J J J J J J J J J J J J J J J J J J J J J J J J J J

158 Backplane Defnton (Wre Lst) (cont.) -5V.12 8.PHI AGO A01 A02 J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J

159 Backplane Defnton (Wre Lst) (cont.) A03 J J J J J J J J A04 J J J J J J J J A05 J J J J J J J J A06 J J J J J J J J A07 J J J J J J J J

160 Backplane Defnton (Wre Lst) (cont.) A08 A09 A10 All A12 A12 + J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J

161 Backplane Defnton (Wre Lst) (cont.) A13 J J J J A13+ A14 A15 AAO.LP.RX AA1.LP.RX AA2.LP.RX AA3.LP.RX AA4.LP.RX J J J J J J J J J J J J J J J J J J J J J J J J J

162 Backplane Defnton (Wre Lst) (cont.) AA5.LP.RX AA6.RX AA7.RX ABO.D1.LP.RX AB1.D2.LP.RX AB2.D3.LP.RX AB3.D4.LP.RX AB4.D5.LP.RX AB5.D6.LP.RX AB6.D7.LP.RX J J J J J J J J J J J J J J J J J J J J J J J J J J J J

163 Backplane Defnton (Wre Lst) (cont.) AB7.D8.LP.RX J J J ABS.LP J J BAO.DIN.l.PP.RX J J J BAO.DOUT.l.PP J J BA1.DIN.2.PP.RX J J J BA1.DOUT.2.PP J J BA2.DIN.3.PP.RX J J J BA2.DOUT.3.PP J J BA3.DIN.4.PP.RX J J J BA3.DOUT.4.PP J J BA4.DIN.5.PP.RX J J J

164 Backplane Defnton (Wre Lst) (cont.) BA4.DOUT.5.PP J J BA5.DIN.6.PP.RX J J J BA5.DOUT.6.PP J J BA6.DIN.7.PP.RX J J J BA6.DOUT.7.PP J J BA7.DIN.8.PP.RX J J J26-Q45 BA7.DOUT.8.PP J J BAR.PP.RX BBO.PP.RX BB1.PP.RX BB2.PP J J J J J J J J J J J

165 Backplane Defnton (Wre Lst) (cont.) BB5.PP.RX BB6.PP.RX BB7.RX BKPT.SEL- BNMI.SW- BREAK- BREAK.STATUS BREAK.SYNC BUSAK- BUSRQ- J J J J J J J J J J J J J J J J J J J J J J J CARRIER.DETECT J J CARRIER.DETECT.2 J J

166 Backplane Defnton (Wre Lst) (cont.) CD.O- J J CD.l- J J J CD.2- J J J CD.3- J J DO J J J J J J J J J Dl J J J J J J J J J D2 J J J J J J J J J

167 Backplane Defnton (Wre Lst) (cont.) D3 D4 D5 D6 J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J

168 Backplane Defnton (Wre Lst) (cont.) D7 DATA.STB DIRECTION.F J J J J J J J J J J J J J J DISK.CONTROL.A.PORT- J J DISK.CONTROL.B.PORT- J J DISK.DATA.PORT- J J EXT.PHI FORCE.NOP J J J J J FORCE.NOP.DLYD J J GND J J J J

169 Backplane Defnton (Wre Lst) (cont.) GND GND GND GND GND GND GND GND GND J J J J J J J J J J J J J J J J J J J J J J J J J J J

170 Backplane Defnton (Wre Lst) (cont.) GND GND GND GND GND GND GND GND GND J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J

171 Backplane Defnton (Wre Lst) (cont.) HALT- HALT.LAMP- IE* IE0.1 IE0.2 IE0.3 INDX INDX.O- INT- J J J J J J J J J J J J J J J J J J J J J J J J

172 Backplane Defnton (Wre Lst) (cont.) IORQ- LOCAL.MODE LOCAL.MODE.2 Ml- M1RQ MDIS- MONITOR MONITOR- MONITOR.LAMP- J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J

173 Backplane Defnton (Wre Lst) (cont.) MONTR.NC MONTR.NO MRD- MRQ- NMI- J J J J J J J J J J J J J J J J J J ORIGINATE.MODE J J ORIGINATE.MODE.2 J J PHI J J J J J

174 Backplane Defnton (Wre Lst) (cont.) POWER.ON.CLR- PS.O- PS.l- PS.2- PS.3- RCV.CLK RCVR.OUT- RD- J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J

175 Backplane Defnton (Wre Lst) (cont.) RDY- READ.DATA- REFRESH- RESET.SW- RESTART- RESTART.D- RING.IND RING.IND.2 J J J J J J J J J J J J J J J J J J RS232.DATA.IN J J RS232.DATA.OUT J J RS232.RETURN J J

176 Backplane Defnton (Wre Lst) (cont.) S2.46MHZ SEL.O- SEL.l- SENSE.SW.1+ SENSE.SW.l- SENSE.SW.2+ SENSE.SW.2- SENSE.SW.CLK SENSE.SW.MEM SERIAL.IN SERIAL.OUT STEP- J J J J J J J J J J J J J J J J J J J J J J J J

177 Backplane Defnton (Wre Lst) (cont.) STOR.SEL- SYNC SYNC.2 SYS.RESET- TCTS TCTS.2 TDSR TDSR.2 TDTR TDTR.2 TERM.BUSY TERM.BUSY.2 J J J J J J J J J J J J J J J J J J J J J J J J J J

178 Backplane Defnton (Wre Lst) (cont.) TRK.OO- TRTS TRTS.2 TRXD TRXD.2 TTXD TTXD.2 TTY.DATA.IN J J J J J J J J J J J J J J J J TTY.DATA.OUT J J TTY.IN.RETURN J J J J J TTY.OUT.RETURN J J UAOO J J

179 Backplane Defnton (Wre Lst) (cont.) UA01 UA02 UA03 UA04 UA05 UA06 UA07 UA08 UA09 UA10 UAH UA12 J J J J J J J J J J J J J J J J J J J J J J J J

180 Backplane Defnton (Wre Lst) (cont.) UA13 UA14 UA15 UB.CONT- UBREQ- UBUSAK- UDBO UDB1 UDB2 UDB3 UDB4 UDB5 J J J J J J J J J J J J J J J J J J J J J J J J

181 Backplane Defnton (Wre Lst) (cont.) UDB6 UDB7 UHALT- UIE UINT- UIORQ- UM1- UMEM- UMRQ- UNMI- UPHI URD- J J J J J J J J J J J J J J J J J J J J J J J J

182 Backplane Defnton (Wre Lst) (cont.) J J J J J J URFSH- URST- USER.LAMP- USER.MEM.ENABLE- J J USER.NC USER.NO UWAIT- UWR- WAIT- WAIT.LAMP- J J J J J J J J J J J J J J

183 Backplane Defnton (Wre Lst) (cent.) WR- WR.DATA- WR.PROT.O- WRITE.GATE- J J J J J J J J J J J J J J J

184

185 APPENDIX J PINOUT CHARTS

186 CONTENTS PINOUT FOR "MICE" BOARD ( ) J-l PINOUT FOR "MONITOR.25" BOARD ( ) J-4 PINOUT FOR "FLOPPY.PIN" BOARD ( ) J-7 PINOUT FOR "BREAKPOINT2" BOARD ( J-10 PINOUT FOR "RTSM2" BOARD ( J-13 PINOUT FOR "CPU.2PIN" BOARD ( ) J-16 PINOUT FOR <MEMORY.25.PIN> ( J-19 PINOUT FOR "STATIC.MEMORY.PIN" BOARD( ) J-22 PINOUT FOR "ZDSP" BOARD ( ) J-25 PINOUT FOR "ZDSP.2" BOARD ( ) J-28 PINOUT FOR "CIB"BOARD ( ) J-31 PINOUT FOR "PIB" BOARD ( ) J-34 PINOUT FOR "REMEX.PIN" BOARD ( ) J-37 PINOUT FOR "PROM PROGRAMMER" BOARD ( ). J-40 PINOUT FOR I/O CONNECTOR "FLOPPY.CABLE.PIN" J-43 PINOUT FOR I/O CONNECTOR "TTY.CABLE" J-45 PINOUT FOR I/O CONNECTOR "ZDSP.CABLE.PIN" J-46 PINOUT FOR "M.ICE.CABLE.2.PIN" J-47 PINOUT FOR "M. ICE. CABLE. 1. PIN" J-48 PINOUT FOR I/O CONNECTOR "ZDSP.2.CABLE.PIN" J-49 PINOUT FOR I/O CONNECTOR "PROLOG.CABLE.PIN" J-50 PINOUT FOR I/O CONNECTOR "LP.CABLE" J-51 PINOUT FOR I/O CONNECTOR "FRONT.PANEL.CABLE" J-52 PINOUT FOR I/O CONNECTOR "POWER CABLE" J-52 PINOUT FOR I/O CONNECTOR "REMEX. CABLE" J-54

187 PINOUT FOR "MICE" BOARD - # J01 PIN # Ol SIGNAL NAME (+05V ) (+05V ) (+05V ) UMRQ- URD- UWR- UINT- UWAIT- A06 A07 A08 All A10 A09 AOO A01 A02 A03 A04 A05 BUSAK- 8. PHI PHI REFRESH- POWER. ON HALT- MI - MRQ- IORQ- UA08 UA09 UDB7 UA12 UA13 UDB3 UDB4 A13 A14 A12.CLR J-l

188 Pnout for MICE Board (cont.) 043 A WR- 045 RD- 046 MONITOR 047 D4 048 D5 049 UIE 050 RESTART- 051 D6 052 D DO 055 Dl 056 D3 057 D2 058 S2.46MHZ 059 (+05V.1.059) V V GND GND GND UIORQ- 066 EXT.PHI 067 URFSH- 068 UM1-069 UNMI- 070 USER.MEM.ENABLE- 071 UBREQ- 072 URST- 073 UMEM- 074 UAOO 075 UA UA IE IE IE GND GND UA UA UA UA UA UA10 J-2

189 Pnout for MICE Board (cont.) 093 UAH 094 UDB5 095 UDB UA14 UA UDB UDB1 101 UHALT- 102 UPHI 103 UBUSAK UDBO SENSE.SW.CLK (OUTPUT LEVEL) SENSE.SW.MEM (OUTPUT LEVEL) BUSRQ- 108 WAIT- 109 INT- 110 NMI- 111 UB.CONT- 112 IE* 113 BNMI.SW- (NMI OR "BREAK" BUTTON) 114 SENSE. SW. 24- (ENABLE SW.EXTERNAL CLOCK) SENSE.SW.2- (ENABLE SW.INTERNAL CLOCK) SENSE.SW.n- (ENABLE SW.EXTERNAL MEMORY) 117 SENSE.SW.l- (ENABLE SW.INTERNAL MEMORY) GND GND GND J-3

190 PINOUT FOR "MONITOR.25" BOARD - # J02 PIN # SIGNAL NAME 001 (+05V.PRINTED.DISTRIBUTION) 002 (+05V.PRINTED.DISTRIBUTION) 003 (+05V.PRINTED.DISTRIBUTION) HALT.LAMP- 006 MONITOR.LAMP- 007 WAIT.LAMP- 008 USER.LAMP- 009 A A RESTART.D- 012 (TY.HI) AGO 017 A A A A A PHI.(SYSTEM.CLOCK) 025 GND POWER.ON.CLR- 027 HALT- 028 Ml- 029 MRQ- 030 IORQ FORCE.NOP.DLYD J-4

191 WR- RD- SYS.RESET- D4 D5 RESTART- D6 D7 USER.MEM.ENABLE- DO Dl D3 D2 (4-0 5V. PRINTED. DISTRIBUTION) (+05V.PRINTED.DISTRIBUTION) (+05V.PRINTED.DISTRIBUTION) (GND.2.062) (GND.2.063) (GND.2.064) STOR.SEL- DISK.DATA.PORT- DISK. CONTROL.B.PORT- DISK. CONTROL. A. PORT- BKPT.SEL- UB.CONT- MRD- USER.NC USER.NO (SPARE.SEL-) (CTC.CARD.SEL-) MONTR.NC MONTR.NO TTY.DATA.OUT SERIAL.OUT RS232.DATA.OUT SERIAL.IN (M1S-) M1RQ (Ml ~ MREQ) RS232.RETURN TTY.DATA.IN RS232.DATA.IN J-5

192 V IE* 097 TTY.IN.RETURN 098-5V TTY.OUT.RETURN 100 (RFI) 101 DATA.STB 102 BREAK FORCE.NOP WAIT MONITOR 111 MONITOR (PHI.B.CLOCK.BUFFERED) 116 BREAK.STATUS 117 SENSE.SW.MEM (PORT FE D4) 118 SENSE.SW.CLK (PORT FE D1,D3) GND GND GND J-6

193 PINOUT FOR "FLOPPY.PIN" BOARD - # J03 PIN # SIGNAL NAME 001 (+05V.PRINTED.DISTRIBUTION) 002 (+05V.PRINTED.DISTRIBUTION) 003 (+05V.PRINTED.DISTRIBUTION) WR.DATA- 007 INDX 008 (WR.PROT.1-) 009 READ.DATA- 010 (TRK.01-) 011 TRK.OO- 012 (DOOR.OPEN-) 013 WR.PROT.O- 014 (INDX.1-) 015 INDX.O- 016 RDY- 017 (CURRENT-) 018 SEL.O- 019 (LOAD.HEAD.1-) 020 (STEP.OUT.1-) 021 (WRITE.1-) 022 (STEP.IN.1-) PHI.(8X.SYSTEM.CLOCK) WRITE.GATE DIRECTION.F 028 STEP IORQ J-7

194 044 WR- 045 RD D4 048 D D6 052 D7 053 SYS.RESET- 054 DO 055 Dl 056 D3 057 D (+05V.PRINTED.DISTRIBUTION) 060 (+05V.PRINTED.DISTRIBUTION) 061 (+05V.PRINTED.DISTRIBUTION) 062 GND GND GND (GND) 083 (GND) 084 SEL.l- 085 (GND) (LOAD.HEAD.0-) J-8

195 WAIT DISK.DATA.PORT- 117 DISK.CONTROL.A.PORT- 118 DISK.CONTROL.B.PORT (GND.3.120) 121 (GND.3.121) 122 (GND.3.122) J-9

196 PINOUT FOR "BREAKPOINT2" BOARD - # J04 PIN # SIGNAL NAME 001 (+05V.PRINTED.DISTRIBUTION) 002 (+05V.PRINTED.DISTRIBUTION) 003 (+05V.PRINTED.DISTRIBUTION) A A A All 013 A A BKPT.SEL- 016 AOO 017 A A A A A POWER.ON.CLR Ml- 029 MRQ- 030 IORQ A A A A15 J-10

197 044 WR- 045 RD D4 048 D D6 052 D DO 055 Dl 056 D3 057 D (+05V.PRINTED.DISTRIBUTION) 060 (+05V.PRINTED.DISTRIBUTION) 061 (+05V.PRINTED.DISTRIBUTION) 062 GND GND GND BREAK.STATUS M1RQ (Ml ~ MREQ FROM MONITOR) J-ll

198 BREAK- 101 BREAK.SYNC MONITOR DATA.STB (GND.4.120) 121 (GND.4.121) 122 (GND.4.122) J-12

199 PINOUT FOR "RTSM2" BOARD - # JOS PIN # SIGNAL NAME 001 (+05V.PRINTED.DISTRIBUTION) 002 (+05V.PRINTED.DISTRIBUTION) 003 (+05V.PRINTED.DISTRIBUTION) A A A All 013 A A AGO 017 A A A A A BUSAK HALT- 028 Ml- 029 MRQ- 030 IORQ FORCE.NOP.DLYD A A A A15 J-13

200 044 WR- 045 RD D4 048 D RESTART.D- 051 D6 052 D DO 055 Dl 056 D3 057 D (+05V.PRINTED.DISTRIBUTION) 060 (+05V.PRINTED.DISTRIBUTION) 061 (+05V.PRINTED.DISTRIBUTION) 062 GND GND GND STOR.SEL J-14

201 FORCE.NOP MONITOR DATA.STB (GND.5.120) 121 (GND.5.121) 122 (GND.5.122) J-15

202 PINOUT FOR "CPU2.PIN" J06 PIN # Ol SIGNAL NAME PS PS PS PS CD CD CD CD (+05V.PRINTED.DISTRIBUTION) (+05V.PRINTED.DISTRIBUTION) (+05V.PRINTED.DISTRIBUTION) RCVR.OUT- (SERIAL.OUT CPUO) RCV.CLK RCV.CLK (XMIT.CLK) SERIAL.IN A06 A07 A08 All A10 A09 SERIAL.OUT AOO A01 A02 A03 A04 A05 BUSAK- 8.PHI.(8X.SYSTEM.CLOCK) PHI.(SYSTEM.CLOCK? REFRESH- POWER. ON. CLR- HALT- Ml- MRQ- IORQ- 0- MDIS- A13 A14 A12 A15 J-16

203 ^' 044 WR RD- MONITOR 047 D D5 RESET.SW- 050 RESTART- 051 D6 052 D7 053 SYS.RESET DO Dl 056 D D2 EXT.PHI.(EXTERNAL.SYSTEM.CLOCK) (+05V.PRINTED.DISTRIBUTION) (+05V.PRINTED.DISTRIBUTION) 061 (+05V.PRINTED.DISTRIBUTION) 062 (GND.6.062) 063 (GND.6.063) 064 (GND.6.064) A13+ (SYSTEM.MEMORY) 068 A ^74 U RCVR.OUT- 078 INDX. (EN-CLKO) IE (GND) (GND) (GND) (GND) 087 (GND) V J-17

204 V FORCE.NOP 107 BUSRQ- 108 WAIT- 109 INT- 110 NMI S2.46MHZ (GND.6.120) 121 (GND.6.121) 122 (GND.6.122) J-18

205 PINOUT FOR <MEMORY.25.PIN> JOT PIN # Ol SIGNAL NAME (+0 5V. PRINTED. DISTRIBUTION) (+05V. PRINTED. DISTRIBUTION) (+05V. PRINTED. DISTRIBUTION) A06 A07 A08 All A10 A09 AOO A01 A02 A03 A04 A05 REFRESH- MRQ- PS. 3 PS. 2 PS.l PS.O CD. 3 CD. 2 CD.l CD.O MDIS A13+ A12+ J-19

206 044 WR MRD- 047 D4 048 D D6 052 D DO 055 Dl 056 D3 057 D (+05V.PRINTED.DISTRIBUTION) 060 (+05V.PRINTED.DISTRIBUTION) 061 (+05V.PRINTED.DISTRIBUTION) 062 (GND.7.062) 063 (GND.7.063) 064 (GND.7.064) V V V V V V V V V.2 J-20

207 V V , (GND.7.120) 121 (GND.7.121) 122 (GND.7.122) J-21

208 PINOUT FOR "STATIC.MEMORY.PIN" BOARD J07 (SO) JOS (SI) J09 (S2) * PIN # SIGNAL NAME 001 (+05V.PRINTED.DISTRIBUTION) 002 (+05V.PRINTED.DISTRIBUTION) 003 (+05V.PRINTED.DISTRIBUTION) A A A All 013 A A AGO 017 A A A A A MRQ PS PS PS.l- 034 PS.O CD.[#CARD]-.(ONE.OF.CD.0-.TO.CD.3-) 039 MDIS J-22

209 044 WR MRD- 047 D4 048 D D6 052 D DO 055 Dl 056 D3 057 D (+05V.PRINTED.DISTRIBUTION) 060 (+05V.PRINTED.DISTRIBUTION) 061 (+05V.PRINTED.DISTRIBUTION) 062 (GND.8.062) 063 (GND.8.063) 064 (GND.8.064) U J-23

210 (GND.8.120) (GND.8.121) (GND.8.122) J-24

211 PINOUT FOR "ZDSP" BOARD J09 PIN # SIGNAL NAME 001 (+05V.PRINTED.DISTRIBUTION) 002 (+05V.PRINTED.DISTRIBUTION) 003 (+05V.PRINTED.DISTRIBUTION) 004 TTXD 005 TRXD 006 TRTS 007 TCTS 008 TDSR 009 A A07 Ol AGO 017 A A A A A PHI. (SYSTEM.CLOCK) 025 TERM.BUSY 026 POWER.ON.CLR Ml IORQ CARRIER.DETECT J-25

212 044 WR- 045 RD D4 048 D5 049 SYNC 050 TDTR 051 D6 052 D DO 055 Dl 056 D3 057 D (+05V.PRINTED.DISTRIBUTION) 060 (+05V.PRINTED.DISTRIBUTION) 061 (+05V.4.PRINTED.DISTRIBUTION) 062 (GND.9.062) 063 (GND.9.063) 064 (GND.9.064) 065 ABO.D1.LP.RX (LP.DATA.l RXP.DATA.l) 066 AB1.D2.LP.RX 067 AB2.D3.LP.RX 068 AB3.D4.LP.RX 069 AB4.D5.LP.RX 070 AB5.D6.LP.RX 071 AB6.D7.LP.RX 072 AB7.D8.LP.RX 073 AAO.LP.RX (LP.DATA.STROBE- RXP.PUNCH.COMMAND) AA5.LP.RX (LP.SELECT RXP.PUNCH.SYSTEM.READY) 076 AA4.LP.RX (LP.BUSY RXP.PUNCH.READY) 077 AA3.LP.RX (LP.PAPER.EMPTY RXP.TAPE.LOW) 078 AA2.LP.RX (LP.FAULT- RXP.ERROR) AA1.LP.RX (LP.INPUT.PRIME- RXP.DIRECTION) 082 ABS.LP (LP ACKNOWLEDGE-) IE0.1 (BOARD IEI) 089 RING.IND V ORIGINATE.MODE 092 LOCAL.MODE 093 J-26

213 V INT IE0.2 (BOARD IEO) (GND.9.120) 121 (GND.9.121) 122 (GND.9.122) J-27

214 PINOUT FOR "ZDSP.2" BOARD J09 PIN # SIGNAL NAME 001 (+05V.PRINTED.DISTRIBUTION) 002 (+05V.PRINTED.DISTRIBUTION) 003 (+05V.PRINTED.DISTRIBUTION) 004 TTXD TRXD TRTS TCTS TDSR A A07 Ol AGO 017 A A A A A PHI. (SYSTEM.CLOCKS 025 TERM.BUSY POWER.ON.CLR Ml IORQ CARRIER.DETECT J-28

215 WR- RD- D4 D5 SYNC. 2 TDTR.2 D6 D7 DO Dl D3 D2 * (-1-0 5V. PRINTED. DISTRIBUTION) (+0 5V. PRINTED. DISTRIBUTION) (+05V. 4. PRINTED. DISTRIBUTION) (GND.9.062) (GND.9.063) (GND.9.064) (ABO.D1.LP.RX (LP.DATA.l RXP.DATA.l) (AB1.D2.LP.RX (AB2.D3.LP.RX (AB3.D4.LP.RX (AB4.D5.LP.RX (AB5.D6.LP.RX (AB6.D7.LP.RX (AB7.D8.LP.RX (AAO.LP.RX (LP. DATA. STROBE- RXP. PUNCH. COMMAND) (AA5.LP.RX (LP. SELECT RXP. PUNCH. SYSTEM.READY) (AA4.LP.RX (LP.BUSY RXP. PUNCH. READY) (AA3.LP.RX (LP. PAPER. EMPTY RXP. TAPE. LOW) (AA2.LP.RX (LP. FAULT- RXP. ERROR) (AA1.LP.RX (LP. INPUT. PRIME- RXP. DIRECTION) (ABS.LP (LP ACKNOWLEDGE-) IE0.2 (BOARD IEI) RING.IND.2 +12V.3 ORIGINATE. MODE. 2 LOCAL. MODE. 2 J-29

216 V INT IE0.3 (BOARD IEO) (GND.9.120) 121 (GND.9.121) 122 (GND.9.122) J-30

217 PINOUT FOR "GIB" BOARD JOS PIN # SIGNAL NAME 001 (+05V.PRINTED.DISTRIBUTION) 002 (+05V.PRINTED.DISTRIBUTION) 003 (+05V.PRINTED.DISTRIBUTION) A A07 Ol AOO 017 A A A A A PHI. (SYSTEM.CLOCK) Ml IORQ J-31

218 RD- D4 D5 D6 D7 SYS.RESET- DO Dl D3 D2 (+05V.PRINTED.DISTRIBUTION) (+05V.PRINTED.DISTRIBUTION) (+0 5V.PRINTED.DISTRIBUTION) (GND.9.062) (GND.9.063) (GND.9.064) ABO.D1.LP.RX AB1.D2.LP.RX (LP.DATA.l RXP.DATA.l) AB2.D3.LP.RX AB3.D4.LP.RX AB4.D5.LP.RX AB5.D6.LP.RX AB6.D7.LP.RX AB7.D8.LP.RX AAO.LP.RX (LP.DATA.STROBE- RXP. PUNCH.COMMAND) AA6.RX (RXP.INPUT.MODE.SELECT) AA5.LP.RX (LP.SELECT RXF.PUNCH.SYSTEM.READY) AA4.LP.RX (LP.BUSY RXP.PUNCH.READY) AA3.LP.RX (LP.PAPER.EMPTY RXP.TAPE.LOW) AA2.LP.RX (LP.FAULT- RXP.ERROR) (ABR) AA1.LP.RX (LP.INPUT.PRIME- ABS.LP (LP.ACKNOWLEDGE-) (AAR) (AAS) AA7.RX (RXP.OUTPUT.MODE.SELECT) IE0.1 (CARD IEI) BAO.DOUT.1.PP (PROLOG.DATA.OUT.1) RXP.DIRECTION) J-32

219 094 BA1.DOUT.2.PP BA2.DOUT.3.PP BA3.DOUT.4.PP BA4.DOUT.5.PP BA5.DOUT.6.PP BA6.DOUT.7.PP 101 BA7.DOUT.8.PP 102 BB5.PP.RX (PROLOG.MODE RXR.EXTERNAL.INHIBIT) 103 BB6.PP.RX (PROLOG.INTERLOCK RXR.DRIVE.RIGHT) BAO.DIN.l.PP.RX (PROLOG.DATA.IN.1 BA1.DIN.2.PP.RX RXB.DATA.IN BA2.DIN.3.PP.RX INT- 110 BA3.DIN.4.PP.RX BA4.DIN.5.PP.RX IE0.2 (CARD IEO) 113 BA5.DIN.6.PP.RX 114 BA6.DIN.7.PP.RX 115 BA7.DIN.8.PP.RX 116 BB2.PP (PROLOG.RESPONSE) 117 BBO.PP.RX (PROLOG.ADDRESS RXR.DATA.READY) 118 BB1.PP.RX (PROLOG.ERROR RXR.RDR.RDY) 119 BAR.PP.RX (PROLOG.TRANSFER RXR.OUTPUT.MODE) 120 (GND.9.120) (GND.9.121) (GND.9.122) J-33

220 PINOUT FOR "PIB" BOARD JOS PIN # SIGNAL NAME 001 (+05V.PRINTED.DISTRIBUTION) 002 (+05V.PRINTED.DISTRIBUTION) 003 (+05V.PRINTED.DISTRIBUTION) A A07 Ol AOO 017 A A A A A PHI. (SYSTEM.CLOCK) Ml IORQ J-34

221 ' RD- D4 D5 D6 D7 SYS.RESET- DO Dl D3 D2 (+0 5V.PRINTED.DISTRIBUTION) (+05V.PRINTED.DISTRIBUTION) (+05V.PRINTED.DISTRIBUTION) (GND.9.062) (GND.9.063) (GND.9.064) ABO.D1.LP.RX (LP.DATA.l RXP.DATA.l) AB1.D2.LP.RX AB2.D3.LP.RX AB3.D4.LP.RX AB4.D5.LP.RX AB5.D6.LP.RX AB6.D7.LP.RX AB7.D8.LP.RX AAO.LP.RX (LP.DATA.STROBE- RXP.PUNCH.COMMAND) AA6.RX (RXP.INPUT.MODE.SELECT) AA5.LP.RX (LP.SELECT RXP.PUNCH.SYSTEM.READY) AA4.LP.RX (LP.BUSY RXP.PUNCH.READY) AA3.LP.RX (LP.PAPER.EMPTY RXP.TAPE.LOW) AA2.LP.RX (LP.FAULT- RXP.ERROR) (ABR) AA1.LP.RX (LP.INPUT.PRIME- ABS.LP (LP.ACKNOWLEDGE-) (AAR) (AAS) AA7.RX (RXP.OUTPUT.MODE.SELECT) IE0.1 (CARD IEI) BAO.DOUT.1.PP (PROLOG.DATA.OUT.1) RXP.DIRECTION) J-35

222 BA1.DOUT.2.PP BA2.DOUT.3.PP BA3.DOUT.4.PP BA4.DOUT.5.PP BA5.DOUT.6.PP BA6.DOUT.7.PP BA7.DOUT.8.PP BB5.PP.RX (PROLOG.MODE RXR.EXTERNAL.INHIBIT) BB6.PP.RX (PROLOG.INTERLOCK RXR.DRIVE.RIGHT) BAO.DIN.l.PP.RX (PROLOG.DATA.IN.1 RXB.DATA.IN BA1.DIN.2.PP.RX BA2.DIN.3.PP.RX INT- BA3.DIN.4.PP.RX BA4.DIN.5.PP.RX IE0.2 (CARD IEO) BA5.DIN.6.PP.RX BA6.DIN.7.PP.RX BA7.DIN.8.PP.RX BB2.PP (PROLOG.RESPONSE) BBO.PP.RX (PROLOG.ADDRESS RXR.DATA.READY) BB1.PP.RX (PROLOG.ERROR RXR.RDR.RDY) BAR.PP.RX (PROLOG.TRANSFER RXR.OUTPUT.MODE) (GND.9.120) (GND.9.121) (GND.9.122) J-36

223 PINOUT FOR "REMEX.PIN" BOARD JOS PIN # SIGNAL NAME 001 (+05V.PRINTED.DISTRIBUTION) 002 (+05V.PRINTED.DISTRIBUTION) 003 (+05V.PRINTED.DISTRIBUTION) A Ol A AGO A A02 A A A05. ' PHI. (SYSTEM.CLOCK) Ml IORQ J-37

224 RD- D4 D5 D6 D7 DO Dl D3 D2 BB7.RX (RXR.DRIVE.LEFT) (+05V.PRINTED.DISTRIBUTION) (+05V.PRINTED.DISTRIBUTION) (+05V.PRINTED.DISTRIBUTION) (GND.9.062) (GND.9.063) (GND.9.064) ABO.D1.LP.RX (LP.DATA.l RXP.DATA.l) AB1.D2.LP.RX AB2.D3.LP.RX AB3.D4.LP.RX AB4.D5.LP.RX AB5.D6.LP.RX AB6.D7.LP.RX AB7.D8.LP.RX AAO.LP.RX (LP.DATA.STROBE- RXP.PUNCH.COMMAND) AA6.RX (RXP.INPUT.MODE.SELECT) AA5.LP.RX (LP.SELECT RXP.PUNCH.SYSTEM.READY) AA4.LP.RX (LP.BUSY RXP.PUNCH.READY) AA3.LP.RX (LP.PAPER.EMPTY RXP.TAPE.LOW) AA2.LP.RX (LP.FAULT- RXP.ERROR) (ABR) AA1.LP.RX (LP.INPUT.PRIME- ABS.LP (LP.ACKNOWLEDGE-) (AAR) (AAS) AA7.RX (RXP.OUTPUT.MODE.SELECT) IE0.1 (CARD IEI) BAO.DOUT.1.PP (PROLOG.DATA.OUT.1) RXP.DIRECTION) J-38

225 094 BA1.DOUT.2.PP 095 BA2.DOUT.3.PP 096 BA3.DOUT.4.PP BA4.DOUT.5.PP BA5.DOUT.6.PP 099 BA6.DOUT.7.PP BA7.DOUT.8.PP 102 BB5.PP.RX (PROLOG.MODE RXR.EXTERNAL.INHIBIT) 103 BB6.PP.RX (PROLOG.INTERLOCK RXR.DRIVE.RIGHT) 104 BAO.DIN.l.PP.RX (PROLOG.DATA.IN.1 RXB.DATA.IN BA1.DIN.2.PP.RX 106 BA2.DIN.3.PP.RX INT- 110 BA3.DIN.4.PP.RX 111 BA4.DIN.5.PP.RX IE0.2 (CARD IEO) BA5.DIN.6.PP.RX 114 BA6.DIN.7.PP.RX BA7.DIN.8.PP.RX BB2.PP (PROLOG.RESPONSE) 117 BBO.PP.RX (PROLOG.ADDRESS RXR.DATA.READY) BB1.PP.RX (PROLOG.ERROR RXR.RDR.RDY) BAR.PP.RX (PROLOG.TRANSFER RXR.OUTPUT.MODE) 120 (GND.9.120) 121 (GND.9.121) 122 (GND.9.122) J-39

226 PINOUT FOR "PROM PROGRAMMER" BOARD J09 PIN # SIGNAL NAME 001 (+05V.PRINTED.DISTRIBUTION) 002 (+05V.PRINTED.DISTRIBUTION) 003 (+05V.PRINTED.DISTRIBUTION) A A07 Ol AOO 017 A A A A A : 024 PHI.(SYSTEM.CLOCK) Ml IORQ J-40

227 RD D4 048 D D6 052 D DO 055 Dl 056 D3 057 D (+05V.PRINTED.DISTRIBUTION) 060 (+05V.PRINTED.DISTRIBUTION) 061 (+05V.PRINTED.DISTRIBUTION) 062 (GND.PRINTED.DISTRIBUTION) 063 (GND.PRINTED.DISTRIBUTION) 064 (GND.PRINTED.DISTRIBUTION) (IEI) J-41

228 (INT-) (IEO) (GND.PRINTED.DISTRIBUTION) 121 (GND.PRINTED.DISTRIBUTION) 122 (GND.PRINTED.DISTRIBUTION) J-42

229 PINOUT FOR I/O CONNECTOR "FLOPPY.CABLE.PIN" J13 PIN # SIGNAL NAME GND GND GND.3, GND GND GND GND GND GND GND GND GND GND GND GND INDX.O- 036 RDY- 038 SEL.O- 039 SEL.l DIRECTION.F 043 STEP- 044 WR.DATA- J-43

230 045 WRITE.GATE- 046 TRK.OO- 047 WR.PROT.O READ.DATA- 050 J-44

231 PINOUT FOR I/O CONNECTOR "TTY.CABLE" J14 PIN # SIGNAL NAME RS232.DATA.IN 003 RS232.DATA.OUT TTY.IN.RETURN 006 TTY.IN.RETURN 007 RS232.RETURN 008 TTY.IN.RETURN TTY.DATA.IN Ol TTY.DATA.OUT 017 TTY.OUT.RETURN TTY.IN.RETURN 025 J-45

232 PINOUT FOR I/O CONNECTOR "ZDSP.CABLE.PIN" J15 PIN # SIGNAL NAME TTXD 003 TRXD 004 TRTS 005 TCTS 006 TDSR 007 GND CARRIER.DETECT 009 ORIGINATE.MODE 010 LOCAL.MODE Ol TDTR RING.IND SYNC 025 TERM.BUSY J-46

233 PINOUT FOR "M.ICE.CABLE.2.PIN" J16 PIN # SIGNAL NAME 001 UMEM UBUSAK- 004 URFSH- 005 UNMI UWAIT- URST UWR- 010 URD- 011 UMRQ- 012 UIORQ UPHI UBREQ UIE UHALT- 017 UM1» 018 UINT- 019 GND GND GND GND GND GND GND J-47

234 PINOUT FOR "M.ICE.CABLE.1.PIN" J17 PIN # SIGNAL NAME Ol UAOO UA02 UA04 UA06 UA08 UA10 UA12 UA14 UDBO UDB2 UDB4 UDB6 UDB7 UA01 UA03 UA05 UA07 UA09 UA11 UA13 UA15 UDB1 UDB3 UDB5 GND J-48

235 PINOUT FOR I/O CONNECTOR "ZDSP.2.CABLE.PIN" J18 PIN # SIGNAL NAME TTXD TRXD TRTS TCTS TDSR GND CARRIER.DETECT ORIGINATE.MODE LOCAL.MODE.2 Ol TDTR RING.IND SYNC TERM.BUSY.2 J-49

236 PINOUT FOR I/O CONNECTOR "PROLOG.CABLE.PIN" J19 PIN # SIGNAL NAME BAR.PP.RX (PROLOG.TRANSFER RXR.OUTPUT.MODE) 003 BB5.PP.RX (PROLOG.MODE RXR.EXTERNAL.INHIBIT) BB6.PP.RX (PROLOG.INTERLOCK RXR.DRIVE.RIGHT) 006 BA6.DOUT.7.PP 007 BA2.DOUT.3.PP BA7.DOUT.8.PP BA3.DOUT.4.PP 010 BA4.DOUT.5.PP 011 BAO.DOUT.l.PP (PROLOG.DATA.OUT.1) 012 BA1.DOUT.2.PP 013 BA5.DOUT.6.PP 014 BB1.PP.RX (PROLOG.ERROR RXR.ERROR) 015 BBO.PP.RX (PROLOG.ADDRESS RXR.DATA.READY) 016 BB2.PP (PROLOG.RESPONSE) 017 BA2.DIN.3.PP.RX 018 BA3.DIN.4.PP.RX BAO.DIN.l.PP.RX (PROLOG.DATA.IN.1 BA1.DIN.2.PP.RX RXB.DATA.I 021 BA6.DIN.7.PP.RX 022 BA7.DIN.8.PP.RX BA4.DIN.5.PP.RX BA5.DIN.6.PP.RX 025 GND J-50

237 PINOUT FOR I/O CONNECTOR "LP.CABLE" J20 PIN # Ol SIGNAL NAME ABO.Dl.LP.RX AB1.D2.LP.RX (LP.DATA.1 RXP.DATA.1) AB2.D3.LP.RX AB3.D4.LP.RX AB4.D5.LP.RX AB5.D6.LP.RX AB6.D7.LP.RX AB7.D8.LP.RX AAO.LP.RX (LP.DATA.STROBE- RXP.PUNCH.COMMAND) AA1.LP.RX (LP.INPUT.PRIME- RXP.DIRECTION) ABS.LP (LP.ACKNOWLEDGE-) AA2.LP.RX (LP.FAULT- RXP.ERROR) AA3.LP.RX (LP.PAPER.EMPTY RXP.TAPE.LOW) GND GND GND AA4.LP.RX (LP.BUSY RXP.PUNCH.READY) AA5.LP.RX (LP.SELECT RXP.PUNCH.SYSTEM.READY) J-51

238 PINOUT FOR I/O CONNECTOR "FRONT.PANEL.CABLE" J21 PIN # SIGNAL NAME GND GND BREAK.SYNC SENSE.SW.l-f GND V V V V USER.NO 012 USER.NC 013 GND SENSE.SW SENSE.SW.l- 016 SENSE.SW BNMI.SW- RESET.SW- > HALT.LAMP- USER.LAMP MONITOR.LAMP- WAIT.LAMP GND MONTR.NO 026 MONTR.NC J-52

239 PINOUT FOR I/O CONNECTOR "POWER CABLE" J25 PIN # SIGNAL NAME V V V (-12V.1) 005 (-12V.2) 006 (-12V.3) V V V (+05V.PRINTED.DISTRIBUTION) 011 (GND.PRINTED.DISTRIBUTION) J-53

240 PINOUT FOR I/O CONNECTOR "REMEX.CABLE" J26 PIN # Ol SIGNAL NAME ABO.Dl.LP.RX AB1.D2.LP.RX AB2.D3.LP.RX AB3.D4.LP.RX AB4.D5.LP.RX AB5.D6.LP.RX AB6.D7.LP.RX AB7.D8.LP.RX (LP.DATA.l RXP.DATA.l) AA1.LP.RX (LP.INPUT.PRIME- RXP.DIRECTION) AAO.LP.RX (LP.DATA.STROBE- RXP.PUNCH.COMMAND) AA4.LP.RX (LP.BUSY RXP.PUNCH.READY) AA5.LP.RX (LP.SELECT RXP.PUNCH.SYSTEM.READY) BB1.PP.RX (PROLOG.ERROR RXR.RDR.RDY) BB5.PP.RX (PROLOG.MODE RXR.EXTERNAL.INHIBIT) BB6.PP.RX (PROLOG.INTERLOCK RXR.DRIVE.RIGHT) BB7.RX ( RXR.DRIVE.LEFT) GND GND AA6.RX (RXP.INPUT.MODE.SELECT) AA7.RX (RXP.OUTPUT.MODE.SELECT) GND GND GND AA2.LP.RX (LP.FAULT- RXP.ERROR) AA3.LP.RX (LP.PAPER.EMPTY RXP.TAPE.LOW) GND BAO.DIN.1.PP.RX (PROLOG.DATA.IN.1 BA1.DIN.2.PP.RX BA2.DIN.3.PP.RX BA3.DIN.4.PP.RX BA4.DIN.5.PP.RX BA5.DIN.6.PP.RX RXB. DATA. IN. 1 J-54

241 044 BA6.DIN.7.PP.RX 045 BAT.DIN.8.PP.RX 046 BBO.PP.RX (PROLOG.ADDRESS RXR.DATA.READY) 047 BAR.PP.RX (PROLOG TRANSFER RXR.OUTPUT.MODE) 048 GND GND GND

242

243 r \- V

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