RTD Embedded Technologies, Inc.

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1 DM35424HR/DM35224HR PCI Express Analg I/O datamdule User s Manual BDM Rev. D RTD Embedded Technlgies, Inc. AS9100 and ISO 9001 Certified

2 RTD Embedded Technlgies, Inc. 103 Innvatin Bulevard State Cllege, PA USA Telephne: Fax:

3 Revisin Histry Rev A Rev B Rev C Rev D Initial Release Added Infrmatin abut DM35224 Updated DIO IDAN Pinut Update FFT specificatin CLK_SRC_GBL changed t CLK_BUS Added matching cnnectr infrmatin and better cnnectr descriptins Added imprved bard dimensin image. Advanced Analg I/O, Advanced Digital I/O, aaio, adio, a2dio, Autnmus SmartCal, Catch the Express, cpumdule, dspframewrk, dspmdule, expressmate, ExpressPlatfrm, HiDANplus, MIL Value fr COTS prices, multiprt, PlatfrmBus, and PC/104EZ are trademarks, and Accessing the Analg Wrld, datamdule, IDAN, HiDAN, RTD, and the RTD lg are registered trademarks f RTD Embedded Technlgies, Inc (frmerly Real Time Devices, Inc.). PS/2 is a trademark f Internatinal Business Machines Inc. PCI, PCI Express, and PCIe are trademarks f PCI-SIG. PC/104, PC/104-Plus, PCI-104, PCIe/104, PCI/104-Express and 104 are trademarks f the PC/104 Embedded Cnsrtium. All ther trademarks appearing in this dcument are the prperty f their respective wners. Failure t fllw the instructins fund in this manual may result in damage t the prduct described in this manual, r ther cmpnents f the system. The prcedure set frth in this manual shall nly be perfrmed by persns qualified t service electrnic equipment. Cntents and specificatins within this manual are given withut warranty, and are subject t change withut ntice. RTD Embedded Technlgies, Inc. shall nt be liable fr errrs r missins in this manual, r fr any lss, damage, r injury in cnnectin with the use f this manual. Cpyright 2017 by RTD Embedded Technlgies, Inc. All rights reserved. RTD Embedded Technlgies, Inc. iii DM35424/DM35224 User s Manual

4 Table f Cntents 1 Intrductin Prduct Overview Bard Features Ordering Infrmatin Cntact Infrmatin Sales Supprt Technical Supprt 9 2 Specificatins Operating Cnditins Electrical Characteristics Analg Input FFT plts 12 3 Bard Cnnectin Bard Handling Precautins Physical Characteristics Cnnectrs and Jumpers Bus Cnnectrs 14 CN1(Tp) & CN2(Bttm): PCIe Cnnectr DM35424 External I/O Cnnectrs 14 Digital I/O Cnnectrs: CN6 14 Analg I/O Cnnectrs: CN14 and CN DM35224 External I/O Cnnectrs 15 Digital I/O Cnnectrs: CN6 15 Analg I/O Cnnectrs: CN Jumpers Steps fr Installing IDAN Cnnectins Mdule Handling Precautins DM35424 Physical Characteristics DM35224 Physical Characteristics Cnnectrs DM35424 External I/O Cnnectrs 20 AIO 1-8 Cnnectr - 68-pin Subminiature D Female Cnnectr 20 AIO 5-16 Cnnectr - 68-pin Subminiature D Female Cnnectr 22 AIO 1-8 Cnnectr - 62-pin High Density D Female Cnnectr 23 AIO 5-16 Cnnectr - 62-pin High Density D Female Cnnectr 24 DIO Cnnectrs - 15-pin D Female Cnnectr DM35224 External I/O Cnnectrs 26 AIO 1-8 Cnnectr - 68-pin Subminiature D Female Cnnectr 26 AIO 1-8 Cnnectr - 62-pin High Density D Female Cnnectr 27 DIO Cnnectrs - 15-pin D Female Cnnectr Steps fr Installing Functinal Descriptin DMA Engine Analg Frnt-End DAC Lpback Mde 31 Single-Ended Psitive Input Mde 32 Single-Ended Negative Input Mde 32 Differential Input Mde 32 RTD Embedded Technlgies, Inc. iv DM35424/DM35224 User s Manual

5 5.4 Analg t Digital Cnverter Initializatin Analg t Digital Cnverter Delay Data Frmatting Digital t Analg Cnverter Initializing the DAC Cnverter Digital I/O Vltage Reference Register Address Space 34 Register Types 34 Clck Surce BAR0 General Bard Cntrl GBC_BRD_RST (Read/Write) GBC_EOI (Read/Clear) GBC_REV (Read-Only) GBC_FMT (Read-Only) GBC_PDP (Read-Only) GBC_BUILD (Read-Only) GBC_SYS_CLK_FREQ (Read Only) GBC_IRQ_STATUS (Read/Clear) GBC_DIRQ_STATUS (Read/Clear) FBn_ID (Read-Only) FBn_Offset (Read-Only) FBn_Offset_DMA (Read-Only) BAR2 Functinal Blck Standard DMA FB_DMAm_Actin (Read/Write) FB_DMAm_LAST_ACTION (READ/WRITE) FB_DMAm_Setup (Read/Write) FB_DMAm_Stat_Used (Read/Write) FB_DMAm_Stat_Invalid (Read/Write) FB_DMAm_Stat_Overflw (Read/Write) FB_DMAm_Stat_Underflw (Read/Write) FB_DMAm_Stat_Cmplete (Read/Write) FB_DMAm_Current_Buffer (Read-Only) FB_DMAm_COUNT (Read-Only) FB_DMAm_RD_FIFO_CNT (Read-Only) FB_DMAm_WR_FIFO_CNT (Read-Only) FB_DMAm_ADDRESSn (Read/Write) FB_DMAm_SIZEn (Read/Write) FB_DMAm_CTRLn (Read/Write) FB_DMAm_STATn (Read/Clear) BAR2 ADC Functinal Blck FB_ID (Read-Only) FB_DMA_CHANNELS (Read -Only) FB_DMA_BUFFERS (Read-Only) Mde_Status (Read/Write, Read-Only) CLK_SRC (Read/Write) START_TRIG (Read/Write) STOP_TRIG (Read/Write) CLK_DIV (Read/Write) CLK_DIV_CNTR (Read Only) PRE_TRIGGER_CAPTURE (Read/Write) POST_STOP_CAPTURE (Read/Write) SAMPLE_CNT (Read Only) INT_ENA (Maskable Read/Write) INT_STAT (Read/Clear) CLK_BUSn AD_CONFIG (Maskable Read/Write) CHn_FRONT_END_CONFIG (Maskable Read/Write) CHn_FIFO_DATA_CNT (Read) CHn_FILTER (Read/Write) CHn_INT_STAT (Read/Clear) 45 RTD Embedded Technlgies, Inc. v DM35424/DM35224 User s Manual

6 CHn_INT_ENA (Read/Write) CHn_THRESH_LOW (Read/Write) CHn_THRESH_HIGH (Read/Write) CH_LAST_SAMPLE (Read-Only) BAR2 DAC Functinal Blck FB_ID (Read-Only) FB_DMA_CHANNELS (Read -Only) FB_DMA_BUFFERS (Read-Only) Mde_Status (Read/Write, Read-Only) CLK_SRC (Read/Write) START_TRIG (Read/Write) STOP_TRIG (Read/Write) CLK_DIV (Read/Write) CLK_DIV_CNTR (Read Only) POST_STOP_CONVERSIONS (Read/Write) CONVERSION_CNT (Read Only) INT_ENA (Maskable Read/Write) INT_STAT (Read/Clear) CLK_BUSn DA_CONFIG (Maskable Read/Write) CH_FRONT_END_CONFIG (Maskable Read/Write) CHn_FIFO_DATA_CNT (Read) CH_INT_STAT (Read/Clear) CH_INT_ENA (Read/Write) CH_LAST_CONVERSIONS (Read/Write) BAR2 Digital I/O Functinal Blck FB_ID (Read-Only) FB_DMA_CHANNELS (Read -Only) FB_DMA_BUFFERS (Read-Only) DIO_INPUT_VAL (Read Only) DIO_OUTPUT_VAL (Read/Write) DIO_DIRECTION (Read/Write) BAR2 Reference Adjustment Digital Ptentimeter Functinal Blck FB_ID (Read-Only) FB_DMA_CHANNELS (Read -Only) FB_DMA_BUFFERS (Read-Only) GO_BUSY (Read/Clear) OUTPUT_LATCH (Read/Write) BAR2 Temperature Sensr Functinal Blck FB_ID (Read-Only) FB_DMA_CHANNELS (Read -Only) FB_DMA_BUFFERS (Read-Only) TEMPERATURE_VAL (Read Only) 52 7 Trubleshting 53 8 Additinal Infrmatin PC/104 Specificatins PCI and PCI Express Specificatin Limited Warranty 55 RTD Embedded Technlgies, Inc. vi DM35424/DM35224 User s Manual

7 Table f Figures Figure 1: High Speed Mde FFT Figure 2: High Reslutin Mde FFT Figure 3: Bard Dimensins Figure 4: Bard Cnnectins Figure 5: Example 104 Stack Figure 6: DM35424 IDAN Dimensins Figure 7: IDAN Dimensins Figure 8: Example IDAN System Figure 9: DM35424 Blck Diagram Figure 10: DM35424 Frnt-End Figure 11: Filter Respnse with each ORDER Value Table f Tables Table 1: Ordering Optins... 8 Table 2: Operating Cnditins Table 3: Electrical Characteristics Table 4: CN6 Digital I/O Pin Assignments Table 5: CN14 Analg I/O Pin Assignments Table 6: CN24 Analg I/O Pin Assignments Table 7: CN6 Digital I/O Pin Assignments Table 8: CN14 Analg I/O Pin Assignments Table 9: IDAN- DM Pin Subminiature "D" Cnnectr Table 10: IDAN- DM Pin Subminiature "D" Cnnectr Table 11: IDAN- DM Pin High Density "D" Cnnectr Table 12: IDAN- DM Pin High Density "D" Cnnectr Table 13: IDAN- DM Pin "D" Cnnectr Table 14: IDAN- DM Pin Subminiature "D" Cnnectr Table 15: IDAN- DM Pin High Density "D" Cnnectr Table 16: IDAN- DM Pin "D" Cnnectr Table 17: Crrespnding DAC t ADC channel Table 18: BAR0 Registers Table 19: DMA Registers Table 20: Multi-Channel ADC Functinal Blck Table 21: Differential Mde Range/Gain Table Table 22: Single-Ended Mde Range/Gain Table Table 23: Multi-Channel DAC Functinal Blck Table 24: Digital I/O Functinal Blck Table 25: Digital Ptentimeter Functinal Blck Table 26: Temperature Sensr Functinal Blck RTD Embedded Technlgies, Inc. vii DM35424/DM35224 User s Manual

8 1 Intrductin 1.1 Prduct Overview The DM35424 is a sftware cnfigurable simultaneus sampling data acquisitin mdule. This mdule prvides 16 differential analg input channels, with prgrammable gains. It als prvides 16 individually cntrlled analg utputs and digital I/O. The DM35224 is a sftware cnfigurable simultaneus sampling data acquisitin mdule. This mdule prvides 8 differential analg input channels, with prgrammable gains. It als prvides 8 individually cntrlled analg utputs and digital I/O. This bard is targeted t sensrs that require high precisin with a lw signal level, such as accelermeters, pressure transducers, and Resistance Temperature Detectrs (RTD). The DAC utput can prvide sufficient current and vltage fr the excitatin vltage f mst sensrs. 1.2 Bard Features PCIe x 1 Interface Universal Bard can be used with a PCIe/104 Type 1 r Type 2 hst Dedicated DMA channel per I/O fr maximum efficiency Analg Inputs 16 Input Channels (DM35424) / 8 Input Channels (DM35224) Prgrammable Differential r Single Ended ±2.5V Differential Analg Input range 0-5V Single Ended Input range Prgrammable gains f 1, 2, 4, 8, 16, 32, 64, & bit delta sigma ADC with simultaneus sampling 9.48µs max cnversin time (105 KHz thrughput) Sampling mdes and triggers are cnfigurable independently Threshld detectin can generate an interrupt, r be used as a start r stp trigger Cnfigurable IIR filter n each channel Analg utputs 16 Single ended channels (DM35424) /8 Single ended channels (DM35224) 16-bit reslutin 10 µs full-scale settling time (±5V range) ±5V utput range 10mA utput current Digital I/O 14 bits f Digital I/O Bit prgrammable directin 5V tlerant 1.3 Ordering Infrmatin The DM35424 is available in the fllwing ptins: Table 1: Ordering Optins Part Number DM35424HR DM35224HR IDAN-DM35224HR-62S IDAN-DM35424HR-62S IDAN-DM35224HR-68S IDAN-DM35424HR-68S Descriptin PCIe/104 Analg I/O datamdule PCIe/104 Analg I/O datamdule PCIe/104 Analg I/O datamdule in IDAN enclsure with 62-pin D-Sub Cnnectr PCIe/104 Analg I/O datamdule in IDAN enclsure with 62-pin D-Sub Cnnectr PCIe/104 Analg I/O datamdule in IDAN enclsure with 68-pin High-Density Cnnectr PCIe/104 Analg I/O datamdule in IDAN enclsure with 68-pin High-Density Cnnectr Nte: Thrughut this dcument, DM35424 refers t bth DM35424 and DM35224 unless therwise nted RTD Embedded Technlgies, Inc. 8 DM35424/DM35224 User s Manual

9 The Intelligent Data Acquisitin Nde (IDAN ) building blck can be used in just abut any cmbinatin with ther IDAN building blcks t create a simple but rugged 104 stack. This mdule can als be incrprated in a custm-built RTD HiDAN r HiDANplus High Reliability Intelligent Data Acquisitin Nde. Cntact RTD sales fr mre infrmatin n ur high reliability systems. 1.4 Cntact Infrmatin SALES SUPPORT Fr sales inquiries, yu can cntact RTD Embedded Technlgies sales via the fllwing methds: Phne: Mnday thrugh Friday, 8:00am t 5:00pm (EST). sales@rtd.cm TECHNICAL SUPPORT If yu are having prblems with yu system, please try the steps in the Trubleshting sectin f this manual. Fr help with this prduct, r any ther prduct made by RTD, yu can cntact RTD Embedded Technlgies technical supprt via the fllwing methds: Phne: Mnday thrugh Friday, 8:00am t 5:00pm (EST). techsupprt@rtd.cm RTD Embedded Technlgies, Inc. 9 DM35424/DM35224 User s Manual

10 2 Specificatins 2.1 Operating Cnditins Table 2: Operating Cnditins Symbl Parameter Test Cnditin Min Max Unit Vcc5 5V Supply Vltage V Vcc3 3.3V Supply Vltage n/a n/a V Vcc12 12V Supply Vltage n/a n/a V Ta Operating Temperature C Ts Strage Temperature C RH Relative Humidity Nn-Cndensing 0 90% % MTBF Mean Time Befre Failure Telcrdia Issue 2 30 C, Grund benign, cntrlled TBD Hurs 2.2 Electrical Characteristics All specificatin Table 3: Electrical Characteristics Symbl Parameter Test Cnditin Min Typ Max Unit P Pwer Cnsumptin (DM35424) Vcc5 = 5.0V 7.52 W Icc 5V Input Supply Current (DM35424) Active 1504 ma P Pwer Cnsumptin (DM35224) Vcc5 = 5.0V TBD W Icc 5V Input Supply Current (DM35224) Active TBD ma PCIe/104 Bus Differential Output Vltage V DC Differential TX Impedance Ω Differential Input Vltage V DC Differential RX Impedance Ω Electrical Idle Detect Threshld mv Analg t Digital Cnverter Linear Input Vltage IN+ r IN V FSR Full-scale Differential Input Vltage VIN=(IN+ - IN-) LSB +2.5 V Linear Differential Input Vltage VIN=(IN+ - IN-) G = PGA Gain G G V Reslutin 24 Bits High-Speed Mde Data Rate High-Reslutin Mde Lw-Pwer Mde SPS Lw-Speed Mde Passive Filter -3dB Frequency 64 KHz Internal Filter -3dB Frequency.49 fdata Hz Internal Filter Stp Band High-Reslutin Mde 95 Attenuatin All ther mdes 100 db Internal Filter Stp Band High-Reslutin Mde fdata All ther mdes fdata fdata fdata Hz Frnt-End Gain Flatness Frequency:0 35Khz 1 db Settling Time Cmplete Settling 78 Samples Delay High-Reslutin Mde 39 All ther mdes 38 Samples ENOB (1) High-Reslutin Mde Bits All ther mdes SNR (1) High-Reslutin Mde db All ther mdes THD (1) High-Reslutin Mde db RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

11 Table 3: Electrical Characteristics Symbl Parameter Test Cnditin Min Typ Max Unit All ther mdes Nise Free Bits (2) High-Reslutin Mde 15.5 All ther mdes 14.6 Bits G Gains Digital t Analg Cnverter Full-scale Analg Output Vltage V Reslutin 16 Bits INL Relative Accuracy LSB Full-Scale Accuracy LSB Nn-Linearity LSB Settling Time 10 µs Output Current 10 ma -3dB Frequency Hz Slew Rate 5 V/µs Digital I/O VIL Input High Vltage 2 5 V VIH Input Lw Vltage V VOL Output Lw Vltage IO =-12mA V VOH Output High Vltage IO = -12mA V Reference Adjustment Digital Ptentimeter Settling Time Change frm 0x0 0xFF 0.5 µs Write t Nnvlatile 12 ms Read Nnvlatile 1 µs Write t Output 1 µs 1 Calculated with Input = KHz, Max Sample Rate 2 Calculated with Inputs grunded, Max Sample Rate RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

12 2.2.1 ANALOG INPUT FFT PLOTS In Figure 1, the ADC was set t high speed mde and a cherent 1KHz sine wave signal was attached t input ADC0 Channel 0. The FFT abslute value was calculated using a Blackman-Hanning three term windw. Three samples were taken, and the FFT data averaged. In Figure 2, the ADC was set t high reslutin mde and a cherent 1KHz sine wave signal was attached t input ADC0 Channel 0. The FFT abslute value was calculated using a Blackman-Hanning three term windw. Three samples were taken, and the FFT data averaged db FS Frequency (MHz) Figure 1: High Speed Mde FFT db FS Frequency (khz) Figure 2: High Reslutin Mde FFT RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

13 3 Bard Cnnectin 3.1 Bard Handling Precautins T prevent damage due t Electrstatic Discharge (ESD), keep yur bard in its antistatic bag until yu are ready t install it int yur system. When remving it frm the bag, hld the bard at the edges, and d nt tuch the cmpnents r cnnectrs. Handle the bard in an antistatic envirnment, and use a grunded wrkbench fr testing and handling f yur hardware. 3.2 Physical Characteristics Weight: Apprximately 80 g (0.18 lbs.) Dimensins: mm L x mm W (3.550 in L x in W) Figure 3: Bard Dimensins RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

14 3.3 Cnnectrs and Jumpers CN6 Digital I/O CN24 Analg I/O (DM35424 nly) CN14 Analg I/O CN1 & CN2: PCIe Cnnectr Figure 4: Bard Cnnectins BUS CONNECTORS CN1(Tp) & CN2(Bttm): PCIe Cnnectr The PCIe cnnectr is the cnnectin t the system CPU. The psitin and pin assignments are cmpliant with the PCI/104-Express Specificatin. (See PC/104 Specificatins n page 54) The DM35424 is a Universal bard, and can cnnect t either a Type 1 r Type 2 PCIe/104 cnnectr DM35424 EXTERNAL I/O CONNECTORS Digital I/O Cnnectrs: CN6 CN6 cntains ne 14 bit prt f digital I/O. The pin assignment is listed belw. The cnnectr is a 2 X 8, 0.1 spacing DIL cnnectr. The typical mating cnnectr is an FCI LF (r similar) cut-t-fit. Pin 1 is indicated by a square slder pad n the bard. Table 4: CN6 Digital I/O Pin Assignments PORT0_1 2 1 PORT0_0 PORT0_3 4 3 PORT0_2 PORT0_5 6 5 PORT0_4 PORT0_7 8 7 PORT0_6 PORT0_ PORT0_8 PORT0_ PORT0_10 PORT0_ PORT0_12 +5V GND RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

15 Analg I/O Cnnectrs: CN14 and CN24 CN14 and CN24 cntain the signals fr the 16 analg I/O channels. The pin assignment is listed belw. The cnnectr is a 2 x 25, 0.1 spacing right-angle cnnectr. A typical mating cnnectr is an FCI LF. Pin 1 is indicated by a square slder pad n the bard. Table 5: CN14 Analg I/O Pin Assignments AGND 2 1 AGND AGND 4 3 DAC0 Channel 0 ADC0 Channel ADC0 Channel 0+ AGND 8 7 AGND AGND 10 9 DAC0 Channel 1 ADC0 Channel ADC0 Channel 1+ AGND AGND AGND DAC0 Channel 2 ADC0 Channel ADC0 Channel 2+ AGND AGND AGND DAC0 Channel 3 ADC0 Channel ADC0 Channel 3+ AGND AGND AGND DAC1 Channel 0 ADC0 Channel ADC0 Channel 4+ AGND AGND AGND DAC1 Channel 1 ADC0 Channel ADC0 Channel 5+ AGND AGND AGND DAC1 Channel 2 ADC0 Channel ADC0 Channel 6+ AGND AGND AGND DAC1 Channel 3 ADC0 Channel ADC0 Channel 7+ AGND AGND Table 6: CN24 Analg I/O Pin Assignments AGND 2 1 AGND AGND 4 3 DAC2 Channel 0 ADC1 Channel ADC1 Channel 0+ AGND 8 7 AGND AGND 10 9 DAC2 Channel 1 ADC1 Channel ADC1 Channel 1+ AGND AGND AGND DAC2 Channel 2 ADC1 Channel ADC1 Channel 2+ AGND AGND AGND DAC2 Channel 3 ADC1 Channel ADC1 Channel 3+ AGND AGND AGND DAC3 Channel 0 ADC1 Channel ADC1 Channel 4+ AGND AGND AGND DAC3 Channel 1 ADC1 Channel ADC1 Channel 5+ AGND AGND AGND DAC3 Channel 2 ADC1 Channel ADC1 Channel 6+ AGND AGND AGND DAC3 Channel 3 ADC1 Channel ADC1 Channel 7+ AGND AGND Nte: CN3 is fr Factry Use nly DM35224 EXTERNAL I/O CONNECTORS Digital I/O Cnnectrs: CN6 CN6 cntains ne 14 bit prt f digital I/O. The pin assignment is listed belw. The cnnectr is a 2 X 8, 0.1 spacing straight cnnectr. The typical mating cnnectr is an FCI LF (r similar) cut-t-fit. Pin 1 is indicated by a square slder pad n the bard. Table 7: CN6 Digital I/O Pin Assignments PORT0_1 2 1 PORT0_0 PORT0_3 4 3 PORT0_2 PORT0_5 6 5 PORT0_4 PORT0_7 8 7 PORT0_6 PORT0_ PORT0_8 PORT0_ PORT0_10 PORT0_ PORT0_12 +5V GND RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

16 Analg I/O Cnnectrs: CN14 CN14 cntain the signals fr the 16 analg I/O channels. The pin assignment is listed belw. The cnnectr is a 2 x 25, 0.1 spacing right-angle cnnectr. A typical mating cnnectr is an FCI LF. Pin 1 is indicated by a square slder pad n the bard. Table 8: CN14 Analg I/O Pin Assignments AGND 2 1 AGND AGND 4 3 DAC0 Channel 0 ADC0 Channel ADC0 Channel 0+ AGND 8 7 AGND AGND 10 9 DAC0 Channel 1 ADC0 Channel ADC0 Channel 1+ AGND AGND AGND DAC0 Channel 2 ADC0 Channel ADC0 Channel 2+ AGND AGND AGND DAC0 Channel 3 ADC0 Channel ADC0 Channel 3+ AGND AGND AGND DAC1 Channel 0 ADC0 Channel ADC0 Channel 4+ AGND AGND AGND DAC1 Channel 1 ADC0 Channel ADC0 Channel 5+ AGND AGND AGND DAC1 Channel 2 ADC0 Channel ADC0 Channel 6+ AGND AGND AGND DAC1 Channel 3 ADC0 Channel ADC0 Channel 7+ AGND AGND Nte: CN3 is fr Factry Use nly JUMPERS There are n jumpers n the DM RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

17 3.4 Steps fr Installing 1. Always wrk at an ESD prtected wrkstatin, and wear a grunded wrist-strap. 2. Turn ff pwer t the PC/104 system r stack. 3. Select and install stand-ffs t prperly psitin the mdule n the stack. 4. Remve the mdule frm its anti-static bag. 5. Check that pins f the bus cnnectr are prperly psitined. 6. Check the stacking rder; make sure all f the busses used by the peripheral cards are cnnected t the cpumdule. 7. Hld the mdule by its edges and rient it s the bus cnnectr pins line up with the matching cnnectr n the stack. 8. Gently and evenly press the mdule nt the PC/104 stack. 9. If any bards are t be stacked abve this mdule, install them. 10. Attach any necessary cables t the PC/104 stack. 11. Re-cnnect the pwer crd and apply pwer t the stack. 12. Bt the system and verify that all f the hardware is wrking prperly. Figure 5: Example 104 Stack RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

18 4 IDAN Cnnectins 4.1 Mdule Handling Precautins T prevent damage due t Electrstatic Discharge (ESD), keep yur mdule in its antistatic bag until yu are ready t install it int yur system. When remving it frm the bag, hld the mdule by the aluminum enclsure, and d nt tuch the cmpnents r cnnectrs. Handle the mdule in an antistatic envirnment, and use a grunded wrkbench fr testing and handling f yur hardware. 4.2 DM35424 Physical Characteristics Weight: Apprximately 0.35 Kg (0.78 lbs.) Dimensins: 152 mm L x 130 mm W x 34 mm H (5. in L x 5.12 in W x 1.34 in H) Figure 6: DM35424 IDAN Dimensins RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

19 4.3 DM35224 Physical Characteristics Weight: Apprximately 0.22 Kg (0.48 lbs.) Dimensins: 152 mm L x 130 mm W x 17 mm H (5. in L x 5.12 in W x 0.67 in H) Figure 7: IDAN Dimensins RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

20 4.4 Cnnectrs DM35424 EXTERNAL I/O CONNECTORS AIO 1-8 Cnnectr - 68-pin Subminiature D Female Cnnectr Cnnectr Part #: Amp Sample Mating Cnnectr: Amp (IDC Crimp) Table 9: IDAN- DM Pin Subminiature "D" Cnnectr IDAN Pin# Signal DM35424 Pin # 1 AGND CN AGND CN DAC0 Channel 0 CN AGND CN ADC0 Channel 0+ CN ADC0 Channel 0- CN AGND CN AGND CN DAC0 Channel 2 CN AGND CN ADC0 Channel 1+ CN ADC0 Channel 1- CN AGND CN AGND CN DAC0 Channel 2 CN AGND CN ADC0 Channel 2+ CN ADC0 Channel 2- CN AGND CN AGND CN DAC0 Channel 3 CN AGND CN ADC0 Channel 3+ CN ADC0 Channel 3- CN AGND CN AGND CN DAC1 Channel 0 CN AGND CN ADC0 Channel 4+ CN ADC0 Channel 4- CN AGND CN AGND CN DAC1 Channel 1 CN AGND CN14 34 Table 9: IDAN- DM Pin Subminiature "D" Cnnectr IDAN Pin# Signal DM35424 Pin # 35 ADC0 Channel 5+ CN ADC0 Channel 5- CN AGND CN AGND CN DAC1 Channel 2 CN AGND CN ADC0 Channel 6+ CN ADC0 Channel 6- CN AGND CN AGND CN DAC1 Channel 3 CN AGND CN ADC0 Channel 7+ CN ADC0 Channel 7- CN AGND CN AGND CN N/C 52 N/C 53 N/C 54 N/C 55 N/C 56 N/C 57 N/C 58 N/C 59 N/C 60 N/C 61 N/C 62 N/C 63 N/C 64 N/C 65 N/C 66 N/C 67 N/C 68 N/C RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

21 RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

22 AIO 5-16 Cnnectr - 68-pin Subminiature D Female Cnnectr Cnnectr Part #: Amp Sample Mating Cnnectr: Amp (IDC Crimp) Table 10: IDAN- DM Pin Subminiature "D" Cnnectr IDAN Pin# Signal DM35424 Pin # 1 AGND CN AGND CN DAC2 Channel 0 CN AGND CN ADC1 Channel 0+ CN ADC1 Channel 0- CN AGND CN AGND CN DAC2 Channel 2 CN AGND CN ADC1 Channel 1+ CN ADC1 Channel 1- CN AGND CN AGND CN DAC2 Channel 2 CN AGND CN ADC1 Channel 2+ CN ADC1 Channel 2- CN AGND CN AGND CN DAC2 Channel 3 CN AGND CN ADC1 Channel 3+ CN ADC1 Channel 3- CN AGND CN AGND CN DAC3 Channel 0 CN AGND CN ADC1 Channel 4+ CN ADC1 Channel 4- CN AGND CN AGND CN DAC3 Channel 1 CN AGND CN24 34 Table 9: IDAN- DM Pin Subminiature "D" Cnnectr IDAN Pin# Signal DM35424 Pin # 35 ADC1 Channel 5+ CN ADC1 Channel 5- CN AGND CN AGND CN DAC3 Channel 2 CN AGND CN ADC1 Channel 6+ CN ADC1 Channel 6- CN AGND CN AGND CN DAC3 Channel 3 CN AGND CN ADC1 Channel 7+ CN ADC1 Channel 7- CN AGND CN AGND CN N/C 52 N/C 53 N/C 54 N/C 55 N/C 56 N/C 57 N/C 58 N/C 59 N/C 60 N/C 61 N/C 62 N/C 63 N/C 64 N/C 65 N/C 66 N/C 67 N/C 68 N/C RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

23 AIO 1-8 Cnnectr - 62-pin High Density D Female Cnnectr Cnnectr Part #: VALCONN HDB-62S Sample Mating Cnnectr: VALCONN HDB-62P Table 11: IDAN- DM Pin High Density "D" Cnnectr IDAN Pin# Signal DM35424 Pin # 1 AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN Reserved 19 Reserved 20 Reserved 21 Reserved 22 AGND CN ADC0 Channel 0+ CN AGND CN ADC0 Channel 1+ CN AGND CN ADC0 Channel 2+ CN AGND CN ADC0 Channel 3+ CN AGND CN ADC0 Channel 4+ CN14 29 Table 11: IDAN- DM Pin High Density "D" Cnnectr IDAN Pin# Signal DM35424 Pin # 32 AGND CN ADC0 Channel 5+ CN AGND CN ADC0 Channel 6+ CN AGND CN ADC0 Channel 7+ CN AGND CN Reserved 40 Reserved 41 Reserved 42 Reserved 43 DAC0 Channel 0 CN ADC0 Channel 0- CN DAC0 Channel 1 CN ADC0 Channel 1- CN DAC0 Channel 2 CN ADC0 Channel 2- CN DAC0 Channel 3 CN ADC0 Channel 3- CN DAC1 Channel 0 CN ADC0 Channel 4- CN DAC1 Channel 1 CN ADC0 Channel 5- CN DAC1 Channel 2 CN ADC0 Channel 6- CN DAC1 Channel 3 CN ADC0 Channel 7- CN Reserved 60 Reserved 61 Reserved 62 Reserved RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

24 AIO 5-16 Cnnectr - 62-pin High Density D Female Cnnectr Cnnectr Part #: VALCONN HDB-62S Sample Mating Cnnectr: VALCONN HDB-62P Table 12: IDAN- DM Pin High Density "D" Cnnectr IDAN Pin# Signal DM35424 Pin # 1 AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN Reserved 19 Reserved 20 Reserved 21 Reserved 22 AGND CN ADC1 Channel 0+ CN AGND CN ADC1 Channel 1+ CN AGND CN ADC1 Channel 2+ CN AGND CN ADC1 Channel 3+ CN AGND CN ADC1 Channel 4+ CN24 29 Table 11: IDAN- DM Pin High Density "D" Cnnectr IDAN Pin# Signal DM35424 Pin # 32 AGND CN ADC1 Channel 5+ CN AGND CN ADC1 Channel 6+ CN AGND CN ADC1 Channel 7+ CN AGND CN Reserved 40 Reserved 41 Reserved 42 Reserved 43 DAC2 Channel 0 CN ADC1 Channel 0- CN DAC2 Channel 1 CN ADC1 Channel 1- CN DAC2 Channel 2 CN ADC1 Channel 2- CN DAC2 Channel 3 CN ADC1 Channel 3- CN DAC3 Channel 0 CN ADC1 Channel 4- CN DAC3 Channel 1 CN ADC1 Channel 5- CN DAC3 Channel 2 CN ADC1 Channel 6- CN DAC3 Channel 3 CN ADC1 Channel 7- CN Reserved 60 Reserved 61 Reserved 62 Reserved RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

25 DIO Cnnectrs - 15-pin D Female Cnnectr Cnnectr Part #: Amp Sample Mating Cnnectr: Amp Table 13: IDAN- DM Pin "D" Cnnectr IDAN Pin# Signal DM35424 Pin # 1 PORT0_0 CN6 1 2 PORT0_2 CN6 3 3 PORT0_4 CN6 5 4 PORT0_6 CN6 7 5 PORT0_8 CN6 9 6 PORT0_10 CN PORT0_12 CN GND CN PORT0_1 CN PORT0_3 CN PORT0_5 CN PORT0_7 CN PORT0_9 CN PORT0_11 CN PORT0_13 CN6 14 RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

26 4.4.2 DM35224 EXTERNAL I/O CONNECTORS AIO 1-8 Cnnectr - 68-pin Subminiature D Female Cnnectr Cnnectr Part #: Amp Sample Mating Cnnectr: Amp (IDC Crimp) Table 14: IDAN- DM Pin Subminiature "D" Cnnectr IDAN Pin# Signal DM35424 Pin # 1 AGND CN AGND CN DAC0 Channel 0 CN AGND CN ADC0 Channel 0+ CN ADC0 Channel 0- CN AGND CN AGND CN DAC0 Channel 2 CN AGND CN ADC0 Channel 1+ CN ADC0 Channel 1- CN AGND CN AGND CN DAC0 Channel 2 CN AGND CN ADC0 Channel 2+ CN ADC0 Channel 2- CN AGND CN AGND CN DAC0 Channel 3 CN AGND CN ADC0 Channel 3+ CN ADC0 Channel 3- CN AGND CN AGND CN DAC1 Channel 0 CN AGND CN ADC0 Channel 4+ CN ADC0 Channel 4- CN AGND CN AGND CN DAC1 Channel 1 CN AGND CN14 34 Table 9: IDAN- DM Pin Subminiature "D" Cnnectr IDAN Pin# Signal DM35424 Pin # 35 ADC0 Channel 5+ CN ADC0 Channel 5- CN AGND CN AGND CN DAC1 Channel 2 CN AGND CN ADC0 Channel 6+ CN ADC0 Channel 6- CN AGND CN AGND CN DAC1 Channel 3 CN AGND CN ADC0 Channel 7+ CN ADC0 Channel 7- CN AGND CN AGND CN N/C 52 N/C 53 N/C 54 N/C 55 N/C 56 N/C 57 N/C 58 N/C 59 N/C 60 N/C 61 N/C 62 N/C 63 N/C 64 N/C 65 N/C 66 N/C 67 N/C 68 N/C RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

27 AIO 1-8 Cnnectr - 62-pin High Density D Female Cnnectr Cnnectr Part #: VALCONN HDB-62S Sample Mating Cnnectr: VALCONN HDB-62P Table 15: IDAN- DM Pin High Density "D" Cnnectr IDAN Pin# Signal DM35224 Pin # 1 AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN AGND CN Reserved 19 Reserved 20 Reserved 21 Reserved 22 AGND CN ADC0 Channel 0+ CN AGND CN ADC0 Channel 1+ CN AGND CN ADC0 Channel 2+ CN AGND CN ADC0 Channel 3+ CN AGND CN ADC0 Channel 4+ CN14 29 Table 11: IDAN- DM Pin High Density "D" Cnnectr IDAN Pin# Signal DM35224 Pin # 32 AGND CN ADC0 Channel 5+ CN AGND CN ADC0 Channel 6+ CN AGND CN ADC0 Channel 7+ CN AGND CN Reserved 40 Reserved 41 Reserved 42 Reserved 43 DAC0 Channel 0 CN ADC0 Channel 0- CN DAC0 Channel 1 CN ADC0 Channel 1- CN DAC0 Channel 2 CN ADC0 Channel 2- CN DAC0 Channel 3 CN ADC0 Channel 3- CN DAC1 Channel 0 CN ADC0 Channel 4- CN DAC1 Channel 1 CN ADC0 Channel 5- CN DAC1 Channel 2 CN ADC0 Channel 6- CN DAC1 Channel 3 CN ADC0 Channel 7- CN Reserved 60 Reserved 61 Reserved 62 Reserved RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

28 DIO Cnnectrs - 15-pin D Female Cnnectr Cnnectr Part #: Amp Sample Mating Cnnectr: Amp Table 16: IDAN- DM Pin "D" Cnnectr IDAN Pin# Signal DM35424 Pin # 1 PORT0_0 CN6 1 2 PORT0_2 CN6 3 3 PORT0_4 CN6 5 4 PORT0_6 CN6 7 5 PORT0_8 CN6 9 6 PORT0_10 CN PORT0_12 CN GND CN PORT0_1 CN PORT0_3 CN PORT0_5 CN PORT0_7 CN PORT0_9 CN PORT0_11 CN PORT0_13 CN6 14 RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

29 4.5 Steps fr Installing 1. Always wrk at an ESD prtected wrkstatin, and wear a grunded wrist-strap. 2. Turn ff pwer t the IDAN system. 3. Remve the mdule frm its anti-static bag. 4. Check that pins f the bus cnnectr are prperly psitined. 5. Check the stacking rder; make sure all f the busses used by the peripheral cards are cnnected t the cpumdule. 6. Hld the mdule by its edges and rient it s the bus cnnectr pins line up with the matching cnnectr n the stack. 7. Gently and evenly press the mdule nt the IDAN system. 8. If any bards are t be stacked abve this mdule, install them. 9. Finish assembling the IDAN stack by installing screws f an apprpriate length. 10. Attach any necessary cables t the IDAN system. 11. Re-cnnect the pwer crd and apply pwer t the stack. 12. Bt the system and verify that all f the hardware is wrking prperly. Figure 8: Example IDAN System RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

30 PCIe Bus Analg I/O Cnnectr 5 Functinal Descriptin 5.1 Blck Diagram The Figure belw shws the functinal blck diagram f the DM The varius parts f the blck diagram are discussed in the fllwing sectins. X2 ADC Cnverter X16 Analg Frntend Filter with PGA PCIe x1 FPGA with DMA Engine X4 Vltage Reference X16 DAC Cnverter Buffered Output with Filter EEPROM Digital I/O Cnnectr Figure 9: DM35424 Blck Diagram 5.2 DMA Engine The DM35424 features a FPGA with a built in PCI Express interface and DMA engine. The FPGA cntrls all cmmunicatin between the bus and the cntrl lgic n the bard. The FPGA als features small FIFOs fr use with DMA, which is needed fr cntinuus data transfer. Each DAC and ADC is prvided with its wn FIFO and DMA channel, allwing them t transfer data independent f ne anther. Each DMA channel can be prgrammed t transfer data frm FPGA t PCI bus r frm the PCI bus t the FPGA. Each DMA channel als features a 64-bit PCI addressing and a 16MB maximum buffer fr memry accessing. 5.3 Analg Frnt-End The DM35424 analg frnt-end cnsist f tw filters and a differential prgrammable gain amplifier, PGA. The tw filters are, ne RF filter with a 3dB cutff frequency f 1MHZ and the secnd filter is a single-ple pass filter with a 3dB cutff frequency f 64KHz. Refer t Figure 10 fr analg frnt-end design. RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

31 + 80Ω 100pF DNP Signal Surce - Mux 1MΩ 2.5V 1MΩ 1000pF + PGA - 3KΩ 0Ω 0Ω 820pF DNP + G=1 - AD 80Ω 100pF Figure 10: DM35424 Frnt-End Nte: Fr custm cutff frequency fr frnt-end filter cntact RTD Sales. The DM35424 als features fur input mdes. These mdes can be selected by using the CHn_FRONT_END_CONFIG (Maskable Read/Write) register f the ADC n page 43. A descriptin f each mde can be fund belw. DAC Lpback Mde The DAC Lpback mde is a single-ended mde which the DAC channel is cnnected internally t its crrespnding ADC channel. Table 17 belw shws the DAC channel with its crrespnding ADC channel. The ADC input must stay within ±2.5V, at a gain f 1, with respect t the bard s vltage reference (2.5V). Table 17: Crrespnding DAC t ADC channel DAC Channel ADC Channel DAC0 Channel 0 ADC0 Channel 0 DAC0 Channel 1 ADC0 Channel 1 DAC0 Channel 2 ADC0 Channel 2 DAC0 Channel 3 ADC0 Channel 3 DAC1 Channel 0 ADC0 Channel 4 DAC1 Channel 1 ADC0 Channel 5 DAC1 Channel 2 ADC0 Channel 6 DAC1 Channel 3 ADC0 Channel 7 DAC2 Channel 0 ADC1 Channel 0 DAC2 Channel 1 ADC1 Channel 1 DAC2 Channel 2 ADC1 Channel 2 DAC2 Channel 3 ADC1 Channel 3 DAC3 Channel 0 ADC1 Channel 4 DAC3 Channel 1 ADC1 Channel 5 DAC3 Channel 2 ADC1 Channel 6 DAC3 Channel 3 ADC1 Channel 7 RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

32 Single-Ended Psitive Input Mde In single-ended psitive input mde, the input signal is measured in reference t the bard s GND. In this mde the input signal is cnnected t input ADC0 Channel 1+ thrugh ADC1 Channel 8+ and the lw side t any f the GND pins available n the Analg Cnnectr. When in single-ended psitive input mde, the high side must stay within ±2.5V, at a gain f 1, with respect t the bard s vltage reference (2.5V). Single-Ended Negative Input Mde In single-ended negative input mde, the input signal is measured in reference t the bard s GND. In this mde the input signal is cnnected t input ADC0 Channel 1- thrugh ADC1 Channel 8- and the lw side t any f the GND pins available n the Analg Cnnectr. When in single-ended negative input mde, the high side must stay within ±2.5V, at a gain f 1, with respect t the bard s vltage reference (2.5V). Differential Input Mde In this mde yur signal surce may r may nt have a separate grund reference. In differential mde, the high side input is measured in reference t the lw side input. In this mde yu cnnect the high side f the input signal t the analg input, ADC0 Channel 1+ thrugh ADC1 Channel 8+, and cnnect the lw side t crrespnding ADC - pin. When in differential mde, bth the high and lw side must stay within ±2.5V, at a gain f 1, with respect t the bard s vltage reference (2.5V). In mst cases, the bard grund must still be attached t the device that is generating the input signal. 5.4 Analg t Digital Cnverter The DM35424 uses a 24 bit delta sigma ADC cnverter, which prvides a very high digital reslutin f the dynamic input vltage. This ADC cnverter has a max thrughput rate f 105 KHz, allwing cnversin speeds up t 9.6µs. This ADC features simultaneus sampling fr all 16 channels, an internal antialiasing filter and fur different peratinal mdes allwing the user t ptimize fr speed, reslutin and pwer. The DM35424 cnversins are cntrlled by a pacer clck and the sampling rati set by the delta sigma ADC. (This rati is listed in Sampling n page 43.) Each ADC cnverter supprts a 511 sample FIFO fr DMA. Each sample is 32 bits INITIALIZATION There are several steps t initialize the Analg t Digital cnverter. The initializatin prepares the cnverter and the frnt-end t capture samples. Fllwing the example prgrams and using the drivers prvided by RTD will ensure that these steps are fllwed in the crrect rder. Initializatin f the ADC is perfrmed as fllws: 1. Set the ADC t the Uninitialized state (MODE = Uninitialized) 2. Setup the DMA fr the channel 3. Set the input mde (CH_FRONT_END_CONFIG) 4. Delay fr at least 3us. This allws the frnt-end t settle. 5. Set the AD_CONFIG register. 6. Set the start and stp triggers (START_TRIG, STOP_TRIG) 7. Set the clck surce (CLK_SOURCE) 8. Set the sample rate (CLK_DIV_CNTR) 9. Set the Pre and/r Pst Capture cunters (PRE_TRIGGER_CAPTURE, POST_STOP_CAPTURE) 10. Set the ADC t the Reset state (MODE = Reset) 11. Start the DMA 12. Start the ADC (MODE = G) ANALOG TO DIGITAL CONVERTER DELAY The Delta-Sigma cnverter used n this bard has a linear phase filter. Linear phase filters exhibit cnstant delay times versus frequency, r cnstant grup delay. Hwever, there is a lng delay frm the time that a sample is taken until it is captured by the FIFO. On this bard, that delay is either 39 samples in High-Reslutin mde, r 38 samples in all ther mdes. The delay can be viewed as an additinal FIFO with a fixed amunt f data in it. All f the data that is visible t the user is delayed by 38 (r 39) samples. After the ADC is initialized, it will cntinue t sample until the bard is reset, r the ADC is placed int an uninitialized state. When capturing is started by setting the ADC Mde t G and having a start trigger, the first sample captured is actually 38 (r 39) samples ld. This is imprtant t recgnize when crrelating captured data with ther events. Fr example, if yu are using the rising edge f an external signal as the start trigger, and yu are als sampling that signal, the first 38 (r 39) samples captured will be lw, fllwed by the rising edge. If the applicatin requires crrelatin with a start and stp events, then the first 38 (r 39) samples shuld be discarded, and always cllect 38 (r 39) mre samples than what is needed. (When a Stp Trigger is used, the POST_STOP_CAPTURE register can be used t capture additinal samples) RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

33 This is als true when pausing the ADC. Let s assume a sample rate f 1 Hz using high-reslutin mde. If yu pause the ADC at t=100s, the last sample captured int the FIFO is frm t=61s. The ADC cntinues t sample, but the samples are discarded. If yu then resume sampling at t=200s, the next sample captured int the FIFO is frm t=161s DATA FORMATTING The cnverted data is stred as a signed 32-bit value in ADC channel s CH_LAST_SAMPLE (Read-Only) and in its DMA channel. Belw are the equatins f hw t cnvert stred cnversin data t a vltage. Differential Single-Ended 2.5 Vltage = Gain (2 23 1) Cnversin Data Vltage = [ 2.5 Gain (2 23 (Cnversin Data 0x7FFFFF)] ) 5.5 Digital t Analg Cnverter The DM35424 digital t analg (DAC) circuitry features 16 independent 16-bit analg utput channels with a prgrammable ±5V range. With the use f DMA data can be cntinuusly written t the DAC t prduce a repetitive and nn-repetitive utput wavefrm. Each DAC cnverter supprts a 511 sample FIFO fr DMA. Each sample is 32 bits INITIALIZING THE DAC CONVERTER The fllwing is a list f the typical steps needed t initialize the DAC cnverter and begin sampling 1. Set the DAC t the Uninitialized state (MODE = Uninitialized) 2. Setup the DMA fr the channel 3. Set the start and stp triggers (START_TRIG, STOP_TRIG) 4. Set the clck surce (CLK_SOURCE) 5. Set the sample rate (CLK_DIV_CNTR) 6. Set the Pst Capture cunter ( POST_STOP_CAPTURE) 7. Set the DAC t the Reset state (MODE = Reset) 8. Start the DMA 9. Start the DAC (MODE = G) 5.6 Digital I/O The DM35424 has 14 buffered TTL/CMOS digital I/O lines, which can be used t transfer data between the system and external devices. The 14 bits can be prgrammed as either inputs r utputs. 5.7 Vltage Reference The DM35424 has an adjustable vltage reference cntrlled by a digital ptentimeter. This allws the vltage references that are used fr the ADC s and DAC s t be adjusted by ±0.5%. By adjusting the reference t a partially ADC r DAC, yu can crrect the gain errr f the device. RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

34 6 Register Address Space The DM35424 was built as a mdular design, which allws each bard functin t have its wn Functinal Blck (FB). Each functinal blck was design t wrk independent f each ther. Fr this reasn, we prvide individual DMA channels, interrupts, clck, and FIFO t each functinal blck. The registers are described by their PCIe Base Address Register (BAR), which is defined in the PCI cnfiguratin space fr this bard. The cnfiguratin space is generally handled by the perating system. Fr mre infrmatin n hw t use the cnfiguratin space, cnsult the PCI Lcal Bus Specificatin, Revisin 3.0 frm the PCI-SIG. Register Types There are several different types f registers that are referred t in this sectin. A descriptin f each type is belw. Read/Write Registers: The value that is written t this register can als be read back. Maskable Registers: This is a 32 bit register that cnsists f 16-bit data field in the upper wrd and a 16-bit mask value in the lwer wrd. Fr each bit in the data field, it is nly written t the register if the crrespnding bit in the mask field is 1. Sticky Registers: This is a status read register. When bit in this register has a value f 1, a 1 needs written t that bit t reset the register t 0. This is typically used fr interrupt status registers. Read Only: This register can nly be read. NOTE: Writing t Read-Only registers may have unexpected results. Clck Surce Clck surces can serve as either sample clcks fr functin blcks, r triggers fr starting and stpping them. Functin blcks can drive a CLK_BUSn with a CLK_SRC (see the register descriptins fr details n the pssible values fr CLK_SRC), and ther functin blcks then trigger frm that clck. This is what lets multiple functin blcks start at the same time, r stp n the same trigger. Fr example, t have all functin blcks start the same time as ADC0, yu wuld set ADC0 t drive CLK_BUS2 with its start trigger. Yu wuld then set all ther functin blcks t use CLK_BUS2 as their start trigger, and then start them. They will wait fr the start trigger n CLK_BUS2 befre they start. Start ADC0, and all f the functin blcks will start with it. Belw is the list f clck surces and the register value needed t select the surce. These clck surces are used in the functinal blcks belw. 0x00: System clck/immediate 0x01: Never 0x02: CLK_BUS2 0x03: CLK_BUS3 0x04: CLK_BUS4 0x05: CLK_BUS5 0x06: CLK_BUS6 0x07: CLK_BUS7 0x08: Channel Threshld One f the channels has exceeded the High r Lw threshld. 0x09: Channel Threshld Inverted All f the channels are within the High and Lw threshld. 0x0A: 0x0B: 0x0C: 0x0D: 0x0E: 0x0F: CLK_BUS2 Inverted CLK_BUS3 Inverted CLK_BUS4 Inverted CLK_BUS5 Inverted CLK_BUS6 Inverted CLK_BUS7 Inverted RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

35 6.1 BAR0 General Bard Cntrl The BAR0 regin is a Memry Mapped register space which cntains sme glbal registers. It als cntains a table describing the different Functin Blcks f the bard, and the ffsets int BAR2 f the registers fr that Functin Blck. Fr maximum flexibility, the user must read the table in BAR0 t calculate the ffset t each Functin Blck in BAR2. Table 18: BAR0 Registers Offset 0x03 0x02 0x01 0x00 0x00 GBC_BRD_RST GBC_EOI GBC_REV GBC_FMT 0x04 GBC_PDP 0x08 GBC_BUILD 0x0C Reserved GBC_SYS_CLK_FREQ 0x10 GBC_IRQ_STATUS 0x14 0x18 GBC_DIRQ_STATUS 0x1C 0x20 FB0_ID 0x24 FB0_OFFSET 0x28 FB0_OFFSET_DMA 0x2C Reserved 0x30 FB1_ID 0x34 FB1_OFFSET 0x38 FB1_OFFSET_DMA 0x3C Reserved 0x20+0x10*n FBn_ID 0x24+0x10*n FBn_OFFSET 0x28+0x10*n FBn_OFFSET_DMA 0x2C+0x10*n Reserved 0xA0 FB8_ID 0xA4 FB8_OFFSET 0xA8 FB8_OFFSET_DMA 0xAC Reserved GBC_BRD_RST (READ/WRITE) This register is used t send a reset cmmand t the bard. Write 0xAA t this register t reset the bard GBC_EOI (READ/CLEAR) This register is used t acknwledge an interrupt. It is used t safeguard against missing an interrupt. At the end f the Interrupt Service Rutines (ISR), write a 0x01 t this register. If there is anther interrupt pending in the status registers, the interrupt line is tggled (Legacy Mde), r anther interrupt is sent (MSI Mde) GBC_REV (READ-ONLY) This register cntains the FPGA revisin fr this bard. A=1, B=2, etc GBC_FMT (READ-ONLY) This register cntains the frmat ID that is used in this bard. The current value is 0x GBC_PDP (READ-ONLY) This register cntains the PDP number fr this bard GBC_BUILD (READ-ONLY) This register cntains a unique 32-bit build number fr the FPGA cde. RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

36 6.1.7 GBC_SYS_CLK_FREQ (READ ONLY) This register cntains the measured frequency f the system clck. Units are 10 khz, i.e. (Frequency in Hertz) = (GBC_SYS_CLK_FREQ * 10 khz). This value is nt available (will read 0) until 100us after a Bard Reset, and is cntinually updated GBC_IRQ_STATUS (READ/CLEAR) This is a 64-bit interrupt status register fr nn-dma interrupts. Each bit in this register crrespnds t ne f the Functin Blcks; bit 0 crrespnds t FB0 (whse ID and OFFSET are at 0x020), etc. Bits 60 thrugh 63 are reserved. This is a Sticky Register, s the user clears it by writing a 1 t the apprpriate bit GBC_DIRQ_STATUS (READ/CLEAR) This is a 64-bit interrupt status register fr DMA interrupts. Each bit in this register crrespnds t ne f the Functin Blcks; bit 0 crrespnds t FB0 (whse ID and OFFSET are at 0x020), etc. Bits 60 thrugh 63 are reserved. This is a sticky register, and the user clears it by writing a 1 t the apprpriate bit FBN_ID (READ-ONLY) This is a 32-bit value that identifies the type f Functin Blck in slt n. 0x ADC 0x DAC 0x0000F000 Vltage Reference 0x Digital I/O 0x0000F001 Temperature Sensr FBN_OFFSET (READ-ONLY) This is the ffset frm the beginning f the Functinal Blck sectin in BAR2 that this Functinal Blck resides in FBN_OFFSET_DMA (READ-ONLY) This is the ffset frm the beginning f the Functinal Blck sectin in BAR2 that the Functinal Blck DMA Registers reside in. RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

37 6.2 BAR2 Functinal Blck Standard DMA This sectin describes a standard DMA implementatin is used by the Functinal Blcks. There is a single DMA engine that services all f the DMA channels used by the Functin Blck. Each DMA channel has a blck f registers assciated with it t cnfigure the DMA channel, as well as set up the descriptrs fr the buffers in system memry. In the sectins belw, m is used t enumerate the DMA channels, and n is used t enumerate the buffer descriptrs within a channel. Table 19: DMA Registers Offset 0x03 0x02 0x01 0x00 D + 0x00 FB_DMAm_Stat_Underflw FB_DMAm_Stat_ FB_DMAm_Setup FB_DMAm_Actin Overflw D + 0x04 FB_DMAm_Current_Buffer FB_DMAm_Cunt D + 0x08 FB_DMAm_RD_FIFO_CNT FB_DMAm_WR_FIFO_CNT D + 0x0C FB_DMAm_Last_Actin FB_DMAm_Stat_ Cmplete FB_DMAm_Stat_ Invalid FB_DMAm_Stat_ Used D + 0x10 FB_DMAm_CTRL0 FB_DMAm_STAT0 Reserved D + 0x14 Reserved FB_DMAm_SIZE0 D + 0x18 FB_DMAm_ADDRESS0 D + 0x1C D + 0x20 FB_DMAm_CTRL1 FB_DMAm_STAT1 Reserved D + 0x24 Reserved FB_DMAm_SIZE1 D + 0x28 FB_DMAm_ADDRESS1 D + 0x2C D + 0x10 + FB_DMAm_CTRLn FB_DMAm_STATn Reserved (0x10 * n) D + 0x14 + Reserved FB_DMAm_SIZEn (0x10 * n) D + 0x18 + FB_DMAm_ADDRESSn (0x10 * n) D + 0x1C + (0x10 * n) FB_DMAM_ACTION (READ/WRITE) This register is the verall cntrl fr this DMA channel. After writing t the Actin register, the user shuld pll the Last_Actin register (belw) until it reads the same value. This shws that the actin has been perfrmed by the DMA state machine. This is especially imprtant when entering and exiting the Clear state. 0x00 = Clear: Clear the Current Buffer field, the internal ffset cunters, and the FIFO. DMA is stpped. 0x01 = G: Starts DMA 0x02 = Pause: DMA transfers are stpped, but all internal registers maintain their state. During PAUSE yu will still receive Stat_Underflw and Stat_Overflw interrupts. After PAUSE, yu may transitin t GO r CLEAR. 0x03 = Halt: Buffer has been filled that has the HALT bit set, attempted t use a buffer with the Valid bit cleared. After HALT, yu must transitin t CLEAR. NOTE: The DMA engine als writes t this register when a buffer is cmpleted with the HALT bit set, r it encunters an invalid buffer. When changing this register frm the G t the Clear state, be sure t read it back t make sure the DMA engine did nt change it t the Halt state FB_DMAM_LAST_ACTION (READ/WRITE) The DMA Engine writes the value f FB_DMAm_Actin t this register after it has cmpleted the actin. This indicates t the user that the last cmmand has been prcessed. It specifically aids the transitin t the Clear state. When transitining t Clear, the user shuld wait until FB_DMAm_Last_Actin indicates that the Clear has been prcessed befre initiating any ther Actin changes. The user may als write a value t this register and then pll the register t see when the value changes. This methd can be used t detect when the DMA engine services the channel withut an Actin change. RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

38 6.2.3 FB_DMAM_SETUP (READ/WRITE) B0: IntEna: Set t 1 t enable the DMA engine t generate interrupts n cmpletin f a buffer. B1: ErrIntEna: Set t 1 t enable the DMA engine t generate interrupts n errr. B2: Directin: Set t 1 t transfer frm the bard t the PCI bus. Clear t 0 t transfer frm the PCI bus t the bard. Nte that althugh the DMA channel always supprts bth directins, the Functin Blck that the channel is assciated with may nly supprt ne directin. B3: IgnreUsed: Set t 1 t prevent an errr cnditin when accessing a buffer with the Used bit set. Examples are cntinuus utput frm a DAC, r very large Pre-trigger buffering using system memry FB_DMAM_STAT_USED (READ/WRITE) This register is used t determine the surce f a DMA interrupt. The bits are cleared by writing 0x00 t the byte. Stat_Used will be set regardless f having ErrIntEna set t 1. B0: Used_Desc. Set t 1 by the DMA engine if it attempting t use a descriptr with the Used bit set FB_DMAM_STAT_INVALID (READ/WRITE) This register is used t determine the surce f a DMA interrupt. The bits are cleared by writing 0x00 t the byte. Stat_Invalid will be set regardless f having ErrIntEna set t 1. B0: Invalid_Desc. Set t 1 by the DMA engine if it attempting t use a descriptr with the Valid bit cleared FB_DMAM_STAT_OVERFLOW (READ/WRITE) This register is used t determine the surce f a DMA interrupt. The bits are cleared by writing 0x00 t the byte. Stat_Overflw will be set regardless f having ErrIntEna set t 1. If an verflw ccurs the DMA engine will PAUSE. B0: Overflw (R/C). Set t 1 by the DMA engine if an verflw ccurred n the FIFO FB_DMAM_STAT_UNDERFLOW (READ/WRITE) This register is used t determine the surce f a DMA interrupt. The bits are cleared by writing 0x00 t the byte. Stat_Underflw will be set regardless f having ErrIntEna set t 1. If an underflw ccurs the DMA engine will PAUSE. B0: Underflw (R/C). Set t 1 by the DMA engine if an underflw ccurred n the FIFO FB_DMAM_STAT_COMPLETE (READ/WRITE) This register is used t determine the surce f a DMA interrupt. The bits are cleared by writing 0x00 t the byte. B0: Buffer_Cmplete (R/C). Set t 1 by the DMA engine when a buffer is filled that has the Interrupt bit set FB_DMAM_CURRENT_BUFFER (READ-ONLY) This is the ID fr the buffer that will be used fr the next access. The user may use this t track the prgress f the DMA activity FB_DMAM_COUNT (READ-ONLY) This is the ffset in the DMA buffer fr the next access. The user may use this t track the prgress f the DMA activity. This value is given in bytes FB_DMAM_RD_FIFO_CNT (READ-ONLY) B[9:0] This is the amunt f data available in the read FIFO in bytes. Sftware can use this t determine when the FIFO is empty. A value f 0x3FC indicates that there are 1020 r mre bytes f data available. B15: RD_EMPTY- 1 indicates that the read FIFO is empty FB_DMAM_WR_FIFO_CNT (READ-ONLY) B[9:0] This is the amunt f space available in the write FIFO in bytes. Sftware can use this t determine when the FIFO is full. A value f 0x3FC indicated that there are 1020 r mre bytes f space available. B15: WR_FULL- 1 indicates that the write FIFO is full RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

39 FB_DMAM_ADDRESSN (READ/WRITE) This is the 64-bit PCI address fr DMA Channel m, buffer n. It must be duble-wrd aligned (i.e. b[1:0] are reserved) FB_DMAM_SIZEN (READ/WRITE) This is the size in bytes f the buffer fr DMA Channel m, buffer n. It must be an integer number f duble-wrds (i.e. b[1:0] are reserved). The actual size is FB_DMAm_SIZEn + 4 Bytes. The maximum buffer size is 16MB FB_DMAM_CTRLN (READ/WRITE) B0: Valid: Set t 1 t indicate that this cntains valid infrmatin. The DMA engine will set the errr bit and halt if it is ready t use this descriptr and it is nt valid. B1: Halt: Set t 1 t halt the DMA engine after this buffer is full. B2: Lp: Set t 1 t start back at descriptr 0 after this buffer is full. This has a higher pririty than the HALT bit. B3: Interrupt: Set t 1 t generate an interrupt after this buffer is full. If the last buffer is reached, and the HALT and LOOP bits are bth 0, the DMA engine will lp. If the last buffer is reached, and the HALT and LOOP bits are bth 1, the DMA engine will halt and the Current_Buffer will be set t FB_DMAM_STATN (READ/CLEAR) B0: Used (R/C): DMA engine sets t 1 t indicate that it has cmpletely used this descriptr. The user must clear this bit when it is ready t be used again. The DMA engine will set the errr bit and PAUSE if it is ready t use this descriptr and the Used bit is set, unless the IgnreUsed bit is set. The bits are cleared by writing 0x00 t the byte. RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

40 ADC Channel 6 ADC Channel 5 ADC Channel 4 ADC Channel 3 ADC Channel 2 ADC Channel 1 ADC Channel 0 ADC Cntrl Header 6.3 BAR2 ADC Functinal Blck This Functin Blck is fr an Analg t Digital cnverter. This ADC has multiple channels, hwever all channels must use the same pacer clck. Each channel has a dedicated FIFO and DMA Channel. Table 20: Multi-Channel ADC Functinal Blck Offset 0x03 0x02 0x01 0x00 FB + 0x00 FB_ID FB + 0x04 FB_DMA_BUFFERS FB_DMA_CHANNELS Reserved Reserved FB + 0x08 STOP_TRIG START_TRIG CLK_SRC MODE_STATUS FB + 0x0C CLK_DIV FB + 0x10 CLK_DIV_CNTR FB + 0x14 PRE_TRIGGER_CAPTURE (limited by FIFO size) FB + 0x18 POST_STOP_CAPTURE FB + 0x1C SAMPLE_CNT FB + 0x20 INT_ENA (Sample, Start, Stp, Threshld, Pacer Tick, etc) FB + 0x24 INT_STAT Reserved FB + 0x28 CLK_BUS3 CLK_BUS2 Reserved FB + 0x2C CLK_BUS7 CLK_BUS6 CLK_BUS5 CLK_BUS4 FB + 0x30 AD_CONFIG (Maskable register 16-bit) FB + 0x34 CH0_FRONT_END_CONFIG (Maskable register 16-bit) FB + 0x38 CH0_FIFO_DATA_CNT FB + 0x3C CH0_INT_ENA CH0_INT_STAT CH0_FILTER Reserved FB + 0x40 CH0_THRESH_HIGH FB + 0x44 CH0_THRESH_LOW FB + 0x48 CH0_LAST_SAMPLE FB + 0x4C CH1_FRONT_END_CONFIG (Maskable register 16-bit) FB + 0x50 CH1_FIFO_DATA_CNT FB + 0x54 CH1_INT_ENA CH1_INT_STAT CH1_FILTER Reserved FB + 0x58 CH1_THRESH_HIGH FB + 0x5C CH1_THRESH_LOW FB + 0x60 CH1_LAST_SAMPLE FB + 0x64 CH2_FRONT_END_CONFIG (Maskable register 16-bit) FB + 0x68 CH2_FIFO_DATA_CNT FB + 0x6C CH2_INT_ENA CH2_INT_STAT CH2_FILTER Reserved FB + 0x70 CH2_THRESH_HIGH FB + 0x74 CH2_THRESH_LOW FB + 0x78 CH2_LAST_SAMPLE FB + 0x7C CH3_FRONT_END_CONFIG (Maskable register 16-bit) FB + 0x80 CH3_FIFO_DATA_CNT FB + 0x84 CH3_INT_ENA CH3_INT_STAT CH3_FILTER Reserved FB + 0x88 CH3_THRESH_HIGH FB + 0x8C CH3_THRESH_LOW FB + 0x90 CH3_LAST_SAMPLE FB + 0x94 CH4_FRONT_END_CONFIG (Maskable register 16-bit) FB + 0x98 CH4_FIFO_DATA_CNT FB + 0x9C CH4_INT_ENA CH4_INT_STAT CH4_FILTER Reserved FB + 0xA0 CH4_THRESH_HIGH FB + 0xA4 CH4_THRESH_LOW FB + 0xA8 CH4_LAST_SAMPLE FB + 0xAC CH5_FRONT_END_CONFIG (Maskable register 16-bit) FB + 0xB0 CH5_FIFO_DATA_CNT FB + 0xB4 CH5_INT_ENA CH5_INT_STAT CH5_FILTER Reserved FB + 0xB8 CH5_THRESH_HIGH FB + 0xBC CH5_THRESH_LOW FB + 0xC0 CH5_LAST_SAMPLE FB + 0xC4 CH6_FRONT_END_CONFIG (Maskable register 16-bit) FB + 0xC8 CH6_FIFO_DATA_CNT FB + 0xCC CH6_INT_ENA CH6_INT_STAT CH6_FILTER Reserved FB + 0xD0 CH6_THRESH_HIGH FB + 0xD4 CH6_THRESH_LOW RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

41 ADC Channel 7 Table 20: Multi-Channel ADC Functinal Blck Offset 0x03 0x02 0x01 0x00 FB + 0xD8 CH6_LAST_SAMPLE FB + 0xDC CH7_FRONT_END_CONFIG (Maskable register 16-bit) FB + 0 xe0 CH7_FIFO_DATA_CNT FB + 0xE4 CH7_INT_ENA CH7_INT_STAT CH7_FILTER Reserved FB + 0xE8 CH7_THRESH_HIGH FB + 0xEC CH7_THRESH_LOW FB + 0xF0 CH7_LAST_SAMPLE FB_ID (READ-ONLY) This is the functinal blck ID. This registry shuld read 0x fr the ADC functinal blck FB_DMA_CHANNELS (READ -ONLY) This register cntains the number f DMA Channels in this Functin Blck. Each Channel cntains a cntrl register, and a set f Buffer Descriptr Registers FB_DMA_BUFFERS (READ-ONLY) This register cntains the number f Buffer Descriptrs in each DMA Channel MODE_STATUS (READ/WRITE, READ-ONLY) Selects the current mde f peratin and indicates its triggering status. B[3:0]: Mde B[7:4]: Status 0x04: Uninitialized. This is the pwer-n state. N cnverter initializatin has taken place. Sampling is stpped, and all cunters are reset and the triggering state machine is reset. Transitin t any f the ther Mdes will start cnverter initializatin (sampling will nt start until initializatin is cmplete). 0x00: Reset. Sampling is stpped. All cunters are reset and the triggering state machine is reset. 0x01: Paused. Sampling is stpped, but the cunters and triggering state machine maintain their state. 0x02: G, Single-Sht. After filling the buffer with the Pst-Stp samples, capturing stps. The Mde must be set back t RESET in rder t capture mre samples. 0x03: G, Re-arm. After filling the buffer with the Pst-Stp samples and the FIFO is empty, the triggering state machine is restarted, i.e. FIFO is filled with Pre-Start samples and waits fr a start trigger. 0x08: Uninitialized The status when in the Uninitialized mde and the cnverter requires initializatin. 0x09: Initializing 0x00: Stpped The status when in the Reset mde, r in the Uninitialized mde and the cnverter des nt require initializatin. 0x01: Filling Pre-Trigger buffer 0x02: Waiting fr start trigger 0x03: Sampling/Waiting fr stp trigger 0x04: Filling Pst-Stp buffer 0x05: Wait t re-arm Waiting until lcal FIFO is empty s the pre-trigger buffer can be filled. 0x07: Dne capturing CLK_SRC (READ/WRITE) Selects the surce fr CLK_DIV frm the clck bus. Refer t Clck Surce n page 34 fr list f valid values. RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

42 6.3.6 START_TRIG (READ/WRITE) Selects the start trigger frm the clck bus. CLK_DIV will start cunting after the start trigger, unless PRE_TRIGGER_CAPTURE is nn-zer in which case CLK_DIV will start cunting immediately. Refer t Clck Surce n page 34 fr list f valid values STOP_TRIG (READ/WRITE) Selects the stp trigger frm the clck bus. Refer t Clck Surce n page 34 fr list f valid values CLK_DIV (READ/WRITE) Divider fr the pacer clck. Pacer Clck Frequency = (Clk_Src_Frequency) / (1 + CLK_DIV). If synchrnizing with the pacer clck frm anther Functin Blck (by using ne f the CLK_BUS signals), this is typically set t CLK_DIV_CNTR (READ ONLY) The current value f the Clck Divide Cunter. This cunter starts at a value f CLK_DIV, and cunts dwn. When it reaches zer, a sample is taken. This is useful when using a slw sample clck PRE_TRIGGER_CAPTURE (READ/WRITE) Number f samples t cllect befre the Start Trigger. The length is limited by the FIFO size writing a value larger than the FIFO size will have indeterminate results POST_STOP_CAPTURE (READ/WRITE) Number f samples t cllect after the Stp Trigger SAMPLE_CNT (READ ONLY) Ttal number f samples cllected. This des nt increment in while in the Waiting Fr Start Trigger state. It als cntinues cunting after a Re-Arm INT_ENA (MASKABLE READ/WRITE) Each bit crrespnds t an interrupt surce. A value f 1 enables the surce, and a value f 0 disables it. See belw fr a descriptin f the surces INT_STAT (READ/CLEAR) Each bit crrespnds t an interrupt surce. Reading a value f 1 indicates that an event has ccurred. Reading a value f 0 indicates that the event has nt ccurred. Writing a 1 will clear that bit. B0: Sample A sample has been taken. B1: Channel Threshld One f the channels has exceeded the High r Lw threshld. Check the CH_THRESH_STAT registers. B2: Pre-Start Buffer Filled B3: Start Trigger B4: Stp Trigger CLK_BUSN B5:Pst-Stp Buffer Filled B6: Sampling has cmpleted and the FIFO is empty (all data transferred t hst) B7: Pacer The pacer clck has ticked. NOTE: If a CLK_BUS is unassigned in all functin blcks, it defaults t System Clck/Immediate. RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

43 Selects a surce t drive nt Clck Bus N. That clck bus can then be used by a different functin blck as a clck surce r trigger. A functin blck can drive multiple different Clck Buses. Hwever, a Clck Bus N shuld nt be driven by mre than ne functin blck at the same time r the clck signal will be undefined. B[7:0]: 0x00: Disables Clck Surce 0x80: Sample A sample has been taken. 0x81: Channel Threshld One f the channels has exceeded the High r Lw threshld. Check the CH_THRESH_STAT registers. 0x82: Pre-Start Buffer Filled 0x83: Start Trigger 0x84: Stp Trigger 0x85: Pst-Stp Buffer Filled 0x86: Sampling has cmpleted and the FIFO is empty (all data transferred t hst) 0x87: Pacer The pacer clck has ticked AD_CONFIG (MASKABLE READ/WRITE) This prvides up t 16 bits t cnfigure the ADC Cnverter. Sampling B[2]: MODE1 B[1]: MODE0 B[0]: CLKDIV The fllwing Table describes the maximum sample rates and the Pacer Clck t Sample Clck ratis Mde MODE[1:0] CLKDIV Pacer:Sample Max Pacer Clck(MHz) Max Sample Rate(SPS) High-Speed : ,468 High-Reslutin : ,734 Lw-Pwer : ,734 Lw-Speed , CHN_FRONT_END_CONFIG (MASKABLE READ/WRITE) This register prvides cnfigure t the Frnt End fr this ADC Channel B[7]: /PWDN 0 = ADC Channel is in lw pwer mde 1= ADC channel is active B[6]: /PGASD 0 = PGA in shutdwn mde 1= PGA active B[5]: SW_EN 0 = input switch tri-state 1 = Input switch enabled B[4:3]: SW_IN[1:0] B[2:0]: PGA_A[2:0] SW_IN[1:0] = 00: DAC Lpback SW_IN[1:0] = 01: Single- Ended Psitive Input (Uniplar Mde) SW_IN[1:0] = 10: Single- Ended Negative Input (Uniplar Mde) SW_IN[1:0] = 11: Differential Input (Biplar Mde) Sets the Range/Gain as belw: Table 21: Differential Mde Range/Gain Table PGA_A[2:0] Range Gain 000 ± 2.5 V ± 1.25 V ± 625 mv ± mv ± mv ± mv 32 Table 22: Single-Ended Mde Range/Gain Table PGA_A[2:0] Range Gain V V V V V V 32 RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual

44 011 ± mv ± mv V V 128 NOTE: The Frnt End may take up t 100us t settle after writing t this register CHN_FIFO_DATA_CNT (READ) This register shws the current sample cunt that is available in the ADC channel FIFO CHN_FILTER (READ/WRITE) The prgrammable digital filter prvides a single ple Infinite Impulse Respnse (IIR) filter n each channel. This a unity-gain filter. The filtered data has a value f: D n = D n 1 (2 ORDER 1) + NewSample 2 ORDER The respnse f the filter is shwn in the Figure 2 belw. Table 1 belw shws the -3dB cutff fr each f the filter settings. Bth the figure and the table are relative t the per-channel sample rate (fs). Figure 11: Filter Respnse with each ORDER Value ORDER -3 db Cutff 0 n/a * fs * fs * fs * fs * fs * fs * fs RTD Embedded Technlgies, Inc DM35424/DM35224 User s Manual