EE 109 HW 7 Processor Organization

Transcription

1 EE 9 HW 7 Processor Organization Name: ue: ee Website Blackboard ONLY ubmission. core: In this homework we will design a simple computer system (processor hardware and instruction set) to evaluate Boolean expressions that use N, OR, and NOT operations. For example, we want to be able to evaluate an expression like: (~X+X)(X2+~X3)(~X+X3) Here are some important choices we have made about the processor: The equations will use at most 8 unique Boolean variables: X through X7. Each variable (Xi) will have a single value: = True and = False and be stored in a small 8 row x column memory. We will use a register-to-register architecture (inputs and outputs of an instruction will be taken from and stored to a register) with three -bit registers: R, R, R2. The computer system will have a single LE to display the result of the expression (ON = = True, OFF = = False). s we define the instruction set, we will obviously need to have N, OR, and NOT instructions. In addition, we will need an instruction to LO a Boolean variable (one of X-X7) into a register (either R, R, or R2) which performs Rx = Xi. Finally, we will need an OUTput instruction to take the value from one of the registers and save it to the output register which connects to the LE. Example ssembly Code s an example, suppose we need to compute: (~X+X) ~(X2+~X3) we could use the assembly code: LO R, X (R = X) NOT R (R = ~R) LO R, X (R = X) OR R, R (R = R) LO R, X2 (R = X2) LO R2, X3 (R2 = X3) NOT R2 (R2 = ~R2) OR R, R2 (R = R2) NOT R (R = ~R) N R, R (R &= R) OUT R

2 The instruction set and its machine code format is defined below: [Note: In the assembly code (the src/destination) is listed first but in the machine code format comes after Rs.] N, Rs Rs &= Rs OR, Rs Rs = Rs NOT = ~ OUT out = LO, Xi 3-bits 3-bits i = var num = Xi Reserved for future use x 6-bits out & unchanged HW 7a et esign and ssembly coding. (4 pts.) Billy Bruin want to add a new instruction ET which would put the constant into without getting any variables from the variable memory or assuming any specific initial register values. Tommy Trojan said this could already be achieved using 3 instructions. Complete the blanks below to show Billy how this can be done: OR R, R NOT R, R 2

3 2. (9 pts.) Fill in the blanks below in the assembly code to correctly evaluate the expression below: (~X+X)(X2+~X3+~X4) ddress LO R, NOT R LO, X OR R, R LO, X2 LO R2, NOT R2 OR, R2 LO, X4 NOT OR, R2 N, R OUT R 3. ( pts.) Given the code you found above, correctly convert the LT 5 instructions to 8-bit machine code. Enter each instruction's machine code as 2 hex digits preceded by 'x'. ssembly 8. LO, X4 = 9. NOT. OR, R2. N, R 2. OUT R Machine Code 8.. x 9. x. x. x 2. x 4. (4 pts.) uppose the processor could have more than 3 registers if needed. How many registers (minimum) would be required to be able to correctly evaluate the expression below (in any order you like as long as it does not alter the intended result). (X~X2 + ~X3X4)(X5~X6 + ~X7X8) 5. (4 pts.) Given the expression from the previous problem (above), suppose you could transform the equation by applying Boolean algebra theorems. How many registers (minimum) would be required to be able to correctly evaluate the expression. 6. (4 pts.) True / False: Putting aside the impact on the hardware, we could add a 4 th register (R3) without modifying the bit layout of the machine code format of the instruction set. 3

4 Processor atapath: To compute the Boolean equations we will design a unit to perform N, OR, NOT, and pass B. Rather than calling it an LU (rithmetic and Logic Unit) we will call it a BLU (Boolean Logic Unit) Boolean Logic Unit (BLU) 4-to- mux PC PC PC2 PC3 PC4 5-bit dder B 5-bit Reg Prog. Counter CLR REET Fetch Logic PC PC PC2 PC3 PC x8 Memory I3 I4 I5 I6 I7 Control REL REL REL REL XEL R_L R_L R2_L F OUT_L B F I3 Internal schematic of the Boolean Logic Unit F R R_L R_L R2_L ata Registers R R R2 3-to- mux, REL[:] 3-to- mux, REL[:] R R B & ~ 2-to- mux OUT_L F F Boolean Logic Unit (BLU) R 2-to- mux OUT B & ~ Boolean Logic Unit (BLU) Block ymbol for the Boolean Logic Unit R 2 8x Memory ddr Val X X 2 X2 3 X X6 7 X7 Xi XEL R* 4

5 HW 7b Processor Hardware Organization tudy the schematic on the previous page and try to understand why the various connections exist and then answer the questions. Look at both the machine code format and the processor datapath to answer the following questions. [5 pts. per question]. What processor signals should be connected to REL[:]? 2. What processor signals should be connected to REL[:]? 3. What processor signals should be connected to,f of the BLU? 4. What signals should be connected to the address inputs of the 8x variable memory (i.e. 2,, should be connected to which signals)? 5. For what instruction(s) should XEL be a? 6. What value should XEL be during an OUT instruction? 7. True / False: If desired, the and F signals to the BLU can be considered "on't Care" during a LO instruction? 8. elect which of the following is a correct implementation of OUT_L. a) I6 and ' and ' b) I7' and I6 and I5 c) I7' and I6 d) I7 and I6' and I5' and I4 e) None of the above 9. elect which of the following is a correct implementation of R2_L. a) ((I7' and I6') or (I7' and I6 and I5')) and (' and ) b) and ' c) ((I7' and I5') or (I7' and I6' and I5)) and ( and ') d) I7' and and ' Teresa Trojan noticed that for certain Boolean expressions we may not have to evaluate the entire expression to find the answer. For example, in the expression below if the first term (~X+X) is false, the whole expression will be false. Rather than wasting time evaluating other terms, we could immediately "jump" to the last OUT instruction. Teresa proposed adding a new instruction call JF (Jump if False). It would have format: JF,addr and cause the Program Counter to jump to addr if is False. Otherwise, execution will continue sequentially. We have updated the instruction set and the datapath on the following pages. Please answer the related questions that follow. 5

6 Updated Machine Code Format with JF instruction N, Rs Rs etc.) &= Rs OR, Rs Rs etc.) = Rs NOT = ~ OUT out = 3-bits 3-bits LO, Xi i = var num = Xi JF Rs, addr -bits 5-bits jump address (where to jump) if Rs==: PC=addr else: PC = PC+ 6

7 Updated (but incomplete) Processor atapath for JF instructions PC PC PC2 PC3 PC4 5-bit dder B 2-to-, 5-bit wide mux Y 5-bit Reg Prog. Counter CLR Fetch Logic PC PC PC2 PC3 PC I3 I4 I5 I6 I7 Control REL REL REL REL XEL R_L R_L R2_L I7 I7 I6 I5 Not all may be needed R_L R_L R2_L REET ata Registers R R R2 32x8 Memory 3-to- mux, REL[:] 3-to- mux, REL[:] R R B & ~ 2-to- mux OUT_L F F Boolean Logic Unit (BLU) R 2-to- mux F OUT_L OUT 2 8x Memory ddr Val X X 2 X2 3 X X6 7 X7 Xi XEL R* 7

8 . Complete just the JF instruction at instruction address 4 (we assume the rest is the same from the earlier question regarding this expression). (~X+X)(X2+~X3+~X4) ddress LO R, NOT R LO, X OR R, R JF, LO, X2 LO R2, NOT R2 OR, R2 LO, X4 NOT OR, R2 N, R OUT R. Billy Bruin noticed that a similar tactic to improve performance could be used for certain other expressions that involved ORing term such as: (X X)+(X2 X3 X4) and he proposed adding a JT (Jump if True) instruction. Teresa Trojan said that wouldn t be necessary and suggest instead of an instruction like JT R, addr one could simply use a 2 instruction sequence:, addr 2. Looking at the datapath for the new JF instruction, what processor signals should be connected to input of the 2-to-, 5-bit mux that feeds the PC? 3. What is the minimal logic for the select bit of that mux (i.e. the 2-to-, 5-bit mux that feeds the PC)? 8