GF14LPP-XL AMS Reference Flow for FINFET Technology. Rajashekhar Chimmalagi Design Methodology April 5 th 2016

Transcription

1 GF14LPP-XL AMS Reference Flow for FINFET Technology Rajashekhar Chimmalagi Design Methodology April 5 th 2016

2 Agenda 1 FinFET & FinFET Challenges 2 GF Reference Flows 3 Ref Flow Design 4 Ref Flow Modules 5 Summary GLOBALFOUNDRIES 2

3 Company Highlights REVENUE MORE THAN ~6B* 25,000 2nd Largest Foundry Patents & Applications 250 Customers 18,000 Employees FAB LOCATIONS FAB CAPACITY Burlington East Fishkill Malta Dresden 300mm 200mm Singapore Trusted Foundry 200K Wafers/Mo 133K Wafers/Mo *Based upon analysts estimates GLOBALFOUNDRIES 3

4 Global Manufacturing Capacity: ~7M Wafers/Yr* East Fishkill, New York Malta, New York Burlington, Vermont Dresden, Germany Singapore TECHNOLOGY 90nm 22nm 28nm, 14nm 350nm 90nm 45nm 22nm 180nm 40nm CAPACITY IN WAFERS/MONTH 14,000 (300mm) Up to 60,000 (300mm) 40,000 (200mm) 60,000 (300mm) 68,000 (300mm) 93,000 (200mm) *200mm Equivalents GLOBALFOUNDRIES 4

5 1 FinFET & FinFET Challenges 2 GF Reference Flows 3 Ref Flow Design 4 Ref Flow Modules 5 Summary GLOBALFOUNDRIES 5

6 End of Bulk CMOS Scaling??? Planar CMOS is hitting hard scaling limits at 20nm Planar FET Gate FinFET Gate length shrink enables performance scaling L g Source Halo Drain Shorter gates need higher doping to control leakage Higher V T at given leakage Degraded mobility Increased junction leakage Increased variation Improved gate control of the channel requires less channel doping Lower V T at given leakage Higher mobility Lower variation Much Higher drive in the same area foot-print [2*h+L]

7 14LPP FinFET Delivering Value / Mainstream Today FinFET Offers Break-through Perf. & Power FET is turned on its edge Gate length shrink enables performance scaling L g Device Performance +50% Fully Qualified In Production Today Mature Tech ramping volume, low D0, proven IP platform, ecosystem 78nm Gate Pitch, um 2 Bitcell, Excellent Die Scaling Intrinsically operates at a lower supply voltage ( FD behavior) Reduced off-state leakage Faster switching speed high drive current Total Power -65% 28nm 14LPP Platform enhancements Deliver Value to Customers Strong FinFET Market Traction GLOBALFOUNDRIES 7

8 FinFET Design Challenges Electrical / Circuit Challenges Quantized width, function of number of fins Tuning of drive strength with number of fins Parasitic Challenges 3D structure => change in computation of parasitics MOL extraction Increased gate capacitance Miller effect magnifies this increase V0_CO C A Source C4 C2 C1 Gate C5 C3 Fin Fin Drain Substrate GLOBALFOUNDRIES 8

9 FinFET Layout Challenges Fin alignment/snapping requirements Poly pitch requirements V0_CO Middle-of-line (MOL) routing CA PC FIN CB CA Source Gate Fin Fin Drain Substrate Double patterning Decomposition One Layer Two Masks Complexity of FinFET structures Many more design rules GLOBALFOUNDRIES 9

10 Moving from Planar to FinFET Planar FinFET Continuous Width of Transistor Discrete or Quantized Widths Width is the Diffusion Width No snapping requirement Fewer DRs, less complex device structures Width defined by number of fins Fins snapping is required More DRs, more complex device structures 3-D finfet technology: Etch uniformity requirement Fixed fin thickness/height, quantized widths All device fins need to be aligned to a certain spacing GLOBALFOUNDRIES 10

11 Using Double Patterning to Overcome Lithographic Challenges Mx shape spacing are now so small that current light sources cannot print them reliably Solution is to split the dense shapes into two masks, each with more sparse shapes This process of splitting a single layer into two masks is called double patterning Decomposition One Layer Two Masks Colorless Shapes (M1_drawing) Mask1 Mask1 Mask2 & Mask2 Shapes Shapes (M1_e1, (M1_E1) (M1_E2) M1_e2) GLOBALFOUNDRIES Confidential 11

12 1 Design Challenges at Advanced Nodes 2 GF Reference Flows 3 Ref Flow Design 4 Ref Flow Modules 5 Summary GLOBALFOUNDRIES 12

13 Design Challenges at Advanced Nodes Design challenges at shrinking dimensions Increased performance variation More pronounced parasitic effects Layout dependent effects Explosion of design rules Yield/defect density Need new methodologies and flows to tackle them! GLOBALFOUNDRIES 13

14 Purpose of Reference Flow Ensure our PDKs, EDA tools and third-party libs work together at design-level Provide methodologies and best practices for AMS designs using GLOBALFOUNDRIES processes IP PDK EDA Tools Design Flows & Methodologies Demonstrate GLOBALFOUNDRIES PDK differentiating features and their effective utilization Demonstrate the development of a working design from specification to final physical verification Provide a guided approach to our tool suites and foundry process GLOBALFOUNDRIES 14

15 This image cannot currently be displayed. This image cannot currently be displayed. This image cannot currently be displayed. Features of the Reference Flow Flow steps are presented as modules Results are available as reference Enables check for correct PDK and flow installation Modules are executable and independent from one another Scripted whenever applicable Allows reuse by customer Documented in detail Clear instructions guide user through each step GLOBALFOUNDRIES 15

16 1 FinFET & FinFET Challenges 2 GF Reference Flows 3 Ref Flow Design 4 Ref Flow Modules 5 Summary GLOBALFOUNDRIES 16

17 Design Overview Delay Controlled Oscillators (DCO) DCOs are widely used in PLLs for generating clocks DCO consists of DCO core and Bias current generator Specs Oscillation frequency: 500MHz Tuning range: 0.5GHz +/- 100MHz Power consumption: < 25uA Supply voltage: 1V +/- 200mV Temperature: -40C to 150C GLOBALFOUNDRIES 17

18 Overview of the 14LPP Reference Flow Modules Design used is a Delay Controlled Oscillator (DCO) Ring oscillator (dco_core) block used in most modules GLOBALFOUNDRIES 18

19 1 Design Challenges at Advanced Nodes 2 GF Reference Flows 3 Ref Flow Design 4 Ref Flow Modules 5 Summary GLOBALFOUNDRIES 19

20 GLOBALFOUNDRIES 20 14LPP AMS Ref Flow Modules Cadence Modules Module 1 DCO Circuit Design Other Modules Module 2 Module 3 Unit Cell Partial Layout Unit Cell Device Placement Re-simulation Streamout Netlist PhyVerif GDS / Netlist Generation DRC / LVS / DPT Module 4 Unit Cell Routing PEX PEX Module 5 Unit Extraction Cell Sign-Off Module 6 DCO Assembly Routing Module 7 DCO Sign-Off

21 Module 1: DCO Circuit Design GLOBALFOUNDRIES 21 Objective Functional Design, Characterization over PVT and Exploring LLE, WPE in 14nm FinFET Design Tasks Schematic Creation Delay cell, DCO Tool VSE PDK Features Devices Lib DCO Characterization over PVTs ADEXL/MMSIM Models with corners Statistical variation MonteCarlo Analysis ADEXL/MMSIM Models with statistical info Exploring LLE, WPE and Assessing potential mismatch to post-layout simulation results ADEXL/MMSIM BSIM-CMG with LLE param WPE approximation added to BSIM-CMG core Set layout constraints and Hand over to back-end team CMS

22 GLOBALFOUNDRIES 22 Module 1 Circuit Design LLE & WPE parameters pre_layout_sw parametric analysis PVT corner simulation Statistical variation settings Reliability analysis settings Calibration test bench and settings Pre-saved ADE-XL states

23 Module 2 : Layout Block Authoring (Delay_cell) Objective Placement of unit cell creating correct by construction layout. Design Task Gen From Source Tool VLS-XL PDK Features XL-complaint Pcells Manual Placement VLS-XL Snap pattern definition in the OA techfile Fluid Guardring VLS-XL Fluid guardring definition in the OA techfile Online DRC ipvs PVS DRC runset GLOBALFOUNDRIES 23

24 Module 2: Layout Block Authoring Unit cell placement Brief explanation of important FinFet pcell features, CDFs and settings Generate from source to create connectivity based layout Template cell aids easy placement Snapping and how FinFets are snapped automatically Connectivity less abutment with dummy poly Fluid guard ring to create p and n taps ipvs with presets to run DRC on the fly GLOBALFOUNDRIES 24

25 Module 2 Layout Block Authoring (1) Place template (2) Place instances (3) Complete routing GLOBALFOUNDRIES 25

26 Module 3: Block Placement Validation Objective Investigate influence of placed FinFet devices RC Parasitics impact Design Tasks Device Placement Tool VLS-XL PDK Features XL-compliant Pcells RC Extraction PVS/QRC PVS runset, QRC Setup Device Parasitics Pre-routing Simulation ADE-XL/MMSIM Models Placement sign-off for routing GLOBALFOUNDRIES 26

27 GLOBALFOUNDRIES 27 Module 3: Block Placement Validation The device parasitic have greater influence Placement validation before doing the routing Add LVS Labels util to create labels on pcell inst terms LVS with virtual connectivity and save the SVDB RCX with extview.il proc to create extracted view ADE-XL simulation and analyze the placement Variable delaycell_diff_view run the corner simulation

28 Module 4 : Block Layout Routing Objective Routing of the design with the features of VLS-XL. Design Task Pin to Trunk Routing Net-constrained Routing Manual wire editing Auto routing Tool/ Feature Wire Editor Wire Editor Wire Editor Space-based Router PDK Features Routing default constraint in the OA techfile Routing default constraint in the OA techfile Routing default constraint in the OA techfile Routing default constraint in the OA techfile Constraint Validation Checker PVS CV GLOBALFOUNDRIES 28

29 Module 4: Block Layout Routing DPT routing same color spacing, color conflicts, odd loop Local interconnect routing Pin-to-Trunk routing methodology ipvs to analyze and fix DPT violations PVS CV for constraint validation GLOBALFOUNDRIES 29

30 Module 5: Block Sign-off Objective Physical verification, abstract generation, RC-extraction, post-layout simulation & streamout. Design Task OA based DRC/LVS Tool/ Feature PVS PDK Features PVS ruledecks for OpenAccess RC Extraction Quantus QRC Compiled QRC techfile Post-Layout Simulation ADEGXL/MMSIM Models Abstract Generation Abstract Generator Abstract options file Stream Out XStream Layer map table GDS based DRC/LVS PVS PVS ruledecks for GDS GLOBALFOUNDRIES 30

31 Module 5: Block Sign-off DRC recommended DRC switches LVS - recommended LVS switches One extracted view for 5 different corners processcorner ADE-XL for different corners based on design variable Analysis of different simulation results for different corners Step by step instructions to create colored abstract views Verify the abstract view GLOBALFOUNDRIES 31

32 Module 6 : Design Layout Assembly Objective Assembly of all the unit cells, routing and DPT sign-off. Design Task Gen From Source Tool/ Feature VLS-XL PDK Features Placement Refinement VLS-XL Snap pattern definition in the OA techfile Routing VSR / Wire Editor Routing default constraint in the OA techfile DPT Sign-off ViPVS PVS DRC runset DRC LVS PVS PVS Rule Deck GLOBALFOUNDRIES 32

33 Module 6: Design Layout Assembly CPH settings to use abstracts with Gen From Source Use template cell and place the unit cell and assemble Pin-To-Trunk & interactive routing - overriding defaults Re-master instances from abstract to layout DPT with Ref Flow util Annotate Sign-off DPT DPT sign-off with ipvs and PVS rules DRC / LVS with PVS GLOBALFOUNDRIES 33

34 GLOBALFOUNDRIES 34 Module 7: Design Sign-Off Objective: Full design implementation physical verification, streaming out to GDS & abstract creation. Design Task OA based DRC/LVS Tool/ Feature PVS PDK Features PVS ruledecks for OpenAccess RC Extraction Post-layout SIM Quantus QRC MMSIM Compiled QRC techfile Models (BSIM-CMG) Stream Out XStream Layer map table GDS based DRC/LVS PVS PVS ruledecks for GDS Abstract Generation Abstract Generator Abstract options file

35 Module : PhyVerif Objective DPT generation, merging and sign-off on fully colored GDS. Design Task GDSII / CDL creation predp DRC Demonstration of DRC LVS. Scripts for Netlist and Colored GDS Scripted runs for DPT DRC LVS recommended switches DP Generation & DRC DP Merge Fully colored DRC LVS GLOBALFOUNDRIES 35

36 Module : PEX Objective PEX and post layout simulation Design Tasks LVS & Query RC Extraction Input/Output environment variables for GF_top.tvf LAYOUT_PATH LAYOUT_PRIMARY LAYOUT_SYSTEM SOURCE_PATH SOURCE_PRIMARY SOURCE_SYSTEM LVS_REPORT LVS settings CHECK_MOSFET_PLORIENT CHECK_MOSFET_NGCON CHECK_MOSFET_CPP TRACE_RESISTANCE CHECK_RESISTOR_ORIENTATION CHECK_RESISTOR_R_CUT CHECK_ESD_AREA CHECK_MIM_AREA_PERIM SHORT_EQUIVALENT_NODES COMPARE_CASE PORT_DEPTH TEXT_DEPTH LVS_REPORT_MAX LVS_FILTER_SHORT_TO_CHECK_LE AKAGE_THRU_FLTGATE LVS_PUSH_DEVICE_SEPARATE_PR OPERTIES LVS_PUSH_DEVICES NETLIST_PRE_LAYOUT_LOCAL PEX_RUN ERC_RUN Layout path Layout cell name GDSII or OASIS Source path Source cell name SPICE LVS report file name TRUE or FALSE TRUE or FALSE TRUE or FALSE TRUE or FALSE TRUE or FALSE TRUE or FALSE TRUE or FALSE TRUE or FALSE TRUE FALSE PRIMARY PRIMARY ALL FALSE TRUE TRUE TRUE pre_layout_local instance parameter is back annotated for base FET devices during LVS step. TRUE Additional parameters are extracted for parasitic extraction FALSE Post Layout Simulation Set to FALSE when PEX_RUN=TRUE NWPROXIMITY TRUE RETARGET TRUE STRESS TRUE EXTRACT_FILL_LAYERS TRUE EXTRACT_XPOS_YPOS TRUE DONT_EXTRACT_FLT_GATE FALSE DONT_EXTRACT_TIED_GATE FALSE DONT_EXTRACT_PARASITIC_DIOD FALSE ES DONT_EXTRACT_PARASITIC_CAP FALSE XACT_FLOW FALSE Demonstrates parasitic extraction flow is described. Generating DSPF and OA View are the target formats. All command files are provided Required Environment variables are listed GLOBALFOUNDRIES 36

37 14LPP Reference Flow Modules Pre-Layout Functional Verification Accelerated Custom Layout Voltus-FI MSOA Interoperability ADE-XL/MMSIM Schematic-XL/Layout-XL Voltus-FI* Virtuoso/EDI* Physical Verification PVS Parasitic Extraction Post-Layout Functional Verification Quantus QRC ADE-XL/MMSIM * Planned for V2 GLOBALFOUNDRIES 37

38 GLOBALFOUNDRIES Reference Flows How to get them? GLOBALFOUNDRIES 38

39 1 Design Challenges at Advanced Nodes 2 GF Reference Flows 3 Ref Flow Design 4 Ref Flow Modules 5 Summary GLOBALFOUNDRIES 39

40 Summary 14LPP Modules are well documented with step by step instructions FinFET features are highlighted nicely Use of template cell for easy placement Provided utils will improve the AMS design methodology Phase II will have MSOA, EM/IR modules GLOBALFOUNDRIES 40

41 Acknowledgements GLOBALFOUNDRIES : Richard Trihy, Venkat Ramasubramanian, Hendrik Mau, Rais Huda, Sascha Hoefer, Winnie Ng, Tim Miller CADENCE : Louis Thiam, John Pierce, Aryoko Prakoso, Tran Hoang GLOBALFOUNDRIES Confidential 41

42 Thank you Disclaimer The information contained herein [is confidential and] is the property of GLOBALFOUNDRIES and/or its licensors. This document is for informational purposes only, is current only as of the date of publication and is subject to change by GLOBALFOUNDRIES at any time without notice. GLOBALFOUNDRIES, the GLOBALFOUNDRIES logo and combinations thereof are trademarks of GLOBALFOUNDRIES Inc. in the United States and/or other jurisdictions. Other product or service names are for identification purposes only and may be trademarks or service marks of their respective owners. GLOBALFOUNDRIES Inc Unless otherwise indicated, all rights reserved. Do not copy or redistribute except as expressly permitted by GLOBALFOUNDRIES.