Digital Logic Design. Final Examination

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1 The University of Toleo Section s5fs_il7.fm - EECS: igital Logic esign r. nthony. Johnson Stuent name igital Logic esign Final Examination Problems Points... Total 5 Was the exam fair? yes no

2 The University of Toleo Section s5fs_il7.fm - EECS: igital Logic esign r. nthony. Johnson Stuent name Problem points Given is a logic (switching) function F in the ecimal list sum-of-minterms representation (-). F (,B,C,) = Σ(, 4, 5, 6, 7,, 4, 5), (,B,C,) = Σ( 9,, ) (-) Problem statement On the example of the given logic function F emonstrate an ability to: Hint #. erive a Karnaugh map representation of the function F,. use the Karnaugh map metho to erive the minimal number of literals SOP an POS expressions of F,. esign the two-level NN-NN implementation of the SOP form of function F, an the two-level NOR-NOR implementation of the POS form of function F, as specifie uner.4 an.5 below. For full creit: all equations, all answers to questions, all circuit moels an other graphical representations are expecte to be entere into the space esignate for them; all shown numerical results must be precee by the symbolic an numeric expressions whose evaluation prouces these numerical results. Problem Solution n explicit emonstration of unerstaning the following solution steps is expecte.. Prepare the Karnaugh map representation of the function F, an place a copy of it into each of the spaces reserve for Figures - an -(c). B C B C (c) F = B + C + C F = ( + C) ( + B + C) (B + ) Figure - Representation forms of the function F. Karnaugh map. Minimum number of literals SOP representation of F. (c)karnaugh map. ())Minimum number of literals POS representation of F. ()

3 The University of Toleo Section s5fs_il7.fm - EECS: igital Logic esign r. nthony. Johnson Stuent name. pply the Karnaugh map minimization metho to erive the Minimum number of literals sum-of-proucts (SOP) representation of the function F. Show the erive algebraic representation in the space reserve for Figure -.. pply the Karnaugh map minimization metho to erive the Minimum number of literals prouct-of-sums (POS) representation of the function F. Show the erive algebraic representation in the space reserve for Figure -()..4 In the space reserve for Figure -, prepare a logic circuit iagram of the two-level NN-NN form of implementation of the erive minimum number of literals SOP expression of the function F.5 In the space reserve for Figure -, prepare a logic circuit iagram of the two-level NOR-NOR form of implementation of the erive minimum number of literals POS expression of the function F. F = B + C + C F = ( + C) ( + B + C) (B + ) B C F C B F C C B Figure - Two-level implementation of the minimum number of literals expressions of the functions F an F. NN-NN implementation of F. NOR-NOR implementation of F.

4 The University of Toleo Section s5fs_il7.fm - 4 EECS: igital Logic esign r. nthony. Johnson Stuent name Problem points Given is the partial escription of a 4-bit universal (biirectional) shift-register, as shown in parts an of Figure.: a partial (incomplete) rawing of a logic circuit moel of the universal shift-register, a specific Function Table for the given universal shift-register. O O O O CLK CLR RES RES RES RES S s MUX 4: s MUX 4: s MUX 4: s MUX 4: S s s s s I SR I SL I I I I Operation coe S S Register operation shift left no change parallel loa shift right Signal esignation O O Signal escription Serial output for shift left operation Serial output for shift right operation (c) Figure. MUX-base implementation of a Universal shift register. Partial logic circuit moel of a universal shift register. Function table of the shift register, showing the operation coes to be implemente by the esign. (c)space for writing in the answer to part.. Problem Statement Base on the given partial escription emonstrate an ability to:. complete the missing connections to the signal inputs of the multiplexers in the given logic circuit moel of the universal shift-register in such a way that the complete circuit implements the functions specifie in the Function Table of Figure.;. recognize an label the serial output terminals for shift-left an shift-right operations.

5 The University of Toleo Section s5fs_il7.fm - 5 EECS: igital Logic esign r. nthony. Johnson Stuent name Hint # For full creit: all equations, all answers to questions, all circuit moels an other graphical representations are expecte to be entere into the space esignate for them; all shown numerical results must be precee by the symbolic an numeric expressions whose evaluation prouces these numerical results. Problem Solution n explicit emonstration of unerstaning the following solution steps is expecte. 8. Using the following labels/esignations for input signals of the shift register: I SR for the shift right operation:, I SL for the shift left operation: I SL, I o I LSB for parallel loa operation, MSB for parallel loa operation, I, I, remaining bits for parallel loa operation, esign an enter in Figure. the necessary wire connections to make the complete circuit moel of Figure. implement the universal shift register specifie by the function table shown in Figure... In the space reserve for Figure.(c), write the signal esignations from Figure. which represent the serial outputs for the shift left an shift right operations.

6 The University of Toleo Section s5fs_il7.fm - 6 EECS: igital Logic esign r. nthony. Johnson Stuent name Problem points Given is the natural language escription of a State Machine (SM): SM chart of the SM is shown in Figure., SM has one input signal: whose logic value is sense at the active ege of the system clock, (c) SM has one output signal: Z which is set to TRUE at the active ege of the system clock, () positive-ege triggere -type flip-flop(s) are to be use as the SM s internal state memory elements. Z= Inputs Clock i / Next state logic Output Internal k s o / state signal / logic / memory Outputs Z= Z= Z= Figure. Mealy-type State Machine. The general Mealy type SM architecture. SM chart of a specific SM for which the esign process is to be emonstrate. Problem Statement On the example of given SM chart escription of a state machine emonstrate an ability to:. compose the State Transition Table that is implie by the given SM chart;. combine the information from the State Transition Table an the -type Flip-Fop Excitation Table to prepare the State Transition Excitation Table of the specifie SM;. apply the Karnaugh Map simplification metho to erive the minimum number of literals internal-state flip-flop excitation functions; 4. compose the next state combinational circuit moel which implements the erive internalstate flip-flop transition excitation function(s). Hint # For full creit: all equations, all answers to questions, all circuit moels an other graphical representations are expecte to be entere into the space esignate for them; all shown numerical results must be precee by the symbolic an numeric expressions whose evaluation prouces these numerical results.

7 The University of Toleo Section s5fs_il7.fm - 7 EECS: igital Logic esign r. nthony. Johnson Stuent name Problem Solution For full creit, an explicit emonstration of unerstaning the following solution steps is expecte.. Compose the state transition table of the SM using the information from the SM chart of Figure.. Show the compose table in the space reserve for Figure. Z= Z=? Z= Z= Sequence Receive? y y / / / / / / Y Y /Z / / + y y Y Z (c) Y y y y y y y = Sy = S Z = y y () - Kmap - Kmap Z- Kmap (e) Figure. State Machine esign process. State transition table of the SM. -type flip-flop excitation table. (c)state transition excitation table of the SM. ()Karnaugh map of the functions,, an X. (e)minimum number of literals expression of the logic functions,, an Z.. In the space reserve for Figure. fill in the contents of the -type flip-flop excitation table.. Combining the information from the state transition table an the flip-flop excitation table compose the state transition excitation table of the SM. Show the compose table in the space reserve for Figure.(c).4 In the space reserve for Figure.() prepare the Karnaugh map representation of the flip-flop excitation function(s) foun in the state transition excitation table..5 Using the prepare Karnaugh map, erive the minimum number of literals expression of the flipflop excitation function(s), an enter the erive expression(s) in the space reserve for Figure.(e).

8 The University of Toleo Section s5fs_il7.fm - 8 EECS: igital Logic esign r. nthony. Johnson Stuent name.6 Using the minimum number of literals logic functions whose expressions are shown in Figure.(e), prepare the logic circuit moel that implements the State Machine escribe by the SM chart of Figure.. S y Sy Y FF y S Z=Sy y CLK S Y FF y y Figure. Logic circuit moel of the State Machine whose SM chart is shown in Figure..

Digital Logic Design. Final Examination

Digital Logic Design. Final Examination The University of Toleo s8fs_il7.fm - EEC: igital Logic esign r. Anthony. Johnson tuent name igital Logic esign Final Examination Problems Points... 4 Total 6 Was the exam fair? yes no The University of