ECE 361 Computer Architecture Lecture 10: Designing a Multiple Cycle Processor
|
|
- Beverley Lamb
- 5 years ago
- Views:
Transcription
1 ECE 6 Computer Architecture Lecture : Designing a Multiple Cycle Processor 6 multipath.. Recap: A Single Cycle Datapath We have everything except control signals (underline) RegDst Today s lecture will show you how to generate the control signals busw RegWr imm6 Rb -bit Registers 6 busb Extender n_sel busa Src Instruction Fetch Unit ctr Data In Instruction<:> <:> <6:> MemWr WrEn Adr Data <:> <:> Imm6 MemtoReg 6 multipath.. ExtOp
2 Recap: PLA Implementation of the Main op<>.. op<>.. op<>.. op<>.. op<>.. op<>.. <> <> <> <> <> op<> R-type ori lw sw beq jump RegWrite Src RegDst MemtoReg MemWrite Branch Jump ExtOp op<> op<> op<> 6 multipath.. The Big Picture: Where are We Now? The Five Classic Components of a Computer Processor Input Datapath Output Today s Topic: Designing the Datapath for the Multiple Clock Cycle Datapath 6 multipath..
3 Outline of Today s Lecture Recap and Introduction Introduction to the Concept of Multiple Cycle Processor Multiple Cycle Implementation of R-type Instructions What is a Multiple Cycle Delay Path and Why is it Bad? Multiple Cycle Implementation of Or Immediate Multiple Cycle Implementation of Load and Store Putting it all Together 6 multipath.. Abstract View of our single cycle processor op fun Main control Next n_sel Equal Src ExtOp ctr Mem MemWr RegDst RegWr MemWr Instruction Fetch Register Fetch Ext Mem Access Reg. Wrt Data Mem Result Store 6 multipath..6 looks like a FSM with as state
4 What s wrong with our CPI= processor? Arithmetic & Logical Inst Reg File mux mux setup Load Inst Reg File mux Data Mem muxsetup Critical Path Store Inst Reg File mux Data Mem Branch Inst Reg File cmp mux Long Cycle Time All instructions take as much time as the slowest Real memory is not so nice as our idealized memory cannot always get the job done in one (short) cycle 6 multipath..7 Drawbacks of this Single Cycle Processor Long cycle time: Cycle time must be long enough for the load instruction: - s Clock -to-q + - Instruction Access Time + - Register File Access Time + - Delay (address calculation) + - Data Access Time + - Register File Setup Time + - Clock Skew Cycle time is much longer than needed for all other instructions. Examples: R-type instructions do not require data memory access Jump does not require operation nor data memory access 6 multipath..8
5 Overview of a Multiple Cycle Implementation The root of the single cycle processor s problems: The cycle time has to be long enough for the slowest instruction Solution: Break the instruction into smaller steps Execute each step (instead of the entire instruction) in one cycle - Cycle time: time it takes to execute the longest step - Keep all the steps to have similar length This is the essence of the multiple cycle processor The advantages of the multiple cycle processor: Cycle time is much shorter Different instructions take different number of cycles to complete - Load takes five cycles - Jump only takes three cycles Allows a functional unit to be used more than once per instruction 6 multipath..9,,, Op, Func ctr The Five Steps of a Load Instruction Old Value Instruction Fetch Instr Decode / -to-q New Value Old Value Old Value Reg. Fetch Address Instruction Access Time New Value Delay through Logic New Value Data Reg Wr ExtOp Old Value New Value Src Old Value New Value RegWr Old Value New Value Register File Access Time busa Old Value New Value Delay through Extender & busb Old Value New Value Delay Address Old Value New Value Data Access Time busw Old Value New 6 multipath.. Register File Write Time
6 Register File & Write Timing: vs. Reality In previous lectures, register file and memory are simplified: Write happens at the clock tick Address, data, and write enable must be stable one set-up time before the clock tick WrEn Adr In real life: Neither register file nor ideal memory has the clock input The write path is a combinational logic delay path: - Write enable goes to and Din settles down - write access delay - Din is written into mem[address] Important: Address and Data must be stable BEFORE Write Enable goes to WrEn Adr 6 multipath.. ce Condition Between Address and Write Enable This real (no clock input) register file may not work reliably in the single cycle processor because: We cannot guarantee will be stable BEFORE RegWr = There is a race between (address) and RegWr (write enable) RegWr Rb busa Reg File busb busw The real (no clock input) memory may not work reliably in the single cycle processor because: We cannot guarantee Address will be stable BEFORE WrEn = There is a race between Adr and WrEn WrEn Adr 6 multipath.. 6
7 How to Avoid this ce Condition? Solution for the multiple cycle implementation: Make sure Address is stable by the end of Cycle N Assert Write Enable signal ONE cycle later at Cycle (N + ) Address cannot change until Write Enable is disasserted 6 multipath.. Dual-Port Dual Port Independent Read (, Dout) and Write (WAdr, Din) ports Read and write (to different location) can occur at the same cycle Read Port is a combinational path: Read Address Valid --> Read Access Delay --> Data Out Valid Write Port is also a combinational path: MemWrite = --> Write Access Delay --> Data In is written into location[] MemWr <:> <:> 6 multipath.. 7
8 Questions and Administrative Matters 6 multipath.. Instruction Fetch Cycle: In the Beginning Every cycle begins right AFTER the clock tick: mem[] <:> + You are here! One Logic Clock Cycle Wr=? MemWr=? Dout Din IRWr=? op=? 6 multipath..6 8
9 Instruction Fetch Cycle: The End Every cycle ends AT the next clock tick (storage element updates): IR <-- mem[] <:> <-- <:> + One Logic Clock Cycle Wr= You are here! MemWr= Din Dout IRWr= Op = Add 6 multipath..7 Wr= Instruction Fetch Cycle: Overall Picture Ifetch Op=Add : Wr, IRWr x: WrCond RegDst, MemR Others: s WrCond=x Src= BrWr= IorD= MemWr= IRWr= SelA= Target busa busb SelB= Op=Add 6 multipath..8 9
10 Register Fetch / Instruction Decode busa <- RegFile[rs] ; busb <- RegFile[rt] ; is not being used: ctr = xx Wr= IorD=x 6 multipath..9 WrCond= MemWr= Go to the Op Func IRWr= RegDst=x 6 6 Imm 6 RegWr= Rb busa Reg File busw busb SelA=x Src=x SelB=xx Op=xx Register Fetch / Instruction Decode (Continue) busa <- Reg[rs] ; busb <- Reg[rt] ; Target <- + SignExt(Imm6)* Wr= Beq ype Ori IorD=x 6 multipath.. WrCond= MemWr= : IRWr= Op 6 Func 6 RegDst=x Imm 6 ExtOp= Extend Rfetch/Decode Op=Add : BrWr, ExtOp SelB= x: RegDst, Src IorD, MemtoReg Others: s RegWr= Rb busa Reg File busw busb << Src=x SelA= SelB= BrWr= Target Op=Add
11 Branch Completion if (busa == busb) Wr= 6 multipath.. <- Target IorD=x WrCond= MemWr= IRWr= RegDst=x Imm 6 ExtOp=x BrComplete Op=Sub SelB= x: IorD, MemReg RegDst, ExtOp : WrCond SelA Src Extend RegWr= Rb busa Reg File busw busb << Src= SelA= SelB= BrWr= Target Op=Sub Instruction Decode: We have a R-type! Next Cycle: R-type Execution Wr= Beq ype Ori IorD=x 6 multipath.. WrCond= MemWr= : IRWr= Op 6 Func 6 RegDst=x Imm 6 ExtOp= Extend RegWr= Rb busa Reg File busw busb << Src=x SelA= SelB= BrWr= Target Op=Add
12 R-type Execution Output <- busa op busb RExec : RegDst SelA SelB= Op=ype x: Src, IorD Wr= WrCond= MemtoReg ExtOp Src=x BrWr= IorD=x MemWr= IRWr= RegDst= RegWr= SelA= Target Rb busa Reg File busw busb << Imm Extend 6 ExtOp=x MemtoReg=x Op=ype SelB= 6 multipath.. R-type Completion Rfinish Op=ype R[rd] <- Output : RegDst, RegWr sela SelB= Wr= WrCond= x: IorD, Src ExtOp Src=x BrWr= IorD=x MemWr= IRWr= RegDst= RegWr= SelA= Target Rb busa Reg File busw busb << Imm Extend 6 ExtOp=x MemtoReg= Op=ype SelB= 6 multipath..
13 A Multiple Cycle Delay Path There is no register to save the results between: Register Fetch: busa <- Reg[rs] ; busb <- Reg[rt] R-type Execution: output <- busa op busb R-type Completion: Reg[rd] <- output Register here to save outputs of Rfetch? sela Wr busa Rb Reg File busw busb selb Op Register here to save outputs of RExec? 6 multipath.. A Multiple Cycle Delay Path (Continue) Register is NOT needed to save the outputs of Register Fetch: IRWr = : busa and busb will not change after Register Fetch Register is NOT needed to save the outputs of R-type Execution: busa and busb will not change after Register Fetch signals SelA, SelB, and Op will not change after R-type Execution Consequently output will not change after R-type Execution In theory (P. 6, P&H), you need a register to hold a signal value if: () The signal is computed in one clock cycle and used in another. () AND the inputs to the functional block that computes this signal can change before the signal is written into a state element. You can save a register if Cond is true BUT Cond is false: But in practice, this will introduce a multiple cycle delay path: - A logic delay path that takes multiple cycles to propagate from one storage element to the next storage element 6 multipath..6
14 Pros and Cons of a Multiple Cycle Delay Path A -cycle path example: IR (storage) -> Reg File Read -> -> Reg File Write (storage) Advantages: Register savings We can share time among cycles: - If takes longer than one cycle, still a OK as long as the entire path takes less than cycles to finish busa Rb Reg File busw busb selb 6 multipath..7 Pros and Cons of a Multiple Cycle Delay Path (Continue) Disadvantage: Static timing analyzer, which ONLY looks at delay between two storage elements, will report this as a timing violation You have to ignore the static timing analyzer s warnings busa Rb Reg File busw busb selb 6 multipath..8
15 Instruction Decode: We have an Ori! Next Cycle: Ori Execution Wr= IorD=x Beq ype Ori 6 multipath..9 WrCond= MemWr= : IRWr= Intruction Reg Op 6 Func 6 RegDst=x Imm 6 ExtOp= Extend RegWr= Rb busa Reg File busw busb << Src=x SelA= SelB= BrWr= Target Op=Add Ori Execution output <- busa or Ext[Imm6] Op=Or OriExec : SelA SelB= x: MemtoReg IorD, Src Wr= WrCond= Src=x BrWr= IorD=x MemWr= IRWr= RegDst= RegWr= SelA= Target Rb busa Reg File busw busb << 6 multipath.. Imm Extend 6 ExtOp= MemtoReg=x Op=Or SelB=
16 Ori Completion OriFinish Op=Or Reg[rt] <- output x: IorD, Src SelB= : SelA Wr= WrCond= RegWr Src=x BrWr= IorD=x MemWr= IRWr= RegDst= RegWr= SelA= Target Rb busa Reg File busw busb << 6 multipath.. Imm Extend 6 ExtOp= MemtoReg= Op=Or SelB= Address Calculation AdrCal : ExtOp SelA SelB= output <- busa + SignExt[Imm6] Op=Add x: MemtoReg Src Wr= WrCond= Src=x BrWr= IorD=x MemWr= IRWr= RegDst=x RegWr= SelA= Target Rb busa Reg File busw busb << 6 multipath.. Imm Extend 6 ExtOp= MemtoReg=x Op=Add SelB= 6
17 Access for Store : ExtOp MemWr SWmem SelA mem[ output] <- busb SelB= Op=Add Wr= WrCond= x: Src,RegDst MemtoReg Src=x BrWr= IorD=x MemWr= IRWr= RegDst=x RegWr= SelA= Target Rb busa Reg File busw busb << Imm Extend 6 ExtOp= MemtoReg=x Op=Add SelB= 6 multipath.. Access for Load : ExtOp LWmem SelA, IorD SelB= Mem Dout <- mem[ output] Op=Add x: MemtoReg Src Wr= WrCond= Src=x BrWr= IorD= MemWr= IRWr= RegDst= RegWr= SelA= Target Rb busa Reg File busw busb << 6 multipath.. Imm Extend 6 ExtOp= MemtoReg=x Op=Add SelB= 7
18 Write Back for Load LWwr : SelA RegWr, ExtOp Reg[rt] <- Mem Dout MemtoReg SelB= Op=Add Wr= WrCond= x: Src IorD Src=x BrWr= IorD=x MemWr= IRWr= RegDst= RegWr= SelA= Target Rb busa Reg File busw busb << Imm Extend 6 ExtOp= MemtoReg= Op=Add SelB= 6 multipath.. Putting it all together: Multiple Cycle Datapath Wr WrCond Src BrWr IorD MemWr IRWr RegDst RegWr SelA Target Rb busa Reg File busw busb << Imm Extend 6 ExtOp MemtoReg SelB Op 6 multipath..6 8
19 Putting it all together: State Diagram Ifetch Op=Add : Wr, IRWr x: WrCond AdrCal RegDst, MemR : ExtOp SelA Others: s SelB= Op=Add lw or sw x: MemtoReg Src lw sw : ExtOp LWmem SelA, IorD SelB= Op=Add x: MemtoReg Src : SelA LWwr RegWr, ExtOp MemtoReg SelB= Op=Add x: Src IorD SWMem : ExtOp MemWr SelA SelB= Op=Add x: Src,RegDst MemtoReg Rfetch/Decode Op=Add : BrWr, ExtOp SelB= x: RegDst, Src IorD, MemtoReg Others: s ype Ori RExec : RegDst SelA SelB= Op=ype x: Src, IorD MemtoReg ExtOp beq Rfinish Op=ype : RegDst, RegWr sela SelB= x: IorD, Src ExtOp BrComplete Op=Sub SelB= x: IorD, MemReg RegDst, ExtOp : WrCond SelA Src OriExec Op=Or : SelA SelB= x: MemtoReg IorD, Src Op=Or OriFinish x: IorD, Src SelB= : SelA RegWr 6 multipath..7 Summary Disadvantages of the Single Cycle Processor 6 multipath..8 Long cycle time Cycle time is too long for all instructions except the Load Multiple Cycle Processor: Divide the instructions into smaller steps Execute each step (instead of the entire instruction) in one cycle Do NOT confuse Multiple Cycle Processor with Multiple Cycle Delay Path Multiple Cycle Processor executes each instruction in multiple clock cycles Multiple Cycle Delay Path: a combinational logic path between two storage elements that takes more than one clock cycle to complete It is possible (desirable) to build a MC Processor without MCDP: Use a register to save a signal s value whenever a signal is generated in one clock cycle and used in another cycle later 9
ECE468. Computer Organization and Architecture. Designing a Multiple Cycle Processor
ECE68 Computer Organization and Architecture Designing a Multiple Cycle Processor ECE68 multipath.. op 6 Instr RegDst A Single Cycle Processor busw RegWr Main imm6 Instr Rb -bit Registers 6 op RegDst
More information361 multipath..1. EECS 361 Computer Architecture Lecture 10: Designing a Multiple Cycle Processor
36 multipath.. EECS 36 Computer Architecture Lecture : Designing a Multiple Cycle Processor Recap: A Single Cycle Datapath We have everything except control signals (underline) Today s lecture will show
More informationECE4680. Computer Organization and Architecture. Designing a Multiple Cycle Processor
ECE68 Computer Organization and Architecture Designing a Multiple Cycle Processor ECE68 Multipath. -- op 6 Instr RegDst A Single Cycle Processor busw RegWr Main imm6 Instr Rb -bit Registers 6 op
More informationECE4680. Computer Organization and Architecture. Designing a Multiple Cycle Processor
ECE468 Computer Organization and Architecture Designing a Multiple Cycle Processor ECE468 Multipath. -- Start X:4 op 6 Instr RegDst A Single Cycle Processor busw RegWr Clk Main imm6 Instr Rb -bit
More informationECE 361 Computer Architecture Lecture 11: Designing a Multiple Cycle Controller. Review of a Multiple Cycle Implementation
ECE 6 Computer Architecture Lecture : Designing a Multiple Cycle ler 6 multicontroller. Review of a Multiple Cycle Implementation The root of the single cycle processor s problems: The cycle time has to
More informationOutline of today s lecture. EEL-4713 Computer Architecture Designing a Multiple-Cycle Processor. What s wrong with our CPI=1 processor?
Outline of today s lecture EEL-7 Computer Architecture Designing a Multiple-Cycle Processor Recap and Introduction Introduction to the Concept of Multiple Cycle Processor Multiple Cycle Implementation
More informationECE468 Computer Organization and Architecture. Designing a Multiple Cycle Controller
ECE468 Computer Organization and Architecture Designing a Multiple Cycle Controller ECE468 multicontroller Review of a Multiple Cycle Implementation The root of the single cycle processor s problems: The
More informationCpE 442. Designing a Multiple Cycle Controller
CpE 442 Designing a Multiple Cycle Controller CPE 442 multicontroller.. Outline of Today s Lecture Recap (5 minutes) Review of FSM control (5 minutes) From Finite State Diagrams to Microprogramming (25
More informationCOMP303 Computer Architecture Lecture 9. Single Cycle Control
COMP33 Computer Architecture Lecture 9 Single Cycle Control A Single Cycle Datapath We have everything except control signals (underlined) RegDst busw Today s lecture will look at how to generate the control
More informationECE468 Computer Organization and Architecture. Designing a Single Cycle Datapath
ECE468 Computer Organization and Architecture Designing a Single Cycle Datapath ECE468 datapath1 The Big Picture: Where are We Now? The Five Classic Components of a Computer Processor Control Input Datapath
More informationCS152 Computer Architecture and Engineering Lecture 13: Microprogramming and Exceptions. Review of a Multiple Cycle Implementation
CS152 Computer Architecture and Engineering Lecture 13: Microprogramming and Exceptions March 3, 1995 Dave Patterson (patterson@cs) and Shing Kong (shing.kong@eng.sun.com) Slides available on http://http.cs.berkeley.edu/~patterson
More information361 datapath.1. Computer Architecture EECS 361 Lecture 8: Designing a Single Cycle Datapath
361 datapath.1 Computer Architecture EECS 361 Lecture 8: Designing a Single Cycle Datapath Outline of Today s Lecture Introduction Where are we with respect to the BIG picture? Questions and Administrative
More informationThe Big Picture: Where are We Now? EEM 486: Computer Architecture. Lecture 3. Designing a Single Cycle Datapath
The Big Picture: Where are We Now? EEM 486: Computer Architecture Lecture 3 The Five Classic Components of a Computer Processor Input Control Memory Designing a Single Cycle path path Output Today s Topic:
More informationCpE242 Computer Architecture and Engineering Designing a Single Cycle Datapath
CpE242 Computer Architecture and Engineering Designing a Single Cycle Datapath CPE 442 single-cycle datapath.1 Outline of Today s Lecture Recap and Introduction Where are we with respect to the BIG picture?
More informationCPU Design Steps. EECC550 - Shaaban
CPU Design Steps 1. Analyze instruction set operations using independent RTN => datapath requirements. 2. Select set of datapath components & establish clock methodology. 3. Assemble datapath meeting the
More informationOutline. EEL-4713 Computer Architecture Designing a Single Cycle Datapath
Outline EEL-473 Computer Architecture Designing a Single Cycle path Introduction The steps of designing a processor path and timing for register-register operations path for logical operations with immediates
More information361 control.1. EECS 361 Computer Architecture Lecture 9: Designing Single Cycle Control
36 control. EECS 36 Computer Architecture Lecture 9: Designing Single Cycle Control Recap: The MIPS Subset ADD and subtract add rd, rs, rt sub rd, rs, rt OR Imm: ori rt, rs, imm6 3 3 26 2 6 op rs rt rd
More informationRecap: A Single Cycle Datapath. CS 152 Computer Architecture and Engineering Lecture 8. Single-Cycle (Con t) Designing a Multicycle Processor
CS 52 Computer Architecture and Engineering Lecture 8 Single-Cycle (Con t) Designing a Multicycle Processor February 23, 24 John Kubiatowicz (www.cs.berkeley.edu/~kubitron) lecture slides: http://inst.eecs.berkeley.edu/~cs52/
More informationDesigning a Multicycle Processor
Designing a Multicycle Processor Arquitectura de Computadoras Arturo Díaz D PérezP Centro de Investigación n y de Estudios Avanzados del IPN adiaz@cinvestav.mx Arquitectura de Computadoras Multicycle-
More informationCOMP303 - Computer Architecture Lecture 8. Designing a Single Cycle Datapath
COMP33 - Computer Architecture Lecture 8 Designing a Single Cycle Datapath The Big Picture The Five Classic Components of a Computer Processor Input Control Memory Datapath Output The Big Picture: The
More informationMajor CPU Design Steps
Datapath Major CPU Design Steps. Analyze instruction set operations using independent RTN ISA => RTN => datapath requirements. This provides the the required datapath components and how they are connected
More informationEEM 486: Computer Architecture. Lecture 3. Designing Single Cycle Control
EEM 48: Computer Architecture Lecture 3 Designing Single Cycle The Big Picture: Where are We Now? Processor Input path Output Lec 3.2 An Abstract View of the Implementation Ideal Address Net Address PC
More informationECE4680 Computer Organization and Architecture. Designing a Pipeline Processor
ECE468 Computer Organization and Architecture Designing a Pipeline Processor Pipelined processors overlap instructions in time on common execution resources. ECE468 Pipeline. 22-4-3 Start X:4 Branch Jump
More informationHow to design a controller to produce signals to control the datapath
ECE48 Computer Organization and Architecture Designing Single Cycle How to design a controller to produce signals to control the datapath ECE48. 2--7 Recap: The MIPS Formats All MIPS instructions are bits
More informationCS3350B Computer Architecture Winter Lecture 5.7: Single-Cycle CPU: Datapath Control (Part 2)
CS335B Computer Architecture Winter 25 Lecture 5.7: Single-Cycle CPU: Datapath Control (Part 2) Marc Moreno Maza www.csd.uwo.ca/courses/cs335b [Adapted from lectures on Computer Organization and Design,
More informationLecture #17: CPU Design II Control
Lecture #7: CPU Design II Control 25-7-9 Anatomy: 5 components of any Computer Personal Computer Computer Processor Control ( brain ) This week ( ) path ( brawn ) (where programs, data live when running)
More informationUC Berkeley CS61C : Machine Structures
inst.eecs.berkeley.edu/~cs6c UC Berkeley CS6C : Machine Structures The Internet is broken?! The Clean Slate team at Stanford wants to revamp the Internet, making it safer (from viruses), more reliable
More informationHardwired Control Unit Ch 14
Hardwired Control Unit Ch 14 Micro-operations Controlling Execution Hardwired Control 1 What is Control (2) So far, we have shown what happens inside CPU execution of instructions opcodes, addressing modes,
More informationCS 152 Computer Architecture and Engineering. Lecture 10: Designing a Multicycle Processor
CS 152 Computer Architecture and Engineering Lecture 1: Designing a Multicycle Processor October 1, 1997 Dave Patterson (http.cs.berkeley.edu/~patterson) lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/
More informationUC Berkeley CS61C : Machine Structures
inst.eecs.berkeley.edu/~cs6c UC Berkeley CS6C : Machine Structures Lecture 26 Single-cycle CPU Control 27-3-2 Exhausted TA Ben Sussman www.icanhascheezburger.com Qutrits Bring Quantum Computers Closer:
More informationHardwired Control Unit Ch 16
Hardwired Control Unit Ch 16 Micro-operations Controlling Execution Hardwired Control 1 What is Control (2) So far, we have shown what happens inside CPU execution of instructions opcodes, addressing modes,
More informationCS152 Computer Architecture and Engineering Lecture 10: Designing a Single Cycle Control. Recap: The MIPS Instruction Formats
CS52 Computer Architecture and Engineering Lecture : Designing a Single Cycle February 7, 995 Dave Patterson (patterson@cs) and Shing Kong (shing.kong@eng.sun.com) Slides available on http://http.cs.berkeley.edu/~patterson
More informationCPU Organization (Design)
ISA Requirements CPU Organization (Design) Datapath Design: Capabilities & performance characteristics of principal Functional Units (FUs) needed by ISA instructions (e.g., Registers, ALU, Shifters, Logic
More informationECE170 Computer Architecture. Single Cycle Control. Review: 3b: Add & Subtract. Review: 3e: Store Operations. Review: 3d: Load Operations
ECE7 Computer Architecture Single Cycle Control Review: 3a: Overview of the Fetch Unit The common operations Fetch the : mem[] Update the program counter: Sequential Code: < + Branch and Jump: < something
More informationCS 110 Computer Architecture Single-Cycle CPU Datapath & Control
CS Computer Architecture Single-Cycle CPU Datapath & Control Instructor: Sören Schwertfeger http://shtech.org/courses/ca/ School of Information Science and Technology SIST ShanghaiTech University Slides
More informationMIPS-Lite Single-Cycle Control
MIPS-Lite Single-Cycle Control COE68: Computer Organization and Architecture Dr. Gul N. Khan http://www.ee.ryerson.ca/~gnkhan Electrical and Computer Engineering Ryerson University Overview Single cycle
More informationCS 61C: Great Ideas in Computer Architecture (Machine Structures) Single- Cycle CPU Datapath & Control Part 2
CS 6C: Great Ideas in Computer Architecture (Machine Structures) Single- Cycle CPU Datapath & Control Part 2 Instructors: Krste Asanovic & Vladimir Stojanovic hfp://inst.eecs.berkeley.edu/~cs6c/ Review:
More informationFull Datapath. CSCI 402: Computer Architectures. The Processor (2) 3/21/19. Fengguang Song Department of Computer & Information Science IUPUI
CSCI 42: Computer Architectures The Processor (2) Fengguang Song Department of Computer & Information Science IUPUI Full Datapath Branch Target Instruction Fetch Immediate 4 Today s Contents We have looked
More informationLecture 6 Datapath and Controller
Lecture 6 Datapath and Controller Peng Liu liupeng@zju.edu.cn Windows Editor and Word Processing UltraEdit, EditPlus Gvim Linux or Mac IOS Emacs vi or vim Word Processing(Windows, Linux, and Mac IOS) LaTex
More informationCS359: Computer Architecture. The Processor (A) Yanyan Shen Department of Computer Science and Engineering
CS359: Computer Architecture The Processor (A) Yanyan Shen Department of Computer Science and Engineering Eecuting R-type Instructions 7 Instructions ADD and subtract add rd, rs, rt sub rd, rs, rt OR Immediate:
More informationRecap: The MIPS Subset ADD and subtract EEL Computer Architecture shamt funct add rd, rs, rt Single-Cycle Control Logic sub rd, rs, rt
Recap: The MIPS Subset EEL-47 - Computer Architecture Single-Cycle Logic ADD and subtract add rd, rs, rt sub rd, rs, rt OR Imm: ori rt, rs, imm 2 rs rt rd shamt t bits 5 bits 5 bits 5 bits 5 bits bits
More informationCS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #19 Designing a Single-Cycle CPU 27-7-26 Scott Beamer Instructor AI Focuses on Poker CS61C L19 CPU Design : Designing a Single-Cycle CPU
More informationCh 5: Designing a Single Cycle Datapath
Ch 5: esigning a Single Cycle path Computer Systems Architecture CS 365 The Big Picture: Where are We Now? The Five Classic Components of a Computer Processor Control Memory path Input Output Today s Topic:
More informationCSCI 402: Computer Architectures. Fengguang Song Department of Computer & Information Science IUPUI. Today s Content
3/6/8 CSCI 42: Computer Architectures The Processor (2) Fengguang Song Department of Computer & Information Science IUPUI Today s Content We have looked at how to design a Data Path. 4.4, 4.5 We will design
More informationinst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 19 CPU Design: The Single-Cycle II & Control !
inst.eecs.berkeley.edu/~cs6c CS6C : Machine Structures Lecture 9 CPU Design: The Single-Cycle II & Control 2-7-22!!!Instructor Paul Pearce! Dell may have shipped infected motherboards! Dell is warning
More informationMulti-cycle Approach. Single cycle CPU. Multi-cycle CPU. Requires state elements to hold intermediate values. one clock cycle or instruction
Multi-cycle Approach Single cycle CPU State element Combinational logic State element clock one clock cycle or instruction Multi-cycle CPU Requires state elements to hold intermediate values State Element
More informationCENG 3420 Lecture 06: Datapath
CENG 342 Lecture 6: Datapath Bei Yu byu@cse.cuhk.edu.hk CENG342 L6. Spring 27 The Processor: Datapath & Control q We're ready to look at an implementation of the MIPS q Simplified to contain only: memory-reference
More informationCENG 3420 Computer Organization and Design. Lecture 06: MIPS Processor - I. Bei Yu
CENG 342 Computer Organization and Design Lecture 6: MIPS Processor - I Bei Yu CEG342 L6. Spring 26 The Processor: Datapath & Control q We're ready to look at an implementation of the MIPS q Simplified
More informationWorking on the Pipeline
Computer Science 6C Spring 27 Working on the Pipeline Datapath Control Signals Computer Science 6C Spring 27 MemWr: write memory MemtoReg: ALU; Mem RegDst: rt ; rd RegWr: write register 4 PC Ext Imm6 Adder
More informationCS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 34 Single Cycle CPU Control I 24-4-16 Lecturer PSOE Dan Garcia www.cs.berkeley.edu/~ddgarcia 1.5 Quake?! NBC movie on May 3 rd. Truth stranger
More informationCS 61C: Great Ideas in Computer Architecture Datapath. Instructors: John Wawrzynek & Vladimir Stojanovic
CS 61C: Great Ideas in Computer Architecture Datapath Instructors: John Wawrzynek & Vladimir Stojanovic http://inst.eecs.berkeley.edu/~cs61c/fa15 1 Components of a Computer Processor Control Enable? Read/Write
More informationCS 61C: Great Ideas in Computer Architecture. MIPS CPU Datapath, Control Introduction
CS 61C: Great Ideas in Computer Architecture MIPS CPU Datapath, Control Introduction Instructor: Alan Christopher 7/28/214 Summer 214 -- Lecture #2 1 Review of Last Lecture Critical path constrains clock
More informationInstructor: Randy H. Katz hcp://inst.eecs.berkeley.edu/~cs61c/fa13. Fall Lecture #18. Warehouse Scale Computer
/29/3 CS 6C: Great Ideas in Computer Architecture Building Blocks for Datapaths Instructor: Randy H. Katz hcp://inst.eecs.berkeley.edu/~cs6c/fa3 /27/3 Fall 23 - - Lecture #8 So5ware Parallel Requests Assigned
More informationCS152 Computer Architecture and Engineering. Lecture 8 Multicycle Design and Microcode John Lazzaro (www.cs.berkeley.
CS152 Computer Architecture and Engineering Lecture 8 Multicycle Design and Microcode 2004-09-23 John Lazzaro (www.cs.berkeley.edu/~lazzaro) Dave Patterson (www.cs.berkeley.edu/~patterson) www-inst.eecs.berkeley.edu/~cs152/
More informationCS 61C: Great Ideas in Computer Architecture Control and Pipelining
CS 6C: Great Ideas in Computer Architecture Control and Pipelining Instructors: Vladimir Stojanovic and Nicholas Weaver http://inst.eecs.berkeley.edu/~cs6c/sp6 Datapath Control Signals ExtOp: zero, sign
More informationInitial Representation Finite State Diagram Microprogram. Sequencing Control Explicit Next State Microprogram counter
Control Implementation Alternatives Control may be designed using one of several initial representations. The choice of sequence control, and how logic is represented, can then be determined independently;
More informationCS61C : Machine Structures
CS 61C L path (1) insteecsberkeleyedu/~cs61c/su6 CS61C : Machine Structures Lecture # path natomy: 5 components of any Computer Personal Computer -7-25 This week Computer Processor ( brain ) path ( brawn
More informationSingle Cycle CPU Design. Mehran Rezaei
Single Cycle CPU Design Mehran Rezaei What does it mean? Instruction Fetch Instruction Memory clk pc 32 32 address add $t,$t,$t2 instruction Next Logic to generate the address of next instruction The Branch
More informationReview. N-bit adder-subtractor done using N 1- bit adders with XOR gates on input. Lecture #19 Designing a Single-Cycle CPU
CS6C L9 CPU Design : Designing a Single-Cycle CPU () insteecsberkeleyedu/~cs6c CS6C : Machine Structures Lecture #9 Designing a Single-Cycle CPU 27-7-26 Scott Beamer Instructor AI Focuses on Poker Review
More informationLecture 10: Control Unit
Lecture 10 What is control? Functional requirements for CPU Control Unit (Ohjausyksikkö) Ch 15-16 [Sta09] (Sta06:16-17) Micro-operations Control signals (Ohjaussignaalit) Hardwired control (Langoitettu
More informationLecture 10: Control Unit
Lecture 10 Control Unit (Ohjausyksikkö) Ch 15-16 [Sta09] (Sta06:16-17) Micro-operations Control signals (Ohjaussignaalit) Hardwired control (Langoitettu ohjaus) Microprogrammed control (Mikro-ohjelmoitu
More informationCS3350B Computer Architecture Quiz 3 March 15, 2018
CS3350B Computer Architecture Quiz 3 March 15, 2018 Student ID number: Student Last Name: Question 1.1 1.2 1.3 2.1 2.2 2.3 Total Marks The quiz consists of two exercises. The expected duration is 30 minutes.
More informationLecture 8: Control COS / ELE 375. Computer Architecture and Organization. Princeton University Fall Prof. David August
Lecture 8: Control COS / ELE 375 Computer Architecture and Organization Princeton University Fall 2015 Prof. David August 1 Datapath and Control Datapath The collection of state elements, computation elements,
More informationCS 61C: Great Ideas in Computer Architecture (Machine Structures) Lecture 28: Single- Cycle CPU Datapath Control Part 1
CS 61C: Great Ideas in Computer Architecture (Machine Structures) Lecture 28: Single- Cycle CPU Datapath Control Part 1 Guest Lecturer: Sagar Karandikar hfp://inst.eecs.berkeley.edu/~cs61c/ http://research.microsoft.com/apps/pubs/default.aspx?id=212001!
More informationCS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #17 Single Cycle CPU Datapath CPS today! 2005-10-31 There is one handout today at the front and back of the room! Lecturer PSOE, new dad
More informationMidterm I March 12, 2003 CS152 Computer Architecture and Engineering
University of California, Berkeley College of Engineering Computer Science Division EECS Spring 2003 John Kubiatowicz Midterm I March 2, 2003 CS52 Computer Architecture and Engineering Your Name: SID Number:
More informationMidterm I October 6, 1999 CS152 Computer Architecture and Engineering
University of California, Berkeley College of Engineering Computer Science Division EECS Fall 1999 John Kubiatowicz Midterm I October 6, 1999 CS152 Computer Architecture and Engineering Your Name: SID
More informationCO Computer Architecture and Programming Languages CAPL. Lecture 18 & 19
CO2-3224 Computer Architecture and Programming Languages CAPL Lecture 8 & 9 Dr. Kinga Lipskoch Fall 27 Single Cycle Disadvantages & Advantages Uses the clock cycle inefficiently the clock cycle must be
More informationThe Processor: Datapath & Control
Orange Coast College Business Division Computer Science Department CS 116- Computer Architecture The Processor: Datapath & Control Processor Design Step 3 Assemble Datapath Meeting Requirements Build the
More informationCOMP303 - Computer Architecture Lecture 10. Multi-Cycle Design & Exceptions
COP33 - Computer Architecture Lecture ulti-cycle Design & Exceptions Single Cycle Datapath We designed a processor that requires one cycle per instruction RegDst busw 32 Clk RegWr Rd ux imm6 Rt 5 5 Rs
More informationUniversity of California College of Engineering Computer Science Division -EECS. CS 152 Midterm I
Name: University of California College of Engineering Computer Science Division -EECS Fall 996 D.E. Culler CS 52 Midterm I Your Name: ID Number: Discussion Section: You may bring one double-sided pages
More informationCS 61C: Great Ideas in Computer Architecture Lecture 12: Single- Cycle CPU, Datapath & Control Part 2
CS 6C: Great Ideas in Computer Architecture Lecture 2: Single- Cycle CPU, Datapath & Control Part 2 Instructor: Sagar Karandikar sagark@eecs.berkeley.edu hbp://inst.eecs.berkeley.edu/~cs6c Midterm Results
More informationCSE 141 Computer Architecture Summer Session Lecture 3 ALU Part 2 Single Cycle CPU Part 1. Pramod V. Argade
CSE 141 Computer Architecture Summer Session 1 2004 Lecture 3 ALU Part 2 Single Cycle CPU Part 1 Pramod V. Argade Reading Assignment Announcements Chapter 5: The Processor: Datapath and Control, Sec. 5.3-5.4
More informationInf2C - Computer Systems Lecture 12 Processor Design Multi-Cycle
Inf2C - Computer Systems Lecture 12 Processor Design Multi-Cycle Boris Grot School of Informatics University of Edinburgh Previous lecture: single-cycle processor Inf2C Computer Systems - 2017-2018. Boris
More informationReview: Abstract Implementation View
Review: Abstract Implementation View Split memory (Harvard) model - single cycle operation Simplified to contain only the instructions: memory-reference instructions: lw, sw arithmetic-logical instructions:
More informationLecture 12: Single-Cycle Control Unit. Spring 2018 Jason Tang
Lecture 12: Single-Cycle Control Unit Spring 2018 Jason Tang 1 Topics Control unit design Single cycle processor Control unit circuit implementation 2 Computer Organization Computer Processor Memory Devices
More informationLecture Topics. Announcements. Today: Single-Cycle Processors (P&H ) Next: continued. Milestone #3 (due 2/9) Milestone #4 (due 2/23)
Lecture Topics Today: Single-Cycle Processors (P&H 4.1-4.4) Next: continued 1 Announcements Milestone #3 (due 2/9) Milestone #4 (due 2/23) Exam #1 (Wednesday, 2/15) 2 1 Exam #1 Wednesday, 2/15 (3:00-4:20
More informationCPE 335. Basic MIPS Architecture Part II
CPE 335 Computer Organization Basic MIPS Architecture Part II Dr. Iyad Jafar Adapted from Dr. Gheith Abandah slides http://www.abandah.com/gheith/courses/cpe335_s08/index.html CPE232 Basic MIPS Architecture
More informationThe Big Picture: Where are We Now? CS 152 Computer Architecture and Engineering Lecture 11. The Five Classic Components of a Computer
The Big Picture: Where are We Now? S 5 omputer Architecture and ngineering Lecture Multicycle ontroller esign (ontinued) The Five lassic omponents of a omputer Processor Input ontrol atapath Output Today
More informationLecture 7 Pipelining. Peng Liu.
Lecture 7 Pipelining Peng Liu liupeng@zju.edu.cn 1 Review: The Single Cycle Processor 2 Review: Given Datapath,RTL -> Control Instruction Inst Memory Adr Op Fun Rt
More informationCPE 335 Computer Organization. Basic MIPS Architecture Part I
CPE 335 Computer Organization Basic MIPS Architecture Part I Dr. Iyad Jafar Adapted from Dr. Gheith Abandah slides http://www.abandah.com/gheith/courses/cpe335_s8/index.html CPE232 Basic MIPS Architecture
More informationProcessor (multi-cycle)
CS359: Computer Architecture Processor (multi-cycle) Yanyan Shen Department of Computer Science and Engineering Five Instruction Steps ) Instruction Fetch ) Instruction Decode and Register Fetch 3) R-type
More informationMidterm I March 1, 2001 CS152 Computer Architecture and Engineering
University of California, Berkeley College of Engineering Computer Science Division EECS Spring 200 John Kubiatowicz Midterm I March, 200 CS52 Computer Architecture and Engineering Your Name: SID Number:
More informationRISC Design: Multi-Cycle Implementation
RISC Design: Multi-Cycle Implementation Virendra Singh Associate Professor Computer Architecture and Dependable Systems Lab Department of Electrical Engineering Indian Institute of Technology Bombay http://www.ee.iitb.ac.in/~viren/
More informationPipeline design. Mehran Rezaei
Pipeline design Mehran Rezaei How Can We Improve the Performance? Exec Time = IC * CPI * CCT Optimization IC CPI CCT Source Level * Compiler * * ISA * * Organization * * Technology * With Pipelining We
More informationLecture 9. Pipeline Hazards. Christos Kozyrakis Stanford University
Lecture 9 Pipeline Hazards Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee18b 1 Announcements PA-1 is due today Electronic submission Lab2 is due on Tuesday 2/13 th Quiz1 grades will
More informationCS420/520 Homework Assignment: Pipelining
CS42/52 Homework Assignment: Pipelining Total: points. 6.2 []: Using a drawing similar to the Figure 6.8 below, show the forwarding paths needed to execute the following three instructions: Add $2, $3,
More informationMidterm I March 12, 2003 CS152 Computer Architecture and Engineering
University of California, Berkeley College of Engineering Computer Science Division EECS Spring 23 John Kubiatowicz Midterm I March 2, 23 CS2 Computer Architecture and Engineering Your Name: SID Number:
More informationCS 152 Computer Architecture and Engineering. Lecture 12: Multicycle Controller Design
CS 152 Computer Architecture and Engineering Lecture 12: Multicycle Controller Design October 10, 1997 Dave Patterson (http.cs.berkeley.edu/~patterson) lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/
More informationCS 110 Computer Architecture Review Midterm II
CS 11 Computer Architecture Review Midterm II http://shtech.org/courses/ca/ School of Information Science and Technology SIST ShanghaiTech University Slides based on UC Berkley's CS61C 1 Midterm II Date:
More informationUC Berkeley CS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c UC Berkeley CS61C : Machine Structures Lecture 25 CPU Design: Designing a Single-cycle CPU Lecturer SOE Dan Garcia www.cs.berkeley.edu/~ddgarcia T-Mobile s Wi-Fi / Cell phone
More informationComputer Science 141 Computing Hardware
Computer Science 4 Computing Hardware Fall 6 Harvard University Instructor: Prof. David Brooks dbrooks@eecs.harvard.edu Upcoming topics Mon, Nov th MIPS Basic Architecture (Part ) Wed, Nov th Basic Computer
More informationEECS150 - Digital Design Lecture 10- CPU Microarchitecture. Processor Microarchitecture Introduction
EECS150 - Digital Design Lecture 10- CPU Microarchitecture Feb 18, 2010 John Wawrzynek Spring 2010 EECS150 - Lec10-cpu Page 1 Processor Microarchitecture Introduction Microarchitecture: how to implement
More informationMidterm I SOLUTIONS October 6, 1999 CS152 Computer Architecture and Engineering
University of California, Berkeley College of Engineering Computer Science Division EECS Fall 1999 John Kubiatowicz Midterm I SOLUTIONS October 6, 1999 CS152 Computer Architecture and Engineering Your
More informationinst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 18 CPU Design: The Single-Cycle I ! Nasty new windows vulnerability!
inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 18 CPU Design: The Single-Cycle I CS61C L18 CPU Design: The Single-Cycle I (1)! 2010-07-21!!!Instructor Paul Pearce! Nasty new windows vulnerability!
More informationCS152 Computer Architecture and Engineering Lecture 16: Memory System
CS152 Computer Architecture and Engineering Lecture 16: System March 15, 1995 Dave Patterson (patterson@cs) and Shing Kong (shing.kong@eng.sun.com) Slides available on http://http.cs.berkeley.edu/~patterson
More informationCS 61C: Great Ideas in Computer Architecture (Machine Structures) Single- Cycle CPU Datapath Control Part 1
CS 61C: Great Ideas in Computer Architecture (Machine Structures) Single- Cycle CPU Datapath Control Part 1 Instructors: Krste Asanovic & Vladimir Stojanovic hfp://inst.eecs.berkeley.edu/~cs61c/ Review
More informationCpE 442. Memory System
CpE 442 Memory System CPE 442 memory.1 Outline of Today s Lecture Recap and Introduction (5 minutes) Memory System: the BIG Picture? (15 minutes) Memory Technology: SRAM and Register File (25 minutes)
More informationadd rd, rs, rt Review: A Single Cycle Datapath We have everything Lecture Recap: Meaning of the Control Signals
CS6C L27 Single-Cycle CPU Control () inst.eecs.berkeley.edu/~cs6c UC Berkeley CS6C : Machine Structures Lecture 26 Single-cycle CPU Control 27-3-2 Ehausted TA Ben Sussman www.icanhascheezburger.com Qutrits
More informationLecture 5 and 6. ICS 152 Computer Systems Architecture. Prof. Juan Luis Aragón
ICS 152 Computer Systems Architecture Prof. Juan Luis Aragón Lecture 5 and 6 Multicycle Implementation Introduction to Microprogramming Readings: Sections 5.4 and 5.5 1 Review of Last Lecture We have seen
More information