Fundamentals of Computer Systems

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1 Fundamentals of Computer Systems Combinational Logic Stephen. Edwards Columbia University Summer 7

2 Combinational Circuits Combinational circuits are stateless. Their output is a function only of the current input. Inputs Combinational Circuit Outputs

3 asic Combinational Circuits Encoders and Decoders Priority Encoders Multiplexers Shifters Circuit Timing Critical Paths and Shortest Paths Glitches rithmetic Circuits Half and Full dders n dder/subtractor Overflow Carry Lookahead dder

4 Encoders and Decoders

5 Overview: Decoder decoder takes a n-bit input and produces n single-bit outputs. The binary input determines which output will be, all others. This is one-hot encoding. O I O I O O

6 Decoders -to-4 in out

7 Decoders -to-4 in out -to-8 decoder in out

8 Decoders -to-4 in out -to-8 decoder in out in 4-to-6 decoder out

9 The 748 -to-8 Decoder 5 Y 4 Y Select Inputs Y C Y Y4 Data Outputs Y5 G 6 9 Y6 Enable Inputs G 4 7 Y7 G 5

10 8 Spotted in the Wild Pac-Man (Midway, 98)

11 General n-bit Decoders Every minterm I n I I I n... I I I n I I. I n I I I n I I I n I I I n I I

12 General n-bit Decoders Implementing a function with a decoder: Every minterm E.g., F = C +C I n... I I I n I I I n I I. I n I I I n I I I n I I I n I I C F C F

13 The 7448 Priority Encoder Input: -of- n Output: n-bit binary number for highest priority input EO GS Inputs Outputs E 4567 G E XXXXXXXX XXXXXXX XXXXXX XXXXX XXXX XXX XX X EI

14 48 Spotted in the Wild Users would connect wires to interrupt sources; pull-ups quiet unconnected interrupts O68K Single-board Computer (Omnibyte 98)

15 Multiplexers

16 The Two-Input Multiplexer S Y S Y

17 The Two-Input Multiplexer S Y S Y S S Y S Y X X X X S Y

18 The Four-Input Mux D C Y D C S S Y S S Y C D S S

19 Two-input Muxes in the Wild Quad -to- mux selects color from a sprite or the background Pac-Man (Midway, 98)

20 General n -input muxes I n. I I n S n S S Y I n I. Y Y = I S n S S + I S n S S + I S n S S +. I n S n S S + I n S n S S I n n-to- n decoder S n S S

21 Using a Mux to Implement an rbitrary Function F = C +C C F

22 Using a Mux to Implement an rbitrary Function F = C +C pply each value in the truth table: C F C F

23 Using a Mux to Implement an rbitrary Function F = C +C pply each value in the truth table: C F C F

24 Using a Mux to Implement an rbitrary Function F = C +C pply each value in the truth table: C F C F

25 Using a Mux to Implement an rbitrary Function F = C +C C F

26 Using a Mux to Implement an rbitrary Function F = C +C C F

27 Using a Mux to Implement an rbitrary Function F = C +C Can always remove a select and feed in,, S, or S. C F C F C Y

28 Using a Mux to Implement an rbitrary Function F = C +C Can always remove a select and feed in,, S, or S. C F C F C Y

29 Using a Mux to Implement an rbitrary Function F = C +C Can always remove a select and feed in,, S, or S. C F C F C Y

30 Using a Mux to Implement an rbitrary Function F = C +C Can always remove a select and feed in,, S, or S. C F C F C Y

31 Using a Mux to Implement an rbitrary Function F = C +C Can always remove a select and feed in,, S, or S. C F C F In this case, the function just happens to be a mux: (not always the case!) C Y Y C

32 Using a Mux to Implement nother Function C F

33 Using a Mux to Implement nother Function C F

34 Using a Mux to Implement nother Function C F

35 Using a Mux to Implement nother Function C F F C C

36 Using a Mux to Implement nother Function C F F C C C F

37 Shifters shifter shifts the inputs bits to the left or to the right. IN n SHIFTER k CNTL n OUT There are various types of shifters. arrel: Selector bits indicate (in binary) how far to the left to shift the input. L/R with enable: Two control bits (upper enables, lower indicates direction). In either case, bits may roll out or wrap around

38 Example: arrel Shifter with Wraparound 8 SHIFTER 8

39 arrel Shifter with Wraparound Main idea: wire up all possible shift amounts and use muxes to select correct one. IN IN IN IN OUT OUT OUT OUT

40 arrel Shifter with Wraparound Main idea: wire up all possible shift amounts and use muxes to select correct one. IN IN IN IN CNTL,CNTL OUT OUT OUT OUT

41 arrel Shifter with Wraparound Main idea: wire up all possible shift amounts and use muxes to select correct one. IN IN IN IN CNTL,CNTL OUT OUT OUT OUT

42 arrel Shifter with Wraparound Main idea: wire up all possible shift amounts and use muxes to select correct one. IN IN IN IN CNTL,CNTL OUT OUT OUT OUT

43 arrel Shifter with Wraparound Main idea: wire up all possible shift amounts and use muxes to select correct one. IN IN IN IN CNTL,CNTL OUT OUT OUT OUT

44 arrel Shifter with Wraparound Main idea: wire up all possible shift amounts and use muxes to select correct one. IN IN IN IN CNTL,CNTL OUT OUT OUT OUT

45 Timing

46 Computation lways Takes Time 74LS There is always a delay between inputs and outputs because Limited currents charging capacitance The speed of light

47 The Simplest Timing Model In Out t p Each gate has its own propagation delay t p. When an input changes, any changing outputs do so after t p. Wire delay is zero.

48 More Realistic Timing Model In Out t p(max) t p(min) It is difficult to manufacture two gates with the same delay; better to treat delay as a range. Each gate has a minimum and maximum propagation delay t p(min) and t p(max). Outputs may start changing after t p(min) and stablize no later than t p(min).

49 Critical Paths and Shortest Paths C D Y How slow can this be?

50 Critical Paths and Shortest Paths C D Y How slow can this be? The critical path has the longest possible delay. t p(max) = t p(max, ND) +t p(max, OR) +t p(max, ND)

51 Critical Paths and Shortest Paths C D Y How fast can this be? The shortest path has the least possible delay. t p(min) = t p(min, ND)

52 Glitches glitch is when a single input change can cause multiple output changes. C C C +C +C C

53 Glitches glitch is when a single input change can cause multiple output changes. C C C +C +C C

54 Glitches glitch is when a single input change can cause multiple output changes. C C C +C +C C

55 Glitches glitch is when a single input change can cause multiple output changes. C C C +C +C C

56 Glitches glitch is when a single input change can cause multiple output changes. C C C +C +C C

57 Glitches glitch is when a single input change can cause multiple output changes. C +C +C C dding such redundancy only works for single input changes; glitches may be unavoidable when multiple inputs change.

58 rithmetic Circuits

59 rithmetic: ddition dding two one-bit numbers: and Produces a two-bit result: C S C S Half dder (carry and sum) C S

60 Full dder In general, you need to add three bits: C o + + = ++ = ++ = ++ = ++ = ++ = C i C o S C i C i C o S S

61 Four-it Ripple-Carry dder C o F C i F F F F S S 4 S S S S

62 Two s Complement dder/subtractor To subtract from, add and. Neat trick: carry in takes care of the + operation. SUTRCT/DD F F F F S 4 S S S S

63 Overflow in Two s-complement Representation When is the result too positive or too negative?

64 Overflow in Two s-complement Representation When is the result too positive or too negative? + + % + % + The result does not fit when the top two carry bits differ. n n n n S n S n % Overflow

65 Ripple-Carry dders are Slow C 4 S The depth of a circuit is the number of gates on a critical path. S This four-bit adder has a depth of 8. C S S n-bit ripple-carry adders have a depth of n.

66 Carry Generate and Propagate The carry chain is the slow part of an adder; carry-lookahead adders reduce its depth using the following trick: C K-map for the carry-out function of a full adder For bit i, C i+ = i i + i C i + i C i = i i +C i ( i + i ) = G i +C i P i Generate G i = i i sets carry-out regardless of carry-in. Propagate P i = i + i copies carry-in to carry-out.

67 Carry Lookahead dder Expand the carry functions into sum-of-products form: C i+ = G i +C i P i C = G +C P C = G +C P = G +(G +C P )P = G +G P +C P P C = G +C P = G +(G +G P +C P P )P = G +G P +G P P +C P P P C 4 = G +C P = G +(G +G P +G P P +C P P P )P = G +G P +G P P +G P P P +C P P P P

68 The 748 inary Carry-Lookahead dder 9 C4 4 4 Σ4 Carry out i has i + product terms, largest of which has i + literals. 5 4 Σ If wide gates don t slow down, delay is independent of number of bits. 6 Σ More realistic: if limited to two-input gates, depth is O(log n). 5 4 Σ 7 C

Fundamentals of Computer Systems

Fundamentals of Computer Systems Combinational Logic Martha. Kim Columbia University Spring 6 / Combinational Circuits Combinational circuits are stateless. Their output is a function only of the current