ECE232: Hardware Organization and Design

Transcription

1 ECE232: Harware Organization an Design ectre 11: Introction to IPs path apte from Compter Organization an Design, Patterson & Hennessy, CB

2 IPS-lite processor Compter Want to bil a processor for a sbset of IPS instrction set ( IPS-lite ) jst enogh to illstrate key ieas instrction set sbset (3 grops): arithmetic-logical: a, sb, an, or, slt memory reference: lw, sw control flow: j, beq can we write real programs with jst these? Nee p to 5 steps to eecte any instrction in or sbset Processor (CP) Control path Iemory IPS Instrctions Demory ECE232: Intro to IPs path 2

3 Instrction Eection Steps Instrction Fetch Decoe, Inc PC an Registers 1. I[PC] 2. Instrction Decoe, PC = PC + 4, Register rea Operation, Branch aress emory operation 3. operation, Branch aress comptation 4. W/STORE in memory Back 5. Register ECE232: Intro to IPs path 3

4 Biling a path for IPS (step 1) PC Instrction emory Step 1: instrction fetch Step 1... PC-4 PC PC+4 PC+8. ECE232: Intro to IPs path 4. a $t0,$t0,$t0 a $t0,$s1,$t0 lw $t1,20($s0) sw $t1,4($t0) Flow of eection

5 path Step 1: ny Instrction 4 PC ress 32-bit aer or wire only for a Clock Instrction Instrction emory (Iem) Once program is loae, Iem is rea-only ECE232: Intro to IPs path 5

6 Biling a path for IPS (step 2) PC Instrction emory Registers Step 1 Step 2: Decoe an Registers R op rs rt r shamt fnct a $t0,$s1,$t0 ECE232: Intro to IPs path 6

7 path Step 2: ny Instrction R op rs rt r shamt fnct a $t0,$t1,$t2 Instrction 6 Register 1 Register 2 Register ata 1 ata 2 Register File Control path Control Points ECE232: Intro to IPs path 7

8 Remaining Steps in Eecting Instrctions 3r step onwars epens on instrction class EX: for instrctions: a $t0, $t1, $t2 otpts from registers t1 an t2 will be sent to the inpt For emory-reference instrction: lw $t0,20($s0) ress Base + offset ECE232: Intro to IPs path 8

9 Biling a path for IPS (lw step 3) PC Instrction emory Registers Step 1 Step 2 Step 3 I op rs rt aress lw $t0, 20($s0) ECE232: Intro to IPs path 9

10 path Step 3-4: R-format Instrctions a, sb, an, or control Instrction [$t3] [$t1] [$t2] Register 1 Register 2 Register ata 1 ata 2 Registers Reg [$t1] [$t2] 3 Zero Reslt [$t1] [$t2] { +, -, ND, OR, etc.} 32 ECE232: Intro to IPs path 10

11 path Step 3: Branch beq $t0,$t1,loop PC + 4 from step 1 atapath Instrction Register 1 Register 2 Register Reg ata 1 ata 2 Registers [$t0] [$t1] control 3 Reslt Zero lt by 4 Branch target To branch control logic 16 Sign Eten 32 ECE232: Intro to IPs path 11

12 Steps 4,5 in Eecting lw,sw 4th step epens on instrction class E: for lw: Fetch from emory em[ress] For sw: Pt the contents of a register in emory lw $t1,20($s0) sw $t1,4($t0) PC Instrction emory Registers emory Step 1 Step 2 Step 3 Step 4 From Register for SW 5th step only for lw; rest are one for lw: Reslt Reg[rt] To register for W ECE232: Intro to IPs path 12

13 path Step 3-5: oa/store lw $t0,24($s3) op rs rt aress control em Instrction Register 1 Register 2 Register Reg ata 1 ata 2 Registers [$s3] 24 Zero [$s3]+24 Reslt ress ata Dem 16 Sign Eten 32 em ECE232: Intro to IPs path 13

14 Instrction Compose path: R-form + oa/store mes control em Register 1 Register 2 Register Reg 16 ata 1 ata 2 Registers Sign Eten 32 3 Src 0 = R-format 1 = oa/store Zero ress ata Dem em emto- Reg 0=R-form 1=/S 1 0 ECE232: Intro to IPs path 14

15 Compose path: + Iem + PC 4 a control em P C r Instrction Iem Reg1 Reg2 Reg Reg 16 ata1 ata2 Registers Sign Eten 32 Src 4 Zero ress ata Dem em emto- Reg ECE232: Intro to IPs path 15

16 Compose path: + Branch P C 4 r Instrction Iem Spports all IPS-lite instrctions? (slt an?) a Reg1 Reg2 Reg Reg 16 ECE232: Intro to IPs path 16 eft Shift 2 mole ata1 ata2 Registers Sign Eten 32 << 2 Src a con Zero PCSrc ress ata Dem em em emto- Reg

17 path: Register fiels Destination registers may iffer across instrction formats: R-format: [r] [rs] op [rt] a $t0,$s0,$s1 For this instrction, bits are the estination (t0), which shol be connecte to the write reg. inpts 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op rs rt r shamt fnct I-format: [rt] mem[[rs] + imm16] lw $t0,24($s3) 6 bits 5 bits 5 bits 16 bits For this instrction, bits shol go to the write reg. port. Bits 0-15 go to the as aress Connection to the write reg. port changes! Soltion? m to the resce! ECE232: Intro to IPs path 17 op rs rt offset

18 path (a RegDst ) P C r Iem 15:11 4 RegDst a 25:21 20:16 Reg1 Reg2 Reg Reg 15:0 ata1 ata2 Regs Sign Eten 31:0 Instrction src << 2 a Zero PCSrc ress ata Dem em em con emto- Reg ECE232: Intro to IPs path 18

19 path: Determine net PC What if instrction is a conitional branch (beq)? if operans eqal, take branch (PC gets PC+4+offset) else PC gets PC+4 Therefore, set control point PCSrc = 1 if an only if beq an Zero asserte ECE232: Intro to IPs path 19

20 path (a Branch control point) P C r 4 Iem 15:11 RegDst a 25:21 20:16 Reg1 Reg2 Reg Reg 15:0 ata1 ata2 Regs Sign Eten << 2 31:0 Instrction src Branch a Zero PCSrc ata ress Dem em em con emto- Reg ECE232: Intro to IPs path 20

21 Smmary Clear nerstaning of ENGIN112 components is necessary Review memories, registers, mltipleers, an s, if necessary The IPs processor is bilt from the escription of IPs instrctions How o we physically eecte each instrction? Ientify components that will perform the eection Share the components In this implementation, an instrction eection starts with the PC an ens with the completion of the instrction For eample, a two vales from registers an write the vale back to a register Don t get left behin Toay s material is critical to the net five weeks of the corse ECE232: Intro to IPs path 21