EXAMINATIONS 2003 END-YEAR COMP 203. Computer Organisation

Transcription

1 EXAINATIONS 2003 COP203 END-YEAR Compter Organisation Time Allowed: 3 Hors (180 mintes) Instrctions: Answer all qestions. There are 180 possible marks on the eam. Calclators and foreign langage dictionaries are allowed. No reference material is allowed. Every bo with a heavy otline reqires an answer. At the end of the eam script there is an appendi listing the IPS instrctions. Topic arks PART I 1 Basic Concepts and Performance 10 marks 2 achine Langage 26 marks 3 Compter Arithmetic 24 marks PART II 4 Processor Data Path and Control 25 marks 5 Pipelined Data Path 30 marks 6 emory Hierarchy 40 marks 7 Bs Protocols 25 marks 1

2 PART I Qestion 1. Basic Concepts and Performance [10 marks] a) [5 marks] Given the following descriptions: A. Base 2 nmber. B. Binary digit. C. Component of a processor that performs arithmetic operations. D. Active part of a compter. It eectes the instrctions of programs. E. Component of a processor that tells the datapath, memory, and I/O devices what to do according to the instrctions of a program. F. Where programs are stored while they are rnning. G. Program that translates a symbolic version of an instrction into its binary version. H. Program that translates from a high level langage notation to assembly langage. I. Program that manages the resorces of a compter for the programs that rn on that machine. J. Individal command to a compter. For each term below, write the letter of the description that best matches the term. 1. Assembler: 2. emory: 3. Compiler: 4. Bit: 5. Instrction: 6. CPU: 7. ALU: 8. Binary nmber: 9. Control: 10. Operating system: 2

3 b) [5 marks] Identify si minimal combinations of the measres below that can be sed to calclate the eection time of a particlar program on a particlar machine: {CPI, rate, period, IPS, C, I} where: CPI refers to the average clock cycles per instrction, rate is the clock freqency/rate, period is the clock period, IPS is the average nmber of instrctions per millisecond (million instrctions per second), C is the nmber of clock cycles sed to eecte the program, and I is the nmber of instrctions that the program will eecte. 3

4 Qestion 2. achine Langage [26 marks] a) [8 marks] Consider the following segment of C code: while (i <= h) { g = g + A[i]; i = i + j; } g = g j; Assme that the registers $s1, $s2, $s3, $s4, and $s5 hold integer variables g, h, i, j, and the base address of integer array A, respectively. Insert a single instrction in each of the three otlined spaces labeled as 1, 2, 3 and 4, so that the reslting seqence of IPS instrctions directly corresponds to the above C code segment. Loop: slt $t0, $s2, $s add $t1, $s3, $s3 add $t1, $t1, $s5 lw $t2, 0($t1) add $s1, $s1, $t2 add $s3, $s3, $s4 3. Eit: 4. 4

5 b) [8 marks] Given the following C procedre/fnction: int eam(int t, int, int v) { int w; w = t + v - 2; } retrn w; Assme that the registers $a0, $a1 and $a2 hold variables t, and v, respectively, and that register $s0 is sed to store the local variable w. Insert a single instrction in each of the otlined spaces labeled as 1, 2, 3, and 4, so that the reslting seqence of IPS instrctions directly corresponds to the above procedre/fnction. eam: 1. sw $s0, 0($sp) add $s0, $a0, $a1 sb $s0, $s0, $a2 addi $s0, $s0, lw $s0, 0($sp)

6 c) [5 marks] Given the following C code segment: /* This fnction does a string copy --- copy the string stored in y to */ void strcpy(char [], char y[]) { int i; } while (([i] = y[i])!= 0) i++; Assme the registers $t0, $a0 and $a1 hold variable i, the base address of character array (string), and the base address of character array (string) y respectively. Insert a single instrction in each of the otlined spaces labeled as 1 and 2, so that the reslting seqence of IPS instrctions directly corresponds to the above segment. strcpy: addi $t0, $zero, 0 Loop:add $t1, $a1, $t0 1. add $t3, $a0, $t0 2. beq $t2, $zero, Eit addi $t0, $t0, 1 j Loop Eit: jr $ra 6

7 d) [5 marks] Consider the following seqence of IPS instrctions: li $s1, addi $s2, $s1, What headecimal vales will be stored in $s2? (Hint: take care with the immediate operand) $s2 = 7

8 Qestion 3. Compter Arithmetic [24 marks] As discssed in the lectres, bit patterns have no inherent meaning. They may represent signed integers, nsigned integers, floating point nmbers, and even machine instrctions. For qestions a) to c), yo may epress nmbers in the form like ( ). Given the bit pattern below: What does it represent, if it is a) [3 marks] a two s complement integer? b) [2 marks] a nsigned integer? c) [4 marks] a single precision floating point nmber (Assming the above bit pattern is in IEEE 754 binary representation)? d) [5 marks] a IPS instrction? 8

9 e) [10 marks] This qestion concerns overflow detection and maniplation. Sppose that A and B are two negative integers stored in registers $s1 and $s2, respectively. Write a seqence of IPS instrctions (at most 10) to process all the following tasks: perform C = A + B; (Store C in register $s3) if there is no overflow, add constant 10 to C and place the reslt in register $s4; otherwise, set the most significant bit of C to 0. Use temporary registers if necessary. 9

10 SPARE PAGE FOR EXTRA S Cross ot the rogh working that yo do not want marked. Specify the qestion nmber for work yo do want marked. 10

11 SPARE PAGE FOR EXTRA S Cross ot the rogh working that yo do not want marked. Specify the qestion nmber for work yo do want marked. 11

12 PART II Qestion 4: Processor DataPath and Control [25 marks] Consider the diagram on the facing page showing the IPS lti Cycle Data Path. a) [10 marks] On the diagram, show the lines and all the components that will be sed to fetch and eecte a IPS sw instrction. Trace the lines and circle the components sing a colored pen. b) [3 marks] Which operations are eected in the first cycle? c) [4 marks] Which operations are eected in the second cycle? d) [3.5 marks] Which operations are eected in the third cycle of a sw instrction? e) [3.5 marks] Which operations are eected in the forth cycle of a sw instrction? f) [1 mark] Which operations are eected in the fifth cycle of a sw instrction? 12

13 Target PC Address Write data emdata emory Instrction register Reg Reg Reg Data Data Data Registers 4 ALU reslt Sign etend Shift left 2 13

14 Qestion 5: Pipelined Data Path [30 marks] a) [10 marks] The diagram on the facing page contains the Pipelined IPS Data Path. Sppose the machine is eecting an isolated sw IPS instrction. On the diagram, show all the lines and components that will be sed when eecting the instrction in all pipeline stages. Trace the lines and circle the components sing a colored pen. Note: Yo do not need to consider control in yor answer. 14

15 IF ID EX E WB Add IF/ID ID/EX EX/E E/WB P C S h I f t Add Instrction memory Registers ALU Data memory Sign eten d 15

16 b) Consider the fragment of an assembly program given below. This program is eected in a pipelined processor. 100 lw $s0, 0($t0) 104 add $t2, $t2, $t0 108 sw $t1, 4($t2) i). [5 marks] Which instrction will be at risk of a hazard if the datapath does not have any forwarding? Why wold this hazard happen? How many nops wold be needed to prevent the hazard and where? To calclate the nmber of nops needed, consider the table below. Instrction Stage when register file read Stage when reslt written to register file or memory lw 2 5 add 2 5 sw 2 4 ii) [5 marks] The diagram on the facing page contains a part of a pipelined datapath with the forwarding nit. Focsing on the hazard yo identified in the qestion i) above show all the lines and components that will be sed when preventing the hazard. Consider only data and control involved in preventing the hazard. Trace both data and control lines and circle both data and control components sing a colored pen. 16

17 ID/EX EX/E E/WB sw $t1, 4($t2) Registers ALU add $t2, $t2, $t0 Data memory lw $s0, 0($t0) rs, rt Forwarding nit rd Rd data data 17

18 c) Consider the fragment of an assembly program given below. This program is eected in a pipelined processor. 100 lw $t0, 0($s0) 104 add $s2, $s2, $s0 108 sw $s2, 4($s1) i). [5 marks] Which instrction will be at risk of a hazard if the datapath does not have any forwarding? Why wold this hazard happen? How many nops wold be needed to prevent the hazard and where? To calclate the nmber of nops needed, consider the table below. Instrction Stage when register file read Stage when reslt written to register file or memory lw 2 5 add 2 5 sw 2 4 ii). [5 marks] The diagram on the facing page contains a part of a pipelined datapath with the forwarding nit. Focsing on the hazard yo identified in the qestion i) above show all the lines and components that will be sed when preventing the hazard. Consider only data and control involved in preventing hazard. Trace both data and control lines and circle both data and control components sing a colored pen. 18

19 ID/EX EX/E E/WB sw $s2, 4($s1) Registers ALU add $s2, $s2, $s0 Data memory lw $t0, 0($s0) rs, rt Forwarding nit rd Rd data data 19

20 Qestion 6. emory Hierarchy [40 marks] This qestion considers a IPS processor with: A 500 Hz clock freqency, A 32 bit (4 byte) register and main memory word size, A main memory size of 256 B, A processor cache, and A Translation Lookaside Bffer (TLB). The main memory is connected to the processor cache via a synchronos bs. One memory word is transferred to the cache dring one bs transaction. One bs transaction takes 10 processor cycles. Access to the processor cache and to the TLB each reqire one processor cycle. The virtal memory space is 4 GB and virtal memory pages are 4 KB. When the processor isses an address reqest, it performs a TLB look p to translate the virtal into a physical address and then accesses the cache. Figre 6.1 shows a part of a page table. Note that all slot nmbers are headecimal. If a virtal page is in memory, its physical page nmber (PPN) is also given as a headecimal nmber. If a virtal page is on disk, its PPN has its disk address in the form (c i,t i, s i ), where i {0, 1, }, c is a cylinder nmber, t is a track nmber, and s is a sector nmber. V PPN 0 00a0c In emory a0d Not Used 0 00a0e In emory 0 abc6 0 00a0f On Disk (c1, t1, s1) 0 00a10 In emory a11 On Disk (c1, t1, s2) Figre 6.1. The compter configration also contains a disk with the following characteristics: Controller latency 2 ms, Average seek time 7.6 ms, Rotational speed 3000 revoltions per minte, and Transfer rate 10 B/s. Also note if a page falt occrs, yo may neglect the memory access times with regard to average disk access time when yo compte the miss penalty. a) [3 marks] Sppose a page table entry is 1 word. What is the size of a page table? The size of a page table = 20

21 b) [8 marks] How many bits does each of the following have? A main memory address = A virtal page nmber = A physical page nmber = An offset inside a page = c) [6 marks] Consider Figre 6.1. Sppose the processor issed the following three virtal addresses AP 1 = AV 1 = 0 00a0eff0 AV 2 = 0 00a10000 AV 3 = 0 00a11772 What are the corresponding physical addresses AP 1, AP 2, and AP 3 that AV 1, AV 2, and AV 3 will be translated into? AP 2 = AP 3 = d) [5 marks] Sppose the address AV 1 makes a hit in the TLB, and the address AP 1 makes a hit in the processor cache. How long will elapse from the moment the processor reqested the AV 1 till the moment the content of AP 1 was delivered to the processor? In yor answer, specify the nmber of processor cycles and the total time. The nmber of processor cycles = The total elapsed time = 21

22 e) [8 marks] Consider Figre 6.1 and sppose the address AV 2 makes a miss in the TLB. Also sppose the address AP 2 makes a miss in the processor cache. Ignore TLB and cache accesses, bt consider all needed accesses to the main memory. Answer the following qestions: How many accesses to the main memory will be needed to accomplish the transfer of the word reqested to the cache? How many processor cycles will be needed for these main memory accesses? How long will it take to perform these memory accesses? The nmber of main memory accesses = The nmber of processor cycles = The time needed for memory accesses = f) [10 marks] Consider Figre 6.1 and the virtal address AV 3. Calclate the average time needed to deliver the reqested word to the processor. 22

23 SPARE PAGE FOR EXTRA S Cross ot the rogh working that yo do not want marked. Specify the qestion nmber for work yo do want marked. 23

24 Qestion 7. Bs Protocols [25 marks] Sppose a 500 Hz IPS processor has a hard disk with the transfer rate of 10 B/s connected to the system bs. The average time to read a 4 KB block from disk is 20 ms. The disk controller has a bffer of 8 bytes. a) [15 marks] Sppose the processor controls the disk operations sing an interrpt driven bs protocol, bt the disk controller has no DA (Direct emory Access) capability. To service a disk interrpt and to control the transfer of 8 bytes from the disk controller to the main memory the processor takes 400 clock cycles. Calclate the processor overhead dring one whole disk read operation. b) [10 marks] Sppose the disk controller has a DA (Direct emory Access) capability. The processor ses 1000 clock cycles to initiate a disk operation and 1000 clock cycles to handle a disk interrpt after the data transfer completion. Calclate the processor overhead dring one whole disk read operation. 24

25 SPARE PAGE FOR EXTRA S Cross ot the rogh working that yo do not want marked. Specify the qestion nmber for work yo do want marked. 25

26 APENDIX Commonly Used IPS Instrctions Arithmetic and Logical Instrctions add Rdest, Rsrc1, Src2 Addition (with overflow) addi Rdest, Rsrc1, Imm Addition Immediate (with overflow) add Rdest, Rsrc1, Src2 Addition (withot overflow) and Rdest, Rsrc1, Src2 AND andi Rdest, Rsrc1, Imm AND Immediate. Pt the logical AND of the integers from register Rsrc1 and Src2 (or Imm) into register Rdest. or Rdest, Rsrc1, Src2 OR ori Rdest, Rsrc1, Imm OR Immediate. Pt the logical OR of the integers from register Rsrc1 and Src2 (or Imm) into register Rdest. sll Rdest, Rsrc1, Src2 Shift Left Logical srl Rdest, Rsrc1, Src2 Shift Right Logical sb Rdest, Rsrc1, Src2 Sbtract (with overflow) sb Rdest, Rsrc1, Src2 Sbtract (withot overflow) Pt the difference of the integers from register Rsrc1 and Src2 into register Rdest. Constant-aniplating Instrctions li Rdest, imm Load Immediate. ove the immediate imm into register Rdest. li Rdest, imm Load Upper Immediate Load the lower halfword of the immediate imm into the pper halfword of register Rdest. The lower bits of the register are set to 0. Comparison Instrctions slt Rdest, Rsrc1, Src2 Set Less Than 26

27 slti Rdest, Rsrc1, Imm Set Less Than Immediate slt Rdest, Rsrc1, Src2 Set Less Than Unsigned Branch and Jmp Instrctions beq Rsrc1, Src2, label Branch on Eqal. Conditionally branch to the instrction at the label if the contents of register Rsrc1 eqals Src2. bne Rsrc1, Src2, label Branch on Not Eqal. Conditionally branch to the instrction at the label if the contents of register Rsrc1 are not eqal to Src2. j label Jmp. Unconditionally jmp to the instrction at the label. jal label Jmp and Link jalr Rsrc Jmp and Link Register. Unconditionally jmp to the instrction at the label or whose address is in register Rsrc. Save the address of the net instrction in register 31. jr Rsrc Jmp Register. Unconditionally jmp to the instrction whose address is in register Rsrc. Load Instrctions lw Rdest, address Load Word. Load the 32-bit qantity (word) at address into register Rdest. lb Rdest, address Load Byte. Load the 8-bit qantity (byte) at address into register Rdest. Store Instrctions sw Rsrc, address Store Word. Store the word from register Rsrc at address. sb Rsrc, address Store Byte. Store the byte from register Rsrc at address. Commonly Used IPS Fields There are si commonly sed IPS fields: op, rs, rt, rd, shamt, and fnct. The op and fnct are sally sed to represent and distingish between different operations/instrctions. The following table gives the op and fnct for the commonly sed IPS instrctions. Instrctions op Fnct add 0 32 sb 0 34 lw 35 NA sw 43 NA beq 4 NA bne 5 NA slt 0 42 j 2 NA jal 3 NA jr 0 8 * * * * * * * * * * * * * * * * * * 27 end