Lecture 13: Exceptions and Interrupts

Transcription

1 Lectre 13: Eceptions and Interrpts S 10 L13 1 James C. Hoe Dept of ECE, CU arch 1, 2010 Annoncements: Handots: Spring break is almost here Check grades on Blackboard idterm 1 graded Handot #9: Lab 3 (on Blackboard) Eceptions and Interrpts A systematic way to handle eceptional conditions that are relatively rare, bt mst be detected and acted pon qickly instrctions may fail and cannot complete eternal I/O devices may need servicing qantm epiration in a time shared system Option 1: write every program with continos checks (a.k.a. polling) for every possible contingency acceptable for simple embedded systems (toaster) Option 2: write normal programs for the best case scenario where nothing nsal happens detect eceptional conditions in HW transparently transfer control to an eception handler that knows how to resolve the condition and then back to yor program S 10 L13 2

2 Interrpt Control Transfer An interrpt is an nplanned fnction call to a system rotine (aka, the interrpt handler) Unlike a normal fnction call, the interrpted thread cannot anticipate the control transfer or prepare for it in any way Control is later retrned to the main thread at the interrpted instrction The control transfer to the interrpt handler and back mst be 100% transparent to the interrpted thread!!! i 1 H 1 i 2 H 2 i 3. H n S 10 L13 3 Types of Interrpts S 10 L13 4 Synchronos Interrpts (a.k.a. eceptions) eceptional conditions tied to a particlar instrction e.g. illegal opcode, illegal operand, virtal memory management falts the falting instrction cannot be finished no forward progress nless handled immediately Asynchronos Interrpts (a.k.a. interrpts) eternal events not tied to a particlar instrction I/O events, timer events some fleibility on when to handle it cannot postpone forever or things start to fall on the floor System Call/Trap Instrction an instrction whose only prpose is to raise an eception whatever for?

3 Interrpt Sorces S 10 L13 5 l devices.) CPU interrpt control logic datapath failed instrctions system call instrctions Eceptions, a.k.a. synchronos interrpts IRQ lines from eterna (I/O, DA, timers, etc. Interrpts, a.k.a. asynchronos interrpts eternal interrpts Virtalization and Protection S 10 L13 6 odern OS spports time shared mltiprocessing bt each ser level process still thinks it is alone each process sees a private set of ser level architectral states that can be modified by the serlevel instrction set each process cannot see or maniplate (directly) state and devices otside of this abstraction OS implements and manages a critical set of fnctionality keep low level details ot of the ser level process protect the ser level process from each other and itself Do yo want to access/manage harddisk directly? Do yo trst yor bddy or yorself to access the harddisk directly?

4 Privilege Levels S 10 L13 7 The OS mst somehow be more powerfl to create and maintain sch an abstraction, hence a separate privileged (akaprotectedor or kernel) mode additional architectral states and instrctions, in particlar those controlling virtalization/ protection/isolation the kernel code rnning in the privileged mode has access to the complete bare hardware system ser level level state and instrctions privileged level hypervisor level for virtalizing mltiple OSs Control and Privilege Transfer S 10 L13 8 User level code never rns in the privileged mode Processor enters the privileged mode only on interrpts ser code srrenders control to a handler in the OS kernel The handler restores privilege level back to ser mode before retrning control to the ser code i 1 i 2 i 3 H 1 H 2. H n

5 S 10 L13 9 Implementing Interrpts Precise Interrpt/Eception Seqential Code Semantics Overlapped Eection S 10 L13 10 i 1 i 2 i 1 : i 2 : i 3 : i 3 A precise interrpt appears (to the interrpt handler) to take place eactly between two instrctions older instrctions finished completely yonger instrctions as if never happened on synchronos interrpts, eection stops jst before the falting instrction

6 S 10 L13 11 Stopping and Restarting a Pipeline t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 IF I 0 I 1 I 2 I 3 I 4 I h I h+1 I h+2 I h+3 ID I 0 I 1 I 2 I 3 I h I h+1 I h+2 EX I 0 I 1 I 2 I h I h+1 E I 0 I 1 I 2 I h WB I 0 I 1 I 2 What if I 0, I 1, I 2, I 3 and I 4 all generate eceptions in t 4? How wold things look different for asynchronos interrpts? S 10 L13 12 Eception Sorces in Different Stages IF instrction memory address/protection falt ID illegal opcode trap to SW emlation of nimplemented instrctions system call instrction (a SW reqested eception) EX invalid reslts: overflow, divide by zero, etc E data memory address/protection falt WB nothing can stop an instrction now We can associate async interrpts (I/O) with any instrction/stage we like

7 Pipeline Flsh for Eceptions S 10 L13 13 IF.Flsh ID.Flsh EX.Flsh Hazard detection nit ID/EX WB 0 EX/E IF/ID Control 0 EX Case 0 WB E/WB WB PC 4 Instrction memory Shift left 2 Registers = Ecept PC ALU Data memory Sign etend Figre from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.] Forwarding nit carry PC in the pipeline with each inst. new pipeline flsh points S 10 L13 14 IPS Interrpt Architectre

8 IPS Interrpt Architectre S 10 L13 15 Privileged system control registers Eception Program Conter (EPC, CR14): which instrction i did we stop on Interrpt Case Register (CR 13): what cased the interrpt Interrpt Stats Register (CR 12): enable and disable interrpts, set privilege modes Loaded atomatically on interrpt transfer events Also accessed by the move from/to co processor 0 instrction: mfc0 Ry, CR and mtc0 Ry, CR Figres from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.] IPS Interrpt Architectre S 10 L13 16 On an interrpt transfer, the CPU hardware saves the interrpt address to EPC can t jst leave frozen in the PC: overwritten immediately can t se r31 as in a fnction call: need to save ser vale In general, CPU hardware mst saves any sch information that cannot be saved and restored in software by the interrpt handler (very few sch things) For eample, the GPR can be managed in SW by the interrpt handler sing a callee saved convention however, r26 and r27 are reserved by convention to be available to the kernel immediately at the start and the end of an interrpt handler

9 Interrpt Servicing S 10 L13 17 On an interrpt transfer, the CPU hardware records the case of the interrpt in a privileged registers (Interrpt Case Register) Option 1: Control is transfer to a pre fied defalt interrpt handler address this initial handler eamines the case and branches to the appropriate handler sbrotine to do the work this address is protected from ser level process so one cannot jst jmp or branch to it Option 2: Vectored Interrpt a bank of privileged registers to hold a separate specialized handler address for each interrpt sorce On an interrpt, hardware transfer control directly to the appropriate handler to save interrpt overhead IPS ses a 7 instrction handler for TLB miss Eample of Cases S 10 L13 18 Figre from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]

10 Handler Eamples S 10 L13 19 On asynchronos interrpts, device specific handlers are invoked to service the I/O devices On eceptions, kernel handlers are invoked to either correct the falting condition and contine the program (e.g., emlate the missing FP fnctionality, pdate virtal memory management), or signal back to the ser process if a ser level handler fnction is registered, or kill the process if the eception cannot be corrected System call is a special kind of fnction call from ser process to kernel level service rotines Retrning from Interrpt Software restores all architectral state saved at the start of the interrpt rotine S 10 L13 20 IPS32 ses a special jmp instrction (ERET) to atomically restore the atomatically saved CPU states restore the privilege level jmp back to the interrpted address in EPC IPS R2000 sed a pair of instrctions jr r26 // jmp to a copy of EPC in r26 rfe // restore from eception mode // mst be sed in the delay slot!!

11 Branch Delay Slot and RFE What if the falting address is a branch delay slot? simply jmping back to the falting address won t contine correctly if the preceding branch was taken we didn t save enogh information to do the right thing IPS s soltion the CPU HW makes a note (in the Case register) if the falting address captred is in a delay slot in these cases, the handler retrns to the preceding branch instrction which gets eected twice (as the last instrction before and first instrction after) Generally harmless ecept JALR r31 eplicitly disallowed by the IPS ISA think abot what wold happen in that case S 10 L13 21 An Etremely Short Handler S 10 L13 22 _handler_shortest: # no prologe needed... short handler body... # can se only r26 and r27 # interrpt not re enabled for # something really qick # epiloge mfc0 r26,epc jr 26 rfe # get falting PC # jmp to retry falting PC # restore from eception mode Note: Yo can find more eamples in the book CD. If yo are really serios abot it, take a look inside Lin sorce. It is not too hard to figre ot once yo know what to look for.

12 A Short Handler _handler_short: # prologe addi sp, sp 08 # allocate stack space (8 byte) sw r8, 00(sp) # back p r8 and r9 for se in body sw r9, 04(sp) # S 10 L short handler body... # can se r26, r27, and r8, r9 # interrpt not re enabled # epiloge lw r8, 00(sp) # restore r8, r9 lw r9, 04(sp) # addi sp, sp, 08 # restore stack pointer mfc0 r26,epc # get EPC j r26 # jmp to retry EPC rfe # restore from eception mode Nesting Interrpts S 10 L13 24 On an interrpt control transfer, frther asynchronos interrpts are disabled atomatically another interrpt wold overwrite the contents of the EPC and Interrpt Case and Stats Registers the handler mst be careflly written to not generate synchronos eceptions itself dring this window of vlnerability For long rnning handlers, interrpt mst be re enabled to not missed additional interrpts the handler mst save the contents of EPC/Case/Stats to memory (stack) before re enabling asynchronos interrpt once interrpts are re enabled, EPC/Case/Stats is clobbered by the net interrpt (contents appear to change for no reason)

13 Interrpt Priority S 10 L13 25 Asynchronos interrpt sorces are ordered by priorities higher priorities interrpts are more timing critical if mltiple interrpts are triggered, the handler handles the highest priority interrpt first Interrpts from different priorities can be selectively disabled by setting the mask in the Stats register (actally a SW convention in IPS) When servicing a particlar priority interrpt, the handler only re enable higher priority interrpts higher priority interrpt won t get delayed Re enabling same/lower priority interrpts may lead to an infinite loop if a device interrpts repeatedly Nestable Handler _handler_nest: # prologe addi sp, sp, 08 # allocate stack space for EPC mfc0 r26, epc # get EPC sw r26, 00( 00(sp) # store EPC onto stack sw r8, 04(sp) # allocate a register for se later addi r26, r0, 0405 # set interrpt enable bit mtc0 r26, stats # write into stats reg S 10 L interrptible # cold free p more registers longer handler body... # to stack if needed # epiloge addi r8, r0, 0404 mtc0 r8, stats ld r26, 00(sp) ld r8, 04(sp) addi sp, sp, 08 j r26 rfe # clear interrpt enable bit # write into stats reg # get EPC back from stack # restore r8 # restore stack pointer # jmp to retry EPC # restore from eception mode