Animating the Datapath. Animating the Datapath: R-type Instruction. Animating the Datapath: Load Instruction. MIPS Datapath I: Single-Cycle

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1 nimating the atapath PS atapath : Single-Cycle npt is either (-type) or sign-etended lower half of instrction (load/store) op offset/immediate W egister File from instrction path beq,, offset if ([] == []) then <- + + s_etend(offset) ata is either from (-type) or (load) Combining the paths for -type instrctions and load/stores sing two mltipleo Fig.. Page nimating the atapath: -type nimating the atapath: Load 6 W egister File add,, 6 W egister File lw,offset() 6 Src em ata emory em emtoeg 6 Src em ata emory em emtoeg

2 6 nimating the atapath: Store W egister File 6 Src sw,offset() em ata emory em emtoeg PS atapath : Single-Cycle dd Separate instrction as instrction and read occr in the same clock cycle Separate adder as operations and increment occr in the same clock cycle egiste 6 etend Src dding instrction fetch operation reslt ddress em em ata emtoeg PS atapath : Single-Cycle atapath ecting add add,, Src ew mltipleor dd is either + or branch target egiste 6 etend left Src dd reslt tra adder needed as both adde operate in each cycle operation em reslt ddress em ata emtoeg emory 6 W egister File 6 Src Src em ata emory em emtoeg dding branch capability and another mltipleor mpoant note: in a single-cycle implementation cannot be stored dring an instrction it only moves throgh combinational logic Qestion: is the em signal really needed?! hink of!

3 atapath ecting lw lw,offset() atapath ecting sw sw,offset() emory 6 W egister File 6 Src Src em ata emory em emtoeg emory 6 W egister File 6 Src Src em ata emory em emtoeg atapath ecting beq beq r,r,offset nit takes inpt from the instrction opcode bits emory 6 W egister File 6 Src Src em ata emory em emtoeg nit generates control inpt write enable (possibly, read enable also) signals for each storage element selector controls for each mltipleor

4 Plan to control : main control sends a -bit Op control field to the control. ased on Op and fnct field of instrction the control generates the -bit control field ecall from Ch. control Fncfield tion and or add sb slt ain mst perform add for load/stores (Op ) sb for branches (Op ) one of and, or, add, sb, slt for -type instrctions, depending on the instrction s 6-bit fnct field (Op ) 6 fnct field Op Op generation by main control control inpt o Setting its lop Fnct Field esired control opcode operation action inpt LW load wo add SW store wo add ranch eq branch eq sbtract -type add add -type sbtract sbtract -type and -type O or -type set on less set on less *ypo in tet Fig..: if it is then there is potential conflict between line and lines -7! Op Fnct field Op Op F F F F F F * h table for control bits esigning the ain atapath with Src -type Load/store or branch opcode opcode shamt fnct Observations abot PS instrction format opcode is always in bits -6 two s to be read are always (bits -) and (bits - 6) base for load/stores is always (bits -) 6-bit offset for branch eqal and load/store is always bits - destination for loads is in bits -6 () while for -type instrctions it is in bits - () (will reqire mltipleor to select) dd [ ] ew mltipleor [ ] [ 6] [ ] egst [ ] egiste 6 etend [ ] left Src control Op dd reslt reslt em ddress ata em emtoeg dding control to the PS atapath (and a new mltipleor to select field to specify destination ): what are the fnctions of the control signals?

5 als atapath with al ame ffect when deasseed ffect when asseed egst he destination nmber for the he destination nmber for the comes from the field (bits -6) comes from the field (bits -) one he on the inpt is written with the vale on the inpt llsrc he second operand comes from the he second operand is the sign-etended, second file otpt ( ) lower 6 bits of the instrction Src he is replaced by the otpt of the adder he is replaced by the otpt of the adder that comptes the vale of + that comptes the branch target em one ata contents designated by the inpt are pt on the fit otpt em one ata contents designated by the inpt are replaced by the vale of the inpt emtoeg he vale fed to the inpt he vale fed to the inpt comes from the comes from the dd [ ] [ 6] [ ] [ 6] [ ] [ ] egst ranch em emtoeg Op em Src egiste 6 etend left control dd reslt reslt ddress Src ata ffects of the seven control signals [ ] PS path with the control nit: inpt to control is the 6-bit instrction opcode field, otpt is seven -bit signals and the -bit Op signal dd egst ranch em left dd reslt Src Src cannot be set directly from the opcode: zero test otcome is reqired als: -ype [ 6] emtoeg Op em Src [ ] [ ] [ 6] [ ] [ ] egiste [ ] 6 etend egst Src emto- eg eg em em ranch Op p -format lw sw beq control reslt etermining control signals for the PS path based on instrction opcode ddress ata emory immediate/ offset [:] signals shown in ble 6 [:] [:6] W egister File [:] 6??? egst Src Vale depends on fnct Src em ata emory em emtoeg

6 als: lw als: sw emory immediate/ offset [:] signals shown in ble 6 [:] [:6] W egister File [:] 6 egst Src Src em ata emory em emtoeg emory immediate/ offset [:] signals shown in ble 6 [:] [:6] W egister File [:] 6 egst Src Src em ata emory em emtoeg als: beq Jmp atapath with opcode -6 Composing jmp - target ew mltipleor with additional control bit Jmp [ ] Jmp [ ] left 6 8 emory immediate/ offset [:] signals shown in ble 6 [:] [:6] W egister File [:] 6 egst Src Src if = em ata emory em emtoeg dd [ ] + [ 8] [ 6] [ ] [ 6] [ ] [ ] egst Jmp ranch em emtoeg Op em Src egiste [ ] 6 etend left control dd reslt reslt ddress ata PS path etended to jmps: control nit generates new Jmp control bit

7 atapath ecting j -type : Step add $t, $t, $t (active = bold) emory jmpaddr [:] 6 op [: nit 6 Op W egister File 8 op 6 [:6] fnct 6 [:] COC 6 +[-8] egst Src Src Jmp ranch em ata emory em emtoeg dd [ ] [ 6] [ ] [ 6] [ ] [ ] egst ranch em emtoeg Op em Src egiste [ ] 6 etend left control dd reslt reslt ddress ata Fetch instrction and increment cont -type : Step add $t, $t, $t (active = bold) -type : Step add $t, $t, $t (active = bold) dd [ 6] egst ranch em emtoeg Op em Src left dd reslt dd [ 6] egst ranch em emtoeg Op em Src left dd reslt [ ] [ ] [ 6] [ ] [ ] egiste [ ] 6 etend control reslt ddress ata [ ] [ ] [ 6] [ ] [ ] egiste [ ] 6 etend control reslt ddress ata two sorce s from the file operates on the two operands

8 dd -type : Step add $t, $t, $t (active = bold) [ 6] egst ranch em emtoeg Op em Src left dd reslt mplementation: lock Op Fnct field Op Op F F F F F F * *ypo in tet Fig..: if it is then there is potential conflict between line and lines -7! h table for control bits [ ] [ ] [ 6] [ ] [ ] egiste [ ] 6 etend control reslt ddress ata F ( ) F F F F Op control block Op Op reslt to control logic npts Otpts mplementation: ain lock al - lw sw beq name format Op Op Op Op Op Op egst Src emtoeg em em ranch Op OP h table for main control signals npts Op Op Op Op Op Op -format w sw beq Otpts egst Src emtoeg em em ranch Op OpO ain control PL (programmable logic array): principle nderlying PLs is that any logical epression can be written as a sm-of-prodcts Single-cycle mplementation otes he steps are not really distinct as each instrction completes in eactly one clock cycle they simply indicate the seqence of flowing throgh the path he operation of the path dring a cycle is prely combinational nothing is stored dring a clock cycle herefore, the machine is stable in a paiclar state at the sta of a cycle and reaches a new stable state only at the end of the cycle

9 Load Steps lw $t, offset($t). Fetch instrction and increment. base from the file: the base ($t) is given by bits - of the instrction. comptes sm of vale read from the file and the sign-etended lower 6 bits (offset) of the instrction. he sm from the is sed as the for the. he from the nit is written into the file: the destination ($t) is given by bits -6 of the instrction ranch Steps beq $t, $t, offset. Fetch instrction and increment. two ($t and $t) from the file. performs a sbtract on the vales from the file; the vale of + is added to the signetended lower 6 bits (offset) of the instrction shifted left by two to give the branch target. he reslt from the is sed to decide which adder reslt (from step or ) to store in the Single-Cycle esign Problems ssming fied-period clock every instrction path ses one clock cycle implies: CP = cycle time determined by length of the longest instrction path (load) bt several instrctions cold rn in a shoer clock cycle: waste of time consider if we have more complicated instrctions like floating point! resorces sed more than once in the same cycle need to be dplicated waste of haware and chip area ample: Fied-period clock vs. variable-period clock in a single-cycle implementation Consider a machine with an additional floating point nit. ssme fnctional nit delays as follows : ns., and adde: ns., FP add: 8 ns., FP mltiply: 6 ns., file access (read or write): ns. mltipleo, control nit, accesses, sign etension, wires: no delay ssme instrction mi as follows all loads take same time and comprise % all stores take same time and comprise % -format instrctions comprise 7% branches comprise % jmps comprise % FP adds and sbtracts take the same time and totally comprise 7% FP mltiplys and divides take the same time and totally comprise 7% Compare the performance of (a) a single-cycle implementation sing a fiedperiod clock with (b) one sing a variable-period clock where each instrction eectes in one clock cycle that is only as long as it needs to be (not really practical bt pretend it s possible!)

10 Soltion nstr. egister ata egister FP FP otal class mem. read oper. mem. write add/ ml/ time sb div ns. Load wo 8 Store wo 7 -format 6 ranch Jmp FP ml/div 6 FP add/sb 8 Clock period for fied-period clock = longest instrction time = ns. verage clock period for variable-period clock = 8 % + 7 % + 6 7% + % + % + 7% + 7% = 7. ns. herefore, performance var-period /performance fied-period = /7 =.9 Fiing the problem with singlecycle designs One soltion: a variable-period clock with different cycle times for each instrction class nfeasible, as implementing a variable-speed clock is technically difficlt nother soltion: se a smaller cycle time have different instrctions take different nmbe of cycles by breaking instrctions into steps and fitting each step into one cycle feasible: mlticyle approach! lticycle pproach reak p the instrctions into steps each step takes one clock cycle balance the amont of work to be done in each step/cycle so that they are abot eqal restrict each cycle to se at most once each major fnctional nit so that sch nits do not have to be replicated fnctional nits can be shared between different cycles within one instrction etween steps/cycles t the end of one cycle store to be sed in later cycles of the same instrction need to introdce additional internal (programmer-invisible) s for this prpose ata to be sed in later instrctions are stored in programmervisible state elements: the file,, ote paiclarities of mlticyle vs. singlediagrams single for and instrctions single, no etra adde etra s to hold between clock cycles lticycle pproach dd ddress emory ata or egiste 6 etend left Src Single-cycle path emory ata egister # egiste egister # egister # dd reslt operation reslt Src ddress em em ata Ot emtoeg lticycle path (high-level view)

11 lticycle atapath reaking instrctions into steps ddress emory emata [ ] [ 6] [ ] [ ] emory [ ] 6 egiste etend left reslt Ot Or goal is to break p the instrctions into steps so that each step takes one clock cycle the amont of work to be done in each step/cycle is abot eqal each cycle ses at most once each major fnctional nit so that sch nits do not have to be replicated fnctional nits can be shared between different cycles within one instrction ata at end of one cycle to be sed in net mst be stored!! asic mlticycle PS path handles -type instrctions and load/stores: new internal in red ovals, new mltipleo in ble ovals reaking instrctions into steps Step : Fetch & ncrement (F) We break instrctions into the following potential eection steps not all instrctions reqire all the steps each step takes one clock cycle. fetch and increment (F). decode and fetch (). ection, comptation, or branch completion (). emory access or -type instrction completion (). emory read completion (W) se to get instrction and pt it in the instrction. ncrement the by and pt the reslt back in the. Can be described sccinctly sing L (egister-ransfer Langage): = emory[]; = + ; = egister ach PS instrction takes from cycles (steps)

12 Step : ecode and egister Fetch () s and in case we need them. Compte the branch in case the instrction is a branch. L: = eg[[-]]; = eg[[-6]]; Ot = + (sign-etend([-]) << ); Step : ection, ddress Comptation or ranch Completion () performs one of for fnctions depending on instrction type reference: Ot = + sign-etend([-]); -type: Ot = op ; branch (instrction completes): if (==) = Ot; jmp (instrction completes): = [-8] ((-) << ) Step : emory access or - type Completion () gain depending on instrction type: Loads and stores access load = emory[ot]; = emory ata egister store (instrction completes) emory[ot] = ; -type (instrctions completes) eg[[-]] = Ot; Step : emory Completion (W) gain depending on instrction type: Load writes back (instrction completes) eg[[-6]]= ; mpoant: here is no reason from a path (or control) point of view that Step cannot be eliminated by performing eg[[-6]]= emory[ot]; for loads in Step. his wold eliminate the as well. he reason this is not done is that, to keep steps balanced in length, the design restriction is to allow each step to contain at most one operation, or one access, or one access.

13 Smmary of ection lticycle ection Step (): Fetch Step : F : : Step name fetch decode/ fetch ction for -type instrctions ction for -reference ction for instrctions branches = emory[] = + = eg [[-]] = eg [[-6]] Ot = + (sign-etend ([-]) << ) ction for jmps ection, Ot = op Ot = + sign-etend if ( ==) then = [-8] comptation, branch/ ([-]) = Ot ([-]) jmp completion emory access or -type eg [[-]] = Load: = emory[ot] : completion Ot or Store: emory [Ot] = : W emory read completion Load: eg[[-6]] = + = emory[]; = + ; em emory em W egiste = egister = emory ata egister O st be lticycle ection Step (): ecode & egister Fetch = eg[[-]]; ( = eg[]) = eg[[-]]; ( = eg[]) Ot = ( + sign-etend([-]) << ) * lticycle ection Step (): emory eference s Ot = + sign-etend([-]); + em emory em eg[] W egiste eg[] * ranch arget ddress O + em emory em eg[] W egiste eg[] em. ddress O

14 lticycle ection Step (): (-ype) Ot = op lticycle ection Step (): ranch s if ( == ) = Ot; + em emory em eg[] W egiste eg[] -ype eslt O ranch arget ddress em emory em eg[] W egiste eg[] ranch arget ddress O lticycle ection Step (): Jmp = [-8] concat ([-] << ) lticycle ection Step (): emory ccess - (lw) = emory[ot]; Jmp ddress em emory em eg[] W egiste eg[] ranch arget ddress O + em emory em em. ata W egiste eg[] eg[] em. ddress O

15 lticycle ection Step (): emory ccess - (sw) emory[ot] = ; lticycle ection Step (): (-ype) eg[[:]] = O + em emory em eg[] W egiste eg[] O + em emory em eg[] W egiste eg[] -ype eslt O lticycle ection Step (): emory Completion (lw) eg[[-6]] = ; lticycle atapath with or em em egst Src + em emory em em. ata W egiste eg[] eg[] em. ddress O ddress emory emata [ ] [ 6] [ ] [ ] emory [ ] 6 egiste [ ] etend left control reslt Ot emtoeg Src Op with control lines and the control block added not all control lines are shown

16 lticycle atapath with ew gates For the jmp ew mltipleor lticycle Step (): Fetch Cond or em em emtoeg Otpts Sorce Op Src Src = emory[]; = + ; ddress emory emata [-6] [ ] [ 6] [ ] [ ] emory [ ] [ ] Op [ ] egst 6 egiste etend Complete mlticycle PS path (with branch and jmp capability) and showing the main control block and all control lines [ ] left 6 8 control left [-8] reslt Jmp [-] Ot Wr* or em emory em emtoeg immediate W egiste 6 jmpaddr [:] egst 8 COC Src Src O Sorce lticycle Step (): ecode & egister Fetch lticycle Step (): emory eference s Wr* or = eg[[-]]; ( = eg[]) = eg[[-]]; ( = eg[]) Ot = ( + sign-etend([-]) << ); em emory em emtoeg immediate W egiste 6 jmpaddr [:] egst 8 COC Src Src O Sorce Wr* or Ot = + sign-etend([-]); em emory em egst emtoeg immediate W egiste 6 jmpaddr [:] 8 COC Src Src O Sorce

17 lticycle Step (): (-ype) lticycle Step (): ranch s Ot = op ; if ( == ) = Ot; Wr* or em emory em egst emtoeg immediate W egiste 6 jmpaddr [:] 8 COC??? Src Src O Sorce if = Wr* or em emory em egst emtoeg immediate W egiste 6 jmpaddr [:] 8 COC Src Src O Sorce lticycle ection Step (): Jmp = [-8] concat ([-] << ); lticycle Step (): emory ccess - (lw) = emory[ot]; Wr* or em emory em egst emtoeg immediate W egiste 6 jmpaddr [:] 8 COC Src Src O Sorce Wr* or em emory em egst emtoeg immediate W egiste 6 jmpaddr [:] 8 COC Src Src O Sorce

18 lticycle ection Steps () emory ccess - (sw) emory[ot] = ; lticycle Step (): (-ype) eg[[:]] = Ot; (eg[d] = Ot) Wr* or em emory em egst emtoeg immediate W egiste 6 jmpaddr [:] 8 COC Src Src O Sorce Wr* or em emory em emtoeg immediate jmpaddr [:] egst W egiste 6 8 COC Src Src O Sorce lticycle ection Steps () emory Completion (lw) Simple Qestions eg[[-6]] = ; How many cycles will it take to eecte this code? Wr* or em emory em egst emtoeg immediate W egiste 6 jmpaddr [:] 8 COC Src Src O Sorce lw $t, ($t) lw $t, ($t) beq $t, $t, Label #assme not eqal add $t, $t, $t sw $t, 8($t) Label:... What is going on dring the 8th cycle of eection? Clock time-line n what cycle does the actal addition of $t and $t takes place?

19 mplementing eview: Finite State achines Vale of control signals is dependent pon: what instrction is being eected which step is being performed Finite state machines (FSs): a set of states and net state fnction, determined by crrent state and the inpt otpt fnction, determined by crrent state and possibly inpt se the information we have accmlated to specify a finite state machine specify the finite state machine graphically, or se microprogramming npts Crrent state Clock et-state fnction et state mplementation is then derived from the specification Otpt fnction Otpts We ll se a oore machine otpt based only on crrent state Sta ample: oore achine he oore machine below, given inpt a binary string terminated by #, will otpt even if the string has an even nmber of s and odd if the string has an odd nmber of s ven state o otpt Otpt even Odd state o otpt # # Otpt odd FS : High-level View sseed signals shown inside state circles emory access instrctions (Figre.8) Sta Sta emory reference FS (Figre.8) fetch/decode and fetch (Figre.7) -type instrctions (Figre.9) ranch instrction (Figre.) High-level view of FS control (Op = 'LW') or (Op = 'SW') fetch em Src = or = Src = Op = Sorce = -type FS (Figre.9) (Op = -type) ranch FS (Figre.) Jmp instrction (Figre.) (Op = 'Q') decode/ egister fetch Src = Src = Op = (Op = 'JP') Jmp FS (Figre.) Otpt even state Otpt odd state fetch and decode steps of every instrction is identical

20 FS : emory eference From state Src = Src = Op = (Op = 'LW') or (Op = 'SW') emory comptation FS : -type From state (Op = -type) ection 6 (Op = 'LW') emory access (Op = 'SW') emory access Src = Src = Op = em or = -back step em or = 7 egst = emtoeg = -type completion emtoeg = egst = o state (Figre.7) FS control for -reference has states o state (Figre.7) FS control to implement -type instrctions has states FS : ranch FS : Jmp 8 From state (Op = 'Q') Src = Src = Op = Cond Sorce = ranch completion 9 From state (Op = 'J') Sorce = Jmp completion o state (Figre.7) FS control to implement branches has state o state (Figre.7) FS control to implement jmps has state

21 W FS : Complete View emory comptation Src = Src = Op = (Op = 'LW') em or = emory access egst = emtoeg = (Op = 'SW') -back step Sta (Op = 'LW') or (Op = 'SW') em or = F emory access 6 7 fetch em Src = or = Src = Op = Sorce = ection Src = Src = Op= egst = emtoeg = 8 -type completion (Op = -type) ranch completion Src = Src = Op = Cond Sorce = (Op = 'Q') decode/ fetch 9 Src = Src = Op = (Op = 'J') Jmp completion Sorce = Labels on arcs are conditions that determine net state he complete FS control for the mlticycle PS path: refer lticycle atapath with ample: CP in a mlticycle CP ssme the control design of the previos slide n instrction mi of % loads, % stores, 9% -type operations, 6% branches, and % jmps What is the CP assming each step reqires clock cycle? Soltion: mber of clock cycles from previos slide for each instrction class: loads, stores, -type instrctions, branches, jmps CP = CP clock cycles / instrction cont = Σ (instrction cont class i CP class i ) / instrction cont = Σ (instrction cont class / instrction cont) CP class = =. FS : mplementation Op Op Op Cond or em emtoeg Sorce Op Src Src egst High-level view of FS implementation: inpts to the combinational logic block are the crrent state nmber and instrction opcode bits; otpts are the net state nmber and control signals to be asseed for the crrent state Op Op opcode field logic npts Op For state bits are reqired for states S S Otpts S S State em S S S S FS : PL mplementation Op Op Op Op Op Op S S S S Cond or em em emtoeg Sorce Sorce Op Op Src Src Src egst S S S pper half is the plane that comptes all the prodcts. he prodcts are carried to the lower O plane by the veical lines. he sm terms for each otpt is given by the corresponding horizontal line.g., or = S.S.S.S + S.S.S.S S

22 FS : O mplementation O ( Only emory) vales of locations are fied ahead of time O can be sed to implement a th table if the is m-bits, we can m entries in the O otpts are the bits of the entry the points to m n O m = n = otpt he size of an m-inpt n-otpt O is m n bits sch a O can be thoght of as an array of size m with each entry in the array being n bits FS : O vs. PL Fit improve the O: break the table into two pas state bits give the 6 otpt signals 6 bits of O all inpt bits give the net state bits bits of O otal.k bits of O PL is mch smaller can share prodct terms only need entries that prodce an active otpt can take into accont don't cares PL size = (#inpts #prodct-terms) + (#otpts #prodctterms) FS control PL = (7)+(7) = 6 PL cells PL cells sally abot the size of a O cell (slightly bigger) icroprogramming icroprogramming is a method of specifying FS control that resembles a programming langage tetal rather graphic this is appropriate when the FS becomes very large, e.g., if the instrction set is large and/or the nmber of cycles per instrction is large in sch sitations graphical representation becomes difficlt as there may be thosands of states and even more arcs joining them a microprogram is specification : implementation is by O or PL microprogram is a seqence of microinstrctions each microinstrction has eight fields (label + 7 fnctional) Label: sed to control microcode seqencing control: specify operation to be done by SC: specify sorce for fit operand SC: specify sorce for second operand egister control: specify read/write for file emory: specify read/write for control: specify the writing of the Seqencing: specify choice of net microinstrction icroprogramming he Seqencing field vale determines the eection oer of the microprogram vale Seq : control passes to the seqentially net microinstrction vale Fetch : branch to the fit microinstrction to begin the net PS instrction, i.e., the fit microinstrction in the microprogram vale ispatch i : branch to a microinstrction based on control inpt and a dispatch table entry (called dispatching): ispatching is implemented by means of creating a table, called dispatch table, whose entries are microinstrction labels and which is indeed by the control inpt. here may be mltiple dispatch tables the vale ispatch i in the seqencing field indicates that the i th dispatch table is to be sed

23 icroprogram he microprogram corresponding to the FS control shown graphically earlier: Label control SC SC egister control em ory W rite control Seqencing Fetch dd Seq dd tshft ispatch em dd tend ispatch LW Seq Fetch SW Fetch format Fnc code Seq Fetch Q Sbt O t-cond Fetch JP Jmp Fetch icroprogram containing microinstrctions ispatch O Op Opcode name Vale -format format jmp JP beq Q lw em sw em ispatch able ispatch O Op Opcode name Vale lw LW sw SW ispatch able icrocode: rade-offs Specification advantages easy to design and write typically manfactrer designs architectre and microcode in parallel mplementation advantages easy to change since vales are in (e.g., off-chip O) can emlate other architectres can make se of internal s mplementation disadvantages control is implemented nowadays on same chip as processor so the advantage of an off-chip O does not eist O is no longer faster than on-boa cache there is little need to change the microcode as general-prpose compte are sed far more nowadays than compte designed for specific applications Smmary echniqes described in this chapter to design paths and control are at the core of all modern compter architectre lticycle paths offer two great advantages over single-cycle fnctional nits can be resed within a single instrction if they are accessed in different cycles redcing the need to replicate epensive logic instrctions with shoer eection paths can complete qicker by consming fewer cycles odern compte, in fact, take the mlticycle paradigm to a higher level to achieve greater instrction throghpt: pipelining (net topic) where mltiple instrctions eecte simltaneosly by having cycles of different instrctions overlap in the path the PS architectre was designed to be pipelined