Recap: Processor Design is a Process. CS 152 Computer Architecture and Engineering Lecture 10. Designing a Multicycle Processor

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1 Recap: rocessor Design is a rocess 52 omputer rchitecture and ngineering Lecture Designing a ulticycle rocessor ottom-up assemble components in target technology to establish critical timing Top-down specify component behavior from high-level requirements Iterative refinement establish partial solution, epand and improve et rchitecture datapath processor control. u LU Decoder equencer Lec. ells Gates Lec.2 Recap: ingle ycle path Rd Rt Dst u Rs Rt Wr busw lk imm6 Rw Ra Rb -bit isters 6 bus tender bus top n_sel lk u LUrc Unit LUctr LU In lk <3:> Rt qual <2:25> Rs <6:2> Wr Wrn dr ory Rd <:5> <:5> Imm6 u to Lec.3 Recap: The Truth Table for the ain ontrol op 6 Dst LUrc to Write Write ranch Jump top ain ontrol LUop (ymbolic) Dst LUrc : LUop R-type ori lw sw beq jump 3 R-type Or LUop <> Lec.4 dd func op dd ubtract LUop <2> LUop <> 6 LU ontrol (Local) LUctr 3

2 Recap: L Implementation of the ain ontrol <> <> <> <> <> R-type ori lw sw beq jump op<> Write LUrc Dst to Write ranch Jump top LUop<2> LUop<> LUop<> Lec.5 Recap: ystematic Generation of ontrol Decode Ocode onditions path ontrol Logic / tore (L, RO) ontrol oints In our single-cycle processor, each ruction is realized by eactly one control command or microruction in general, the controller is a finite state machine microruction microruction can also control sequencing (see later) Lec.6 The ig icture: Where are We Now? The Five lassic omponents of a omputer rocessor ontrol path ory Input Output Today s Topic: Designing the path for the ultiple lock ycle path Lec.7 ehavioral models of path omponents entity adder6 is generic (ccout_delay : TI := 2 ns; adderout_delay: TI := 2 ns); port(, : in std_logic_vector (5 downto ); DOUT: out std_logic_vector (5 downto ); IN: in std_logic; OUT: out std_logic); architecture behavior of adder is end adder6; begin adder6_process: process(,, IN) out 6 6 DOUT 6 in variable tmp : std_logic_vector (8 downto ); variable adder_out : std_logic_vector (3 downto ); variable carry : std_logic; begin tmp := addum (addum(, ), IN); adder_out := tmp(5 downto ); carry :=tmp(6); OUT <= carry after ccout_delay; DOUT <= adder_out after adderout_delay; end process; end behavior; Lec.8

3 ehavioral pecification of ontrol Logic bstract View of our single cycle processor entity maincontrol is port(opcode: in std_logic_vector (5 downto ); LUop out std_logic_vector ( downto ); equal_cond: etop LUsrc wr to Wr Dst n end maincontrol; in std_logic; architecture behavior of maincontrol is begin control: process(opcode,equal_cond) constant ORIop: std_logic_vector (5 downto ) := ; begin -- etop only (no etend) for ORI case opcode is when ORIop=> etop <= ; when others => etop <= ; end case; end process; end behavior; Decode / ontrol-store address modeled by ase statement n_sel Net op fun qual ister ain ontrol top LUrc LUctr t LU LU control Rd Wr ccess Dst Wr Wr. Wrt Result tore ach arm of case drives control signals for that operation just like the microruction either can be symbolic Lec.9 looks like a F with as state Lec. What s wrong with our I= processor? rithmetic & Logical Inst ory mu LU mu setup Load Inst ory mu LU musetup ritical ath tore Inst ory mu LU ranch Inst ory cmp mu Long ycle ll ructions take as much time as the slowest Real memory is not as nice as our idealized memory cannot always get the job done in one (short) cycle Lec. ory ccess hysics => fast memories are small (large memories are slow) address question: register file vs. memory => Use a hierarchy of memories rocessor address decoder ache proc. bus torage rray L2 ache selected word line storage cell bit line sense amps time-period 2-5 time-periods 2-3 time-periods Lec.2 mem. bus memory

4 Reducing ycle asic Limits on ycle ut combinational dependency graph and insert register / latch Do same work in two fast cycles, rather than one slow one ay be able to short-circuit path and remove some components for some ructions! cyclic ombinational Logic cyclic ombinational Logic () Net address logic <= branch? + offset : + 4 <= [] ister ccess <= R[rs] LU operation R <= + ontrol n_sel top LUrc LUctr Rd Wr Dst Wr Wr cyclic ombinational Logic () Lec.3 Net Operand ec ccess. Result tore Lec.4 artitioning the I= path dd registers between smallest steps ample ulticycle path Net n_sel Operand qual top LUrc LUctr ec Rd Wr ccess Dst Wr. Wr Result tore n_sel Net Operand qual top LUrc LUctr t LU Rd Wr ccess To Dst Wr. Result tore lace enables on all registers ritical ath? Lec.5 Lec.6

5 Recall: tep-by-step rocessor Design tep : I => Logical ister Transfers tep 2: omponents of the path tep 3: RTL + omponents => path tep 4: path + Logical RTs => hysical RTs tep 4: R-rtype (add, sub,.) Logical ister Transfer Logical ister Transfers DDU R[rd] < R[rs] + R[rt]; < + 4 hysical ister Transfers hysical ister Transfers < [pc] DDU < R[rs]; < R[rt] < + R[rd] < ; < + 4 tep 5: hysical RTs => ontrol Net Inst. ec ccess. Lec.7 Lec.8 tep 4: Logical immed tep 4 : Load Logical ister Transfer Logical ister Transfers ORI R[rt] < R[rs] OR Zt(Im6); < + 4 hysical ister Transfers hysical ister Transfers < [pc] ORI < R[rs]; < R[rt] < or Zt(Im6) R[rt] < ; < + 4 Logical ister Transfer hysical ister Transfers Logical ister Transfers R[rt] < [R[rs] + t(im6)]; < + 4 hysical ister Transfers < [pc] < R[rs]; < R[rt] < + t(im6) < [] R[rd] < ; < + 4 Net Inst. ec ccess. Net Inst. ec ccess. Lec.9 Lec.2

6 tep 4 : tore Logical ister Transfer hysical ister Transfers W W Logical ister Transfers [R[rs] + t(im6)] < R[rt]; < + 4 hysical ister Transfers < [pc] < R[rs]; < R[rt] < + t(im6); [] < < + 4 tep 4 : ranch Logical ister Transfer hysical ister Transfers Logical ister Transfers Q if R[rs] == R[rt] then <= + 4+t(Im6) else <= + 4 hysical ister Transfers < [pc] Q < (R[rs] = R[rt]) if then < + 4 +t(im6) else < +4 Net Inst. ec ccess. Net Inst. ec ccess. Lec.2 Lec.22 Our ontrol odel tep 4 ontrol pecification for multicycle proc tate specifies control points for ister Transfer Transfer occurs upon eiting state (same falling edge) <= [] ruction fetch inputs (conditions) <= R[rs] <= R[rt] decode / operand fetch Net tate Logic ontrol tate tate X ister Transfer ontrol oints R-type ORi <= fun <= or ZX <= + X W Q <= + X <= Net(,qual) ecute Output Logic Depends on Input <= [] [] <= <= + 4 ory outputs (control points) Lec.23 R[rd] <= <= + 4 R[rt] <= <= + 4 R[rt] <= <= + 4 Lec.24 Write-back

7 Traditional F ontroller tep 5 (datapath + state diagram control) state op cond net state control points Translate RTs into control points ssign states Then go build the controller Truth Table qual 6 net tate control points 4 tate datapath tate op Lec.25 Lec.26 apping RTs to ontrol oints ssigning tates <= [] imem_rd, en ruction fetch <= [] ruction fetch <= R[rs] <= R[rt] en, en, en decode <= R[rs] <= R[rt] decode R-type ORi <= fun LUfun, en <= or ZX <= + X W <= + X Q <= Net(,qual) ecute R-type ORi <= fun <= or ZX <= + X W Q <= + X <= Net() ecute R[rd] <= <= + 4 Dst, Wr, en R[rt] <= <= + 4 <= [] R[rt] <= <= + 4 [] <= <= + 4 Lec.27 ory Write-back R[rd] <= <= + 4 R[rt] <= <= + 4 <= [] R[rt] <= <= + 4 [] <= <= + 4 Lec.28 ory Write-back

8 (ostly) Detailed ontrol pecification (missing ) tate Op field q Net Ops ec Write-ack en sel r LU R W -R Wr Dst??????? Q R-type ORI W -all same in oore machine Q: R: fun ORi: or : add W: add Lec.29 erformance valuation What is the average I? state diagram gives I for each ruction type workload gives frequency of each type Type I i for type Frequency I i freqi i rith/logic 4 4%.6 Load 5 3%.5 tore 4 %.4 branch 3 2%.6 verage I:4. Lec.3 How ffectively are we utilizing our hardware? rinceton Organization < + < or ZX <- [] <- R[rs ]; < R[rt] < + X < + X net ZX X -us us W-us R[rd] < ; < +4; R[rt] < ; < +4; ample: memory is used twice, at different times ve mem access per = +Flw + Fsw ~.3 if I is 4.8, imem utilization = /4.8, dmem =.3/4.8 We could reduce HW without hurting performance etra control < [] R[rd] < ; < +4; [] <- < +4; < +4; < +X; Lec.3 ingle memory for ruction and data access memory utilization ->.3/4.8 ometimes, mues replaced with tri-state buses Difference often depends on whether buses are internal to chip (mues) or eternal (tri-state) In this case our state diagram does not change several additional control signals must ensure each bus is only driven by one source on each cycle Lec.

9 nother lternative ultiycle ath What about a 2-us icroarchitecture (datapath)? -us net mem mem ZX X In each clock cycle, each us can be used to transfer from one source µ-ruction can simply contain -us and W-Dst fields us W-us net ZX X Decode / Operand -us us net ZX X Lec.33 Lec.34 Load ecute ummary net ZX X Disadvantages of the ingle ycle rocessor Long cycle time ycle time is too long for all ructions ecept the Load net ZX X addr ultiple ycle rocessor: Divide the ructions into smaller steps ecute each step (ead of the entire ruction) in one cycle Write-back net ZX X artition datapath into equal size chunks to minimize cycle time ~ levels of logic between latches Follow same 5-step method for designing real processor What about bus? adder? ister port? Lec.35 Lec.36