Recap: Processor Design is a Process. CS 152 Computer Architecture and Engineering Lecture 9. Designing a Multicycle Processor

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1 Recap: Processor Design is a Process C 52 Computer rchitecture and Engineering Lecture 9 Designing a ulticycle Processor Feb 24, 999 John Kubiatowicz (http.cs.berkeley.edu/~kubitron) lecture slides: ottom-up assemble components in target technology to establish critical timing Top-down specify component behavior from high-level requirements Iterative refinement establish partial solution, epand and improve et rchitecture datapath processor control u LU Decoder equencer Lec9. Cells Gates Lec9.2 Recap: ingle Cycle path busw Clk Rd Rt u Rs Rt Wr imm6 Rw Ra Rb -bit isters 6 bus Etender bus LUctr EtOp n_sel Clk u Unit LU In Clk Zero <3:> Rt <2:25> Rs <6:2> Wr WrEn dr ory Rd <:5> <:5> Imm6 u to Lec9.3 Recap: The Truth Table for the ain op 6 ain to Write Write ranch Jump EtOp LUop (ymbolic) : LUop 3 op R-type ori lw sw beq jump R-type Or dd dd LU (Local) ubtract LUop <2> LUop <> LUop <> Lec9.4 func 6 LUctr 3

2 Recap: PL Implementation of the ain op<5>. op<5> op<5>.. op<5>.. op<5>.. op<5>..... <> <> <> <> <> R-type ori lw sw beq jump op<> Write to Write ranch Jump EtOp LUop<2> LUop<> LUop<> Lec9.5 Recap: ystematic Generation of Decode OPcode Conditions path Logic / tore (PL, RO) Points In our single-cycle processor, each instruction is realized by eactly one control command or microinstruction in general, the controller is a finite state machine microinstruction can also control sequencing (see later) microinstruction Lec9.6 The ig Picture: Where are We Now? The Five Classic Components of a Computer Processor Input ory path Output Outline of Today s Lecture Recap: single cycle processor VHDL versions Faster designs ulticycle path Performance nalysis ulticycle Today s Topic: Designing the path for the ultiple Clock Cycle path Lec9.7 Lec9.8

3 ehavioral models of path Components entity adder6 is generic (ccout_delay : TIE := 2 ns; adderout_delay: TIE := 2 ns); port(, : in vlbit_d(5 downto ); DOUT: out vlbit_d(5 downto ); CIN: in vlbit; COUT: out vlbit); end adder6; architecture behavior of adder is begin adder6_process: process(,, CIN) variable tmp : vlbit_d(8 downto ); variable adder_out : vlbit_d(3 downto ); variable carry: vlbit; 6 6 Cout Cin begin tmp := addum (addum (, ), CIN); adder_out := tmp(5 downto ); 6 carry :=tmp(6); DOUT COUT <= carry after ccout_delay; DOUT <= adder_out after adderout_delay; end process; end behavior; Lec9.9 ehavioral pecification of Logic entity maincontrol is port(opcode: in vlbit_d(5 downto ); equal_cond: in vlbit; etop out vlbit; LUsrc out vlbit; LUop out vlbit_d( downto ); Ewr out vlbit; to out vlbit; Wr n end maincontrol; out vlbit; out vlbit; out vlbit; Decode / -store address modeled by Case statement Each arm drives control signals for that operation just like the microinstruction either can be symbolic architecture behavior of maincontrol is begin control: process(opcode,equal_cond) constant ORIop: vlbit_ld(5 downto ) := ; begin -- etop only (no etend) for ORI inst case opcode is when ORIop => etop <= ; when others => etop <= ; end case; end process; end behavior; Lec9. bstract View of our single cycle processor What s wrong with our CPI= processor? op ain rithmetic & Logical Inst ory mu LU mu setup n_sel Net fun Equal ister EtOp Et looks like a F with as state LUctr LU LU control Rd Wr Wr Wrt Wr Result tore Load Inst ory mu LU musetup Critical Path tore Inst ory mu LU ranch Inst ory cmp mu Long Cycle Time ll instructions take as much time as the slowest Real memory is not as nice as our idealized memory cannot always get the job done in one (short) cycle Lec9. Lec9.2

4 ory Time Physics => fast memories are small (large memories are slow) torage rray address address decoder question: register file vs. memory => Use a hierarchy of memories Processor Cache proc. bus L2 Cache selected word line storage cell bit line sense amps cycle 2-3 cycles 2-5 cycles Lec9.3 mem. bus memory Reducing Cycle Time Cut combinational dependency graph and insert register / latch Do same work in two fast cycles, rather than one slow one ay be able to short-circuit path and remove some components for some instructions! storage element storage element cyclic Combinational Logic storage element cyclic Combinational Logic () storage element cyclic Combinational Logic () storage element Lec9.4 asic Limits on Cycle Time Partitioning the CPI= path Net address logic <= branch? + offset : + 4 dd registers between smallest steps <= [] ister <= R[rs] LU operation R <= + n_sel Net Operand EtOp LUctr Eec Rd Wr Wr Wr Result tore n_sel Net Operand Equal EtOp LUctr Eec Rd Wr Wr Wr Result tore Lec9.5 Lec9.6

5 Eample ulticycle path dministrative Issues Read Chapter 5 n_sel Net Operand E Equal EtOp LUctr Et LU Rd Wr To Wr Result tore Tapes now available in 25 claughlin Hall This lecture and net one slightly different from the book idterm net Wednesday 3/3/99: 5:3pm to 8:3pm, 277 Cory No class on that day idterm reminders: Pencil, calculator, one 8.5 (both sides) of handwritten notes it in every other chair, every other row (odd row & odd seat) eet at LaVal s pizza after the midterm Critical Path? Lec9.7 Lec9.8 Recall: tep-by-step Processor Design tep : I => Logical ister Transfers tep 2: Components of the path tep 3: RTL + Components => path tep 4: path + Logical RTs => Physical RTs tep 5: Physical RTs => tep 4: R-rtype (add, sub,...) Logical ister Transfer inst Logical ister Transfers DDU R[rd] < R[rs] + R[rt]; < + 4 Physical ister Transfers inst Physical ister Transfers Time < E[pc] DDU < R[rs]; < R[rt] < + R[rd] < ; < + 4 E Net Inst. Eec Lec9.9 Lec9.2

6 tep 4: Logical immed tep 4 : Load Logical ister Transfer inst Logical ister Transfers ORI R[rt] < R[rs] OR ZEt(Im6); < + 4 Physical ister Transfers inst Physical ister Transfers Time < E[pc] ORI < R[rs]; < R[rt] < or ZEt(Im6) R[rt] < ; < + 4 Logical ister Transfer Physical ister Transfers Time inst inst Logical ister Transfers R[rt] < E[R[rs] + Et(Im6)]; < + 4 Physical ister Transfers < E[pc] < R[rs]; < R[rt] < + Et(Im6) < E[] R[rd] < ; < + 4 Net Inst. E Eec Net Inst. E Eec Lec9.2 Lec9.22 tep 4 : tore Logical ister Transfer Physical ister Transfers Time inst inst Logical ister Transfers E[R[rs] + Et(Im6)] < R[rt]; < + 4 Physical ister Transfers < E[pc] < R[rs]; < R[rt] < + Et(Im6); E[] < < + 4 tep 4 : ranch Logical ister Transfer Physical ister Transfers Time inst Logical ister Transfers EQ if R[rs] == R[rt] then <= + Et(Im6) else inst Physical ister Transfers < E[pc] EQ E< (R[rs] == R[rt]) if E then < + 4 else < + Et(Im6) Net Inst. E Eec Net Inst. E Eec Lec9.23 Lec9.24

7 lternative datapath (book): ultiple Cycle path iminizes Hardware: memory, adder Wr WrCond rc rwr Zero IorD Wr Wr Wr LUel Target u Rdr Ideal ory Wrdr Din Dout Rs Rt 5 5 Rt Rd u u Ra Rb bus 4 Rw busw bus << 2 u 2 3 u Zero LU LU LU Out Our odel tate specifies control points for ister Transfer Transfer occurs upon eiting state (same falling edge) inputs (conditions) Net tate Logic tate Output Logic tate X ister Transfer Points Depends on Input Imm Etend 6 EtOp to LUel LUOp outputs (control points) Lec9.25 Lec9.26 tep 4 => pecification for multicycle proc Traditional F ler <= E[] instruction fetch state op cond net state control points <= R[rs] <= R[rt] decode / operand fetch R-type ORi <= fun <= or ZX <= + X <= E[] EQ <= + X <= Net(,Equal) E[] <= Eecute ory Truth Table Equal 6 net tate control points R[rd] <= R[rt] <= R[rt] <= Write-back Lec tate op 2/24/99 datapath tate UC pring 999 Lec9.28

8 tep 5: datapath + state diagram control Translate RTs into control points ssign states Then go build the controller apping RTs to Points <= E[] imem_rd, en <= R[rs] <= R[rt] en, en, Een instruction fetch decode R-type ORi <= fun LUfun, en <= or ZX <= + X EQ <= + X <= Net(,Equal) Eecute Lec9.29 R[rd] <=, Wr, en R[rt] <= <= E[] R[rt] <= E[] <= ory Write-back Lec9.3 ssigning tates R-type <= fun R[rd] <= ORi <= or ZX R[rt] <= <= E[] <= R[rs] <= R[rt] <= + X <= E[] R[rt] <= instruction fetch decode EQ <= + X <= Net() E[] <= Eecute ory Write-back Lec9.3 Detailed pecification tate Op field Eq Net Ops Eec Write-ack en sel E r LU R W -R Wr Dst??????? EQ R-type ori -all same in oore machine EQ: R: fun ORi: or : add : add Lec9.

9 Performance Evaluation What is the average CPI? state diagram gives CPI for each instruction type workload gives frequency of each type Type CPI i for type Frequency CPI i freqi i rith/logic 4 4%.6 Load 5 3%.5 tore 4 %.4 branch 3 2%.6 verage CPI:4. ler Design The state digrams that arise define the controller for an instruction set processor are highly structured Use this structure to construct a simple microsequencer reduces to programming this very simple device microprogramming sequencer control microinstruction datapath control micro- sequencer Lec9.33 Lec9.34 Eample: Jump-Counter Using a Jump Counter op-code ap RO Counter zero inc load i i+ None of above: Do nothing (for wait states) i Lec9.35 <= E[] inc instruction fetch <= R[rs] decode <= R[rt] load R-type ORi EQ <= fun <= or ZX <= + X <= + X <= Net() inc inc inc inc <= E[] E[] <= inc R[rd] <= R[rt] <= R[rt] <= zero zero zero 2/24/99 zero UC pring 999 zero Eecute ory Write-back Lec9.36

10 Our icrosequencer icroprogram pecification µ Taken Net Ops Eec Write-ack en sel E r LU R W -R Wr Dst? inc load taken op-code icro- ap RO Z I L datapath control EQ R: ORi: : : zero zero inc fun zero inc or zero inc add inc zero inc add zero Lec9.37 Lec9.38 apping RO Eample: ling ory R-type EQ ori addr ory data Inst. Inst_rd I_wait _en Lec9.39 Lec9.4

11 ler handles non-ideal memory Really imple Time-tate R-type ORi <= fun <= or ZX <= E[] ~wait <= R[rs] <= R[rt] <= + X instruction fetch wait decode / operand fetch EQ <= <= + X Net() Eecute instruction fetch Eecute decode R-type ORi <= fun <= or ZX <= E[] ~wait <= R[rs] <= R[rt] <= + X wait <= + X EQ R[rd] <= R[rt] <= <= E[] ~wait wait R[rt] <= E[] <= ~wait wait ory Write-back Lec9.4 write-back ory R[rd] <= R[rt] <= <= E[] R[rt] <= wait E[] <= wait <= Net() Lec9.42 Time-state Path Overview of Local decode and control at each stage Valid Inst. Dcd Ctrl e E Ctrl mem Ctrl wb W Ctrl may be designed using one of several initial representations. The choice of sequence control, and how logic is represented, can then be determined independently; the control can then be implemented with one of several methods using a structured logic technique. Initial Representation Finite tate Diagram icroprogram Net Eec Equal equencing Eplicit Net tate icroprogram counter Function + Dispatch ROs Logic Representation Logic Equations Truth Tables Lec9.43 Implementation PL RO Technique hardwired control microprogrammed control Lec9.44

12 ummary ummary (cont d) Disadvantages of the ingle Cycle Processor Long cycle time Cycle time is too long for all instructions ecept the Load ultiple Cycle Processor: Divide the instructions into smaller steps Eecute each step (instead of the entire instruction) in one cycle Partition datapath into equal size chunks to minimize cycle time ~ levels of logic between latches Follow same 5-step method for designing real processor is specified by finite state digram pecialize state-diagrams easily captured by microsequencer simple increment & branch fields datapath control fields design reduces to icroprogramming is more complicated with: comple instruction sets restricted datapaths (see the book) imple set and powerful datapath => simple control could try to reduce hardware (see the book) rather go for speed => many instructions at once! Lec9.45 Lec9.46 Where to get more information? Net two lectures: ultiple Cycle ler: ppendi C of your tet book. icroprogramming: ection 5.5 of your tet book. D. Patterson, icroprograming, cientific merica, arch 983. D. Patterson and D. Ditzel, The Case for the Reduced et Computer, Computer rchitecture News 8, 6 (October 5, 98) Lec9.47